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authorJasper Lievisse Adriaanse <jasper@cvs.openbsd.org>2012-12-21 07:49:50 +0000
committerJasper Lievisse Adriaanse <jasper@cvs.openbsd.org>2012-12-21 07:49:50 +0000
commita35e820400998b878e37bfd59b64a8525b00e462 (patch)
treed0602df2c84a6934e900ec89a3e27b51c78490f0 /sys/dev/pci/pcidevs.h
parent4ed40740a15d9f6d4ef85be6c0dec2e3b8dc7a87 (diff)
regen
Diffstat (limited to 'sys/dev/pci/pcidevs.h')
-rw-r--r--sys/dev/pci/pcidevs.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/sys/dev/pci/pcidevs.h b/sys/dev/pci/pcidevs.h
index f006e995b85..5def7bb1d53 100644
--- a/sys/dev/pci/pcidevs.h
+++ b/sys/dev/pci/pcidevs.h
@@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * OpenBSD: pcidevs,v 1.1661 2012/11/17 15:42:29 kettenis Exp
+ * OpenBSD: pcidevs,v 1.1663 2012/12/21 07:48:51 jasper Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@@ -2392,6 +2392,7 @@
#define PCI_PRODUCT_INTEL_CORE2G_GT2_PLUS 0x0122 /* HD Graphics 3000 */
#define PCI_PRODUCT_INTEL_CORE2G_M_GT2_PLUS 0x0126 /* HD Graphics 3000 */
#define PCI_PRODUCT_INTEL_XEONE3_1200V2_HB 0x0150 /* Xeon E3-1200v2 Host */
+#define PCI_PRODUCT_INTEL_XEONE3_1200V2_PCIE 0x0151 /* Xeon E3-1200v2 PCIE */
#define PCI_PRODUCT_INTEL_CORE3G_D_GT1 0x0152 /* HD Graphics 2500 */
#define PCI_PRODUCT_INTEL_CORE3G_M_HB 0x0154 /* Core 3G Host */
#define PCI_PRODUCT_INTEL_CORE3G_M_GT1 0x0156 /* HD Graphics 2500 */
@@ -2730,6 +2731,7 @@
#define PCI_PRODUCT_INTEL_7SERIES_RAID_1 0x1e04 /* 7 Series RAID */
#define PCI_PRODUCT_INTEL_7SERIES_RAID_2 0x1e06 /* 7 Series RAID */
#define PCI_PRODUCT_INTEL_7SERIES_RAID_3 0x1e07 /* 7 Series RAID */
+#define PCI_PRODUCT_INTEL_7SERIES_SATA_3 0x1e08 /* 7 Series SATA */
#define PCI_PRODUCT_INTEL_7SERIES_RAID_4 0x1e0e /* 7 Series RAID */
#define PCI_PRODUCT_INTEL_7SERIES_PCIE_1 0x1e10 /* 7 Series PCIE */
#define PCI_PRODUCT_INTEL_7SERIES_PCIE_2 0x1e12 /* 7 Series PCIE */
@@ -2750,6 +2752,7 @@
#define PCI_PRODUCT_INTEL_Z75_LPC 0x1e46 /* Z75 LPC */
#define PCI_PRODUCT_INTEL_B75_LPC 0x1e49 /* B75 LPC */
#define PCI_PRODUCT_INTEL_H77_LPC 0x1e4a /* H77 LPC */
+#define PCI_PRODUCT_INTEL_C216_LPC 0x1e53 /* C216 LPC */
#define PCI_PRODUCT_INTEL_QM77_LPC 0x1e55 /* QM77 LPC */
#define PCI_PRODUCT_INTEL_HM77_LPC 0x1e57 /* HM77 LPC */
#define PCI_PRODUCT_INTEL_UM77_LPC 0x1e58 /* UM77 LPC */
@@ -4963,6 +4966,7 @@
#define PCI_PRODUCT_PLX_PEX_8533 0x8533 /* PEX 8533 */
#define PCI_PRODUCT_PLX_PEX_8547 0x8547 /* PEX 8547 */
#define PCI_PRODUCT_PLX_PEX_8548 0x8548 /* PEX 8548 */
+#define PCI_PRODUCT_PLX_PEX_8603 0x8603 /* PEX 8603 */
#define PCI_PRODUCT_PLX_PEX_8612 0x8612 /* PEX 8612 */
#define PCI_PRODUCT_PLX_PEX_8613 0x8613 /* PEX 8613 */
#define PCI_PRODUCT_PLX_PEX_8614 0x8614 /* PEX 8614 */