summaryrefslogtreecommitdiff
path: root/sys/dev/pci/pcidevs.h
diff options
context:
space:
mode:
authorJonathan Gray <jsg@cvs.openbsd.org>2019-01-05 11:50:33 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2019-01-05 11:50:33 +0000
commitad93b37064cbd78b1442a1b19899bae95146892e (patch)
treeaa098762f0be746ca8725c82f5517ac9a247cf52 /sys/dev/pci/pcidevs.h
parente5f1f2996dfa246b20b8b8dd4f9544dcb6ac9225 (diff)
regen
Diffstat (limited to 'sys/dev/pci/pcidevs.h')
-rw-r--r--sys/dev/pci/pcidevs.h67
1 files changed, 66 insertions, 1 deletions
diff --git a/sys/dev/pci/pcidevs.h b/sys/dev/pci/pcidevs.h
index d39c682d191..0b00c486676 100644
--- a/sys/dev/pci/pcidevs.h
+++ b/sys/dev/pci/pcidevs.h
@@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * OpenBSD: pcidevs,v 1.1873 2018/12/18 04:25:16 tedu Exp
+ * OpenBSD: pcidevs,v 1.1874 2019/01/05 11:49:41 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@@ -4634,6 +4634,21 @@
#define PCI_PRODUCT_INTEL_E5_SAD_1 0x3cf4 /* E5 SAD */
#define PCI_PRODUCT_INTEL_E5_BROADCAST 0x3cf5 /* E5 Broadcast */
#define PCI_PRODUCT_INTEL_E5_SAD_2 0x3cf6 /* E5 SAD */
+#define PCI_PRODUCT_INTEL_CORE8G_S_D_HB_2C 0x3e0f /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_H_HB_4C 0x3e10 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_W_HB_4C 0x3e18 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_D_HB_4C 0x3e1f /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_D_HB_8C 0x3e30 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_W_HB_8C 0x3e31 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_S_HB_8C 0x3e32 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_S_HB_4C 0x3e33 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_U_GT3_1 0x3ea5 /* Iris Plus Graphics 655 */
+#define PCI_PRODUCT_INTEL_CORE8G_S_D_HB_6C 0x3ec2 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_H_HB_6C 0x3ec4 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_W_HB_6C 0x3ec6 /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_S_S_HB_6C 0x3eca /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_U_HB_2C 0x3ecc /* Core 8G Host */
+#define PCI_PRODUCT_INTEL_CORE8G_U_HB_4C 0x3ed0 /* Core 8G Host */
#define PCI_PRODUCT_INTEL_CORE8G_S_HB_4C 0x3e1f /* Core 8G Host */
#define PCI_PRODUCT_INTEL_CORE8G_S_PCIE_X16 0x3e81 /* Core 8G PCIE */
#define PCI_PRODUCT_INTEL_CORE8G_S_PCIE_X8 0x3e85 /* Core 8G PCIE */
@@ -4725,6 +4740,7 @@
#define PCI_PRODUCT_INTEL_CORE7G_U_GT1 0x5906 /* HD Graphics 610 */
#define PCI_PRODUCT_INTEL_CORE7G_Y_HB 0x590c /* Core 7G Host */
#define PCI_PRODUCT_INTEL_CORE7G_Y_GT1 0x590e /* HD Graphics */
+#define PCI_PRODUCT_INTEL_CORE7G_S_HB_2C 0x590f /* Core 7G Host */
#define PCI_PRODUCT_INTEL_XEONE3_1200V6_HB2 0x5910 /* Xeon E3-1200 v6/7 Host */
#define PCI_PRODUCT_INTEL_CORE_GMM_2 0x5911 /* Core GMM */
#define PCI_PRODUCT_INTEL_CORE7G_S_GT2 0x5912 /* HD Graphics 630 */
@@ -4737,6 +4753,7 @@
#define PCI_PRODUCT_INTEL_CORE7G_H_GT2 0x591b /* HD Graphics 630 */
#define PCI_PRODUCT_INTEL_CORE7G_U_GT2_2 0x591d /* HD Graphics P630 */
#define PCI_PRODUCT_INTEL_CORE7G_Y_GT2 0x591e /* HD Graphics 615 */
+#define PCI_PRODUCT_INTEL_CORE7G_S_HB_4C 0x591f /* Core 7G Host */
#define PCI_PRODUCT_INTEL_CORE7G_U_GT3_15W 0x5926 /* Iris Plus Graphics 640 */
#define PCI_PRODUCT_INTEL_CORE7G_U_GT3_28W 0x5927 /* Iris Plus Graphics 650 */
#define PCI_PRODUCT_INTEL_APOLLOLAKE_IGD_1 0x5a84 /* HD Graphics 505 */
@@ -5149,7 +5166,55 @@
#define PCI_PRODUCT_INTEL_100SERIES_LP_UART_3 0x9d66 /* 100 Series UART */
#define PCI_PRODUCT_INTEL_100SERIES_LP_HDA 0x9d70 /* 100 Series HD Audio */
#define PCI_PRODUCT_INTEL_200SERIES_U_HDA 0x9d71 /* 200 Series HD Audio */
+#define PCI_PRODUCT_INTEL_300SERIES_U_LPC 0x9d84 /* 300 Series LPC */
+#define PCI_PRODUCT_INTEL_300SERIES_U_P2SB 0x9da0 /* 300 Series P2SB */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PMC 0x9da1 /* 300 Series PMC */
+#define PCI_PRODUCT_INTEL_300SERIES_U_SMB 0x9da3 /* 300 Series SMBus */
+#define PCI_PRODUCT_INTEL_300SERIES_U_SPI_1 0x9da4 /* 300 Series SPI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_TH 0x9da6 /* 300 Series TH */
+#define PCI_PRODUCT_INTEL_300SERIES_U_UART_1 0x9da8 /* 300 Series UART */
+#define PCI_PRODUCT_INTEL_300SERIES_U_UART_2 0x9da9 /* 300 Series UART */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_1 0x9db0 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_2 0x9db1 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_3 0x9db2 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_4 0x9db3 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_5 0x9db4 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_6 0x9db5 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_7 0x9db6 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_8 0x9db7 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_9 0x9db8 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_10 0x9db9 /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_11 0x9dba /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_12 0x9dbb /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_13 0x9dbc /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_14 0x9dbd /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_15 0x9dbe /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_PCIE_16 0x9dbf /* 300 Series PCIE */
+#define PCI_PRODUCT_INTEL_300SERIES_U_EMMC 0x9dc4 /* 300 Series eMMC */
+#define PCI_PRODUCT_INTEL_300SERIES_U_I2C_1 0x9dc5 /* 300 Series I2C */
+#define PCI_PRODUCT_INTEL_300SERIES_U_I2C_2 0x9dc6 /* 300 Series I2C */
+#define PCI_PRODUCT_INTEL_300SERIES_U_UART_3 0x9dc7 /* 300 Series UART */
+#define PCI_PRODUCT_INTEL_300SERIES_U_HDA 0x9dc8 /* 300 Series HD Audio */
+#define PCI_PRODUCT_INTEL_300SERIES_U_AHCI 0x9dd3 /* 300 Series AHCI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_RAID_1 0x9dd5 /* 300 Series RAID */
+#define PCI_PRODUCT_INTEL_300SERIES_U_RAID_2 0x9dd7 /* 300 Series RAID */
+#define PCI_PRODUCT_INTEL_300SERIES_U_MEI_1 0x9de0 /* 300 Series MEI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_MEI_2 0x9de1 /* 300 Series MEI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_IDER 0x9de2 /* 300 Series IDER */
+#define PCI_PRODUCT_INTEL_300SERIES_U_KT 0x9de3 /* 300 Series KT */
+#define PCI_PRODUCT_INTEL_300SERIES_U_MEI_3 0x9de4 /* 300 Series MEI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_MEI_4 0x9de5 /* 300 Series MEI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_I2C_3 0x9de8 /* 300 Series I2C */
+#define PCI_PRODUCT_INTEL_300SERIES_U_I2C_4 0x9de9 /* 300 Series I2C */
+#define PCI_PRODUCT_INTEL_300SERIES_U_I2C_5 0x9dea /* 300 Series I2C */
+#define PCI_PRODUCT_INTEL_300SERIES_U_I2C_6 0x9deb /* 300 Series I2C */
+#define PCI_PRODUCT_INTEL_300SERIES_U_XHCI 0x9ded /* 300 Series xHCI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_SSRAM 0x9def /* 300 Series Shared SRAM */
#define PCI_PRODUCT_INTEL_WL_9560_1 0x9df0 /* Dual Band Wireless AC 9560 */
+#define PCI_PRODUCT_INTEL_300SERIES_U_SDXC 0x9df5 /* 300 Series SDXC */
+#define PCI_PRODUCT_INTEL_300SERIES_U_THERM 0x9df9 /* 300 Series Thermal */
+#define PCI_PRODUCT_INTEL_300SERIES_U_SPI_2 0x9dfb /* 300 Series SPI */
+#define PCI_PRODUCT_INTEL_300SERIES_U_ISH 0x9dfc /* 300 Series ISH */
#define PCI_PRODUCT_INTEL_PINEVIEW_DMI 0xa000 /* Pineview DMI */
#define PCI_PRODUCT_INTEL_PINEVIEW_IGC_1 0xa001 /* Pineview Video */
#define PCI_PRODUCT_INTEL_PINEVIEW_IGC_2 0xa002 /* Pineview Video */