Move everything to where is supposed to be (reg definitions, etc).

Add some of the skip logic.

1 files changed, 96 insertions, 20 deletions

diff --git a/sys/dev/pci/ubsecreg.h b/sys/dev/pci/ubsecreg.h
index d68a2c8a2cb..4eb14d2dcab 100644
--- a/sys/dev/pci/ubsecreg.h
+++ b/sys/dev/pci/ubsecreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ubsecreg.h,v 1.1 2000/05/18 01:25:19 jason Exp $	*/
+/*	$OpenBSD: ubsecreg.h,v 1.2 2000/06/03 13:14:39 jason Exp $	*/
 
 /*
  * Copyright (c) 2000 Theo de Raadt
@@ -27,27 +27,103 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#define UB_MCR			0x00		/* MCR */
+/*
+ * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband
+ * Security "uBSec" chip.  Definitions from revision 2.8 of the product
+ * datasheet.
+ */
+
+#define BS_BAR		0x10	/* DMA and status base address register */
+
+/*
+ * DMA Control & Status Registers (offset from BS_BAR)
+ */
+#define	BS_MCR1		0x00	/* DMA Master Command Record 1 */
+#define	BS_CTRL		0x04	/* DMA Control */
+#define	BS_STAT		0x08	/* DMA Status */
+#define	BS_ERR		0x0c	/* DMA Error Address */
+#define	BS_MCR2		0x10	/* DMA Master Command Record 2 */
+
+/* BS_CTRL - DMA Control */
+#define	BS_CTRL_MCR2INT		0x40000000	/* enable intr MCR for MCR2 */
+#define	BS_CTRL_MCR1INT		0x20000000	/* enable intr MCR for MCR1 */
+#define	BS_CTRL_OFM		0x10000000	/* Output fragment mode */
+#define	BS_CTRL_BE32		0x08000000	/* big-endian, 32bit bytes */
+#define	BS_CTRL_BE64		0x04000000	/* big-endian, 64bit bytes */
+#define	BS_CTRL_DMAERR		0x02000000	/* enable intr DMA error */
+#define	BS_CTRL_RNG_M		0x01800000	/* RND mode */
+#define	BS_CTRL_RNG_1		0x00000000	/* 1bit rn/one slow clock */
+#define	BS_CTRL_RNG_4		0x00800000	/* 1bit rn/four slow clocks */
+#define	BS_CTRL_RNG_8		0x01000000	/* 1bit rn/eight slow clocks */
+#define	BS_CTRL_RNG_16		0x01800000	/* 1bit rn/16 slow clocks */
+#define	BS_CTRL_FRAG_M		0x0000ffff	/* output fragment size mask */
+
+/* BS_STAT - DMA Status */
+#define	BS_STAT_MCR1_BUSY	0x80000000	/* MCR1 is busy */
+#define	BS_STAT_MCR1_FULL	0x40000000	/* MCR1 is full */
+#define	BS_STAT_MCR1_DONE	0x20000000	/* MCR1 is done */
+#define	BS_STAT_DMAERR		0x10000000	/* DMA error */
+#define	BS_STAT_MCR2_FULL	0x08000000	/* MCR2 is full */
+#define	BS_STAT_MCR2_DONE	0x04000000	/* MCR2 is done */
+
+/* BS_ERR - DMA Error Address */
+#define	BS_ERR_READ		0x00000001	/* fault was on read */
+
+#define	UBSEC_CARD(sid)		(((sid) & 0xf0000000) >> 28)
+#define	UBSEC_SID(crd,ses)	(((crd) << 28) | ((ses) & 0x7ff))
+#define	MAX_SCATTER		10
+
+struct ubsec_pktctx {
+	u_int8_t	pc_deskey[24];		/* 3DES key */
+	u_int8_t	pc_hminner[20];		/* hmac inner state */
+	u_int8_t	pc_hmouter[20];		/* hmac outer state */
+	u_int8_t	pc_iv[8];		/* 3DES iv */
+	u_int32_t	pc_flags;
+};
+#define	UBS_PKTCTX_COFFSET	0xffff0000	/* cryto to mac offset */
+#define	UBS_PKTCTX_ENC_3DES	0x00008000	/* use 3des */
+#define	UBS_PKTCTX_ENC_NONE	0x00000000	/* no encryption */
+#define	UBS_PKTCTX_INBOUND	0x00004000	/* inbound packet */
+#define	UBS_PKTCTX_AUTH		0x00003000	/* authentication mask */
+#define	UBS_PKTCTX_AUTH_NONE	0x00000000	/* no authentication */
+#define	UBS_PKTCTX_AUTH_MD5	0x00001000	/* use hmac-md5 */
+#define	UBS_PKTCTX_AUTH_SHA1	0x00002000	/* use hmac-sha1 */
+
+struct ubsec_pktbuf {
+	u_int32_t	pb_addr;		/* address of buffer start */
+	u_int32_t	pb_next;		/* pointer to next pktbuf */
+	u_int32_t	pb_len;
+};
+#define	UBS_PKTBUF_LEN		0x0000ffff	/* length mask */
 
-#define UB_DMACTRL		0x04		/* DMA control */
-#define UB_DMAC_MCR2IEN		0x40000000	/* Enable MCR2 completion interrupt */
-#define UB_DMAC_MCRIEN		0x20000000	/* Enable MCR completion interrupt */
-#define UB_DMAC_FRAGMODE	0x10000000
-#define UB_DMAC_LE32		0x08000000
-#define UB_DMAC_LE64		0x04000000
-#define UB_DMAC_DMAERR		0x02000000
+struct ubsec_mcr {
+	u_int32_t		mcr_flags;	/* flags/packet count */
 
-#define UB_DMASTAT		0x08
-#define UB_DMAS_MCRBUSY		0x80000000
-#define UB_DMAS_MCRFULL		0x40000000
-#define UB_DMAS_MCRDONE		0x20000000
-#define UB_DMAS_DMAERR		0x10000000
-#define UB_DMAS_MCR2FULL	0x08000000
-#define UB_DMAS_MCR2DONE	0x04000000
+	u_int32_t		mcr_cmdctxp;	/* command ctx pointer */
+	struct ubsec_pktbuf	mcr_ipktbuf;	/* input chain header */
+	struct ubsec_pktbuf	mcr_opktbuf;	/* output chain header */
+};
+#define	UBS_MCR_PACKETS		0x0000ffff	/* packets in this mcr */
+#define	UBS_MCR_DONE		0x00010000	/* mcr has been processed */
+#define	UBS_MCR_ERROR		0x00020000	/* error in processing */
+#define	UBS_MCR_ERRORCODE	0xff000000	/* error type */
 
-#define UB_DMAADDR		0x0c
-#define UB_DMAA_ADDMASK		0xfffffffc
-#define UB_DMAA_READ		0x00000002
+struct ubsec_q {
+	SIMPLEQ_ENTRY(ubsec_q)		q_next;
+	struct ubsec_softc		*q_sc;
+	struct cryptop			*q_crp;
+	struct ubsec_mcr		q_mcr;
+	struct ubsec_pktctx		q_ctx;
 
-#define UB_MCR2			0x10		/* MCR2 */
+	struct mbuf *		      	q_src_m;
+	long				q_src_packp[MAX_SCATTER];
+	int				q_src_packl[MAX_SCATTER];
+	int				q_src_npa, q_src_l;
+	struct ubsec_pktbuf		q_srcpkt[MAX_SCATTER-1];
 
+	struct mbuf *			q_dst_m;
+	long				q_dst_packp[MAX_SCATTER];
+	int				q_dst_packl[MAX_SCATTER];
+	int				q_dst_npa, q_dst_l;
+	struct ubsec_pktbuf		q_dstpkt[MAX_SCATTER-1];
+};