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authorJonathan Gray <jsg@cvs.openbsd.org>2022-01-27 23:05:40 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2022-01-27 23:05:40 +0000
commit9447cef630188fc20e1210d0a0958441289d1ca4 (patch)
tree6ee7b9071ae4bbec83c3995192c7c8371270ba53 /sys/dev/pci
parent150b2b74ff7da7256cfd12014fabde70f39c8c3a (diff)
drm/amd/amdgpu: fix psp tmr bo pin count leak in SRIOV
From Jingwen Chen 8662d0c6a36807093aed34b17b930484fd4bf22f in linux 5.15.y/5.15.17 85dfc1d692c9434c37842e610be37cd4ae4e0081 in mainline linux
Diffstat (limited to 'sys/dev/pci')
-rw-r--r--sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
index bfbcdc8a349..fbd720bde43 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
@@ -2207,12 +2207,16 @@ static int psp_hw_start(struct psp_context *psp)
return ret;
}
+ if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
+ goto skip_pin_bo;
+
ret = psp_tmr_init(psp);
if (ret) {
DRM_ERROR("PSP tmr init failed!\n");
return ret;
}
+skip_pin_bo:
/*
* For ASICs with DF Cstate management centralized
* to PMFW, TMR setup should be performed after PMFW