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authorStuart Henderson <sthen@cvs.openbsd.org>2009-05-21 23:04:21 +0000
committerStuart Henderson <sthen@cvs.openbsd.org>2009-05-21 23:04:21 +0000
commite05032cbbfa35d846563269454722a206737422a (patch)
treead47d17c6d7cd311062d914e1aea10421501addf /sys/dev/pci
parent185d67cd6bd7d199a16ca4b631e1f64771bbf941 (diff)
add support for BCM576x, 577xx, and some new 572x/578x devices.
from Brad; testing by phessler, naddy, myself and others on a range of older and newer devices. ok dlg@.
Diffstat (limited to 'sys/dev/pci')
-rw-r--r--sys/dev/pci/if_bge.c84
-rw-r--r--sys/dev/pci/if_bgereg.h130
2 files changed, 145 insertions, 69 deletions
diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c
index 06d61187ac1..635202b5c91 100644
--- a/sys/dev/pci/if_bge.c
+++ b/sys/dev/pci/if_bge.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bge.c,v 1.262 2009/04/23 19:15:07 kettenis Exp $ */
+/* $OpenBSD: if_bge.c,v 1.263 2009/05/21 23:04:20 sthen Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -240,6 +240,7 @@ const struct pci_matchid bge_devices[] = {
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751 },
@@ -255,10 +256,17 @@ const struct pci_matchid bge_devices[] = {
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F },
@@ -270,6 +278,10 @@ const struct pci_matchid bge_devices[] = {
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906 },
{ PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57720 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780 },
+ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790 },
{ PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PW008GE4 },
{ PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PW008GE5 },
@@ -288,8 +300,12 @@ const struct pci_matchid bge_devices[] = {
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
#define BGE_IS_575X_PLUS(sc) \
(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \
@@ -298,8 +314,12 @@ const struct pci_matchid bge_devices[] = {
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
#define BGE_IS_5714_FAMILY(sc) \
(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \
@@ -364,6 +384,10 @@ static const struct bge_revision {
{ BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
{ BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
{ BGE_CHIPID_BCM5755_C0, "BCM5755 C0" },
+ { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
+ { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
+ { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
+ { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
/* the 5754 and 5787 share the same ASIC ID */
{ BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
{ BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
@@ -391,9 +415,13 @@ static const struct bge_revision bge_majorrevs[] = {
{ BGE_ASICREV_BCM5780, "unknown BCM5780" },
{ BGE_ASICREV_BCM5714, "unknown BCM5714" },
{ BGE_ASICREV_BCM5755, "unknown BCM5755" },
+ { BGE_ASICREV_BCM5761, "unknown BCM5761" },
+ { BGE_ASICREV_BCM5784, "unknown BCM5784" },
+ { BGE_ASICREV_BCM5785, "unknown BCM5785" },
/* 5754 and 5787 share the same ASIC ID */
{ BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
{ BGE_ASICREV_BCM5906, "unknown BCM5906" },
+ { BGE_ASICREV_BCM57780, "unknown BCM57780" },
{ 0, NULL }
};
@@ -1638,7 +1666,11 @@ bge_blockinit(struct bge_softc *sc)
/* Enable host coalescing bug fix. */
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
val |= (1 << 29);
/* Turn on write DMA state machine */
@@ -1646,6 +1678,13 @@ bge_blockinit(struct bge_softc *sc)
val = BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS;
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
+ val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
+ BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
+ BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
+
if (sc->bge_flags & BGE_PCIE)
val |= BGE_RDMAMODE_FIFO_LONG_BURST;
@@ -1668,8 +1707,13 @@ bge_blockinit(struct bge_softc *sc)
/* Turn on send BD completion state machine */
CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
+ val = BGE_SDCMODE_ENABLE;
+
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
+ val |= BGE_SDCMODE_CDELAY;
+
/* Turn on send data completion state machine */
- CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
+ CSR_WRITE_4(sc, BGE_SDC_MODE, val);
/* Turn on send data initiator state machine */
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
@@ -1813,17 +1857,21 @@ bge_attach(struct device *parent, struct device *self, void *aux)
/*
* Save ASIC rev.
*/
-
sc->bge_chipid =
- pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
- BGE_PCIMISCCTL_ASICREV;
+ (pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL)
+ >> BGE_PCIMISCCTL_ASICREV_SHIFT);
+
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
+ sc->bge_chipid = pci_conf_read(pc, pa->pa_tag,
+ BGE_PCI_PRODID_ASICREV);
+ }
printf(", ");
br = bge_lookup_rev(sc->bge_chipid);
if (br == NULL)
- printf("unknown ASIC (0x%04x)", sc->bge_chipid >> 16);
+ printf("unknown ASIC (0x%x)", sc->bge_chipid);
else
- printf("%s (0x%04x)", br->br_name, sc->bge_chipid >> 16);
+ printf("%s (0x%x)", br->br_name, sc->bge_chipid);
/*
* PCI Express check.
@@ -1895,6 +1943,7 @@ bge_attach(struct device *parent, struct device *self, void *aux)
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
sc->bge_flags |= BGE_10_100_ONLY;
@@ -1914,15 +1963,20 @@ bge_attach(struct device *parent, struct device *self, void *aux)
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
sc->bge_flags |= BGE_PHY_5704_A0_BUG;
- if (BGE_IS_5705_OR_BEYOND(sc)) {
+ if ((BGE_IS_5705_OR_BEYOND(sc)) &&
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 &&
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 &&
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) {
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
sc->bge_flags |= BGE_PHY_JITTER_BUG;
if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
sc->bge_flags |= BGE_PHY_ADJUST_TRIM;
- } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)
+ } else
sc->bge_flags |= BGE_PHY_BER_BUG;
}
@@ -2199,7 +2253,11 @@ bge_reset(struct bge_softc *sc)
/* Disable fastboot on controllers that support it. */
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 ||
+ BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index c17b5b548f3..7520d56e98c 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.91 2009/04/23 19:15:07 kettenis Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.92 2009/05/21 23:04:20 sthen Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -199,6 +199,7 @@
#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
#define BGE_PCI_ISR_MBX_HI 0xB0
#define BGE_PCI_ISR_MBX_LO 0xB4
+#define BGE_PCI_PRODID_ASICREV 0xBC
/* XXX:
* Used in PCI-Express code for 575x chips.
@@ -219,6 +220,7 @@
#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
+#define BGE_PCIMISCCTL_ASICREV_SHIFT 16
#if BYTE_ORDER == LITTLE_ENDIAN
#define BGE_DMA_SWAP_OPTIONS \
@@ -234,61 +236,65 @@
(BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \
BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
-#define BGE_CHIPID_BCM5700_A0 0x70000000
-#define BGE_CHIPID_BCM5700_A1 0x70010000
-#define BGE_CHIPID_BCM5700_B0 0x71000000
-#define BGE_CHIPID_BCM5700_B1 0x71010000
-#define BGE_CHIPID_BCM5700_B2 0x71020000
-#define BGE_CHIPID_BCM5700_B3 0x71030000
-#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
-#define BGE_CHIPID_BCM5700_C0 0x72000000
-#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
-#define BGE_CHIPID_BCM5701_B0 0x01000000
-#define BGE_CHIPID_BCM5701_B2 0x01020000
-#define BGE_CHIPID_BCM5701_B5 0x01050000
-#define BGE_CHIPID_BCM5703_A0 0x10000000
-#define BGE_CHIPID_BCM5703_A1 0x10010000
-#define BGE_CHIPID_BCM5703_A2 0x10020000
-#define BGE_CHIPID_BCM5703_A3 0x10030000
-#define BGE_CHIPID_BCM5703_B0 0x11000000
-#define BGE_CHIPID_BCM5704_A0 0x20000000
-#define BGE_CHIPID_BCM5704_A1 0x20010000
-#define BGE_CHIPID_BCM5704_A2 0x20020000
-#define BGE_CHIPID_BCM5704_A3 0x20030000
-#define BGE_CHIPID_BCM5704_B0 0x21000000
-#define BGE_CHIPID_BCM5705_A0 0x30000000
-#define BGE_CHIPID_BCM5705_A1 0x30010000
-#define BGE_CHIPID_BCM5705_A2 0x30020000
-#define BGE_CHIPID_BCM5705_A3 0x30030000
-#define BGE_CHIPID_BCM5750_A0 0x40000000
-#define BGE_CHIPID_BCM5750_A1 0x40010000
-#define BGE_CHIPID_BCM5750_A3 0x40030000
-#define BGE_CHIPID_BCM5750_B0 0x40100000
-#define BGE_CHIPID_BCM5750_B1 0x41010000
-#define BGE_CHIPID_BCM5750_C0 0x42000000
-#define BGE_CHIPID_BCM5750_C1 0x42010000
-#define BGE_CHIPID_BCM5750_C2 0x42020000
-#define BGE_CHIPID_BCM5714_A0 0x50000000
-#define BGE_CHIPID_BCM5752_A0 0x60000000
-#define BGE_CHIPID_BCM5752_A1 0x60010000
-#define BGE_CHIPID_BCM5752_A2 0x60020000
-#define BGE_CHIPID_BCM5714_B0 0x80000000
-#define BGE_CHIPID_BCM5714_B3 0x80030000
-#define BGE_CHIPID_BCM5715_A0 0x90000000
-#define BGE_CHIPID_BCM5715_A1 0x90010000
-#define BGE_CHIPID_BCM5715_A3 0x90030000
-#define BGE_CHIPID_BCM5755_A0 0xa0000000
-#define BGE_CHIPID_BCM5755_A1 0xa0010000
-#define BGE_CHIPID_BCM5755_A2 0xa0020000
-#define BGE_CHIPID_BCM5755_C0 0xa2000000
-#define BGE_CHIPID_BCM5787_A0 0xb0000000
-#define BGE_CHIPID_BCM5787_A1 0xb0010000
-#define BGE_CHIPID_BCM5787_A2 0xb0020000
-#define BGE_CHIPID_BCM5906_A1 0xc0010000
-#define BGE_CHIPID_BCM5906_A2 0xc0020000
+#define BGE_CHIPID_BCM5700_A0 0x7000
+#define BGE_CHIPID_BCM5700_A1 0x7001
+#define BGE_CHIPID_BCM5700_B0 0x7100
+#define BGE_CHIPID_BCM5700_B1 0x7101
+#define BGE_CHIPID_BCM5700_B2 0x7102
+#define BGE_CHIPID_BCM5700_B3 0x7103
+#define BGE_CHIPID_BCM5700_ALTIMA 0x7104
+#define BGE_CHIPID_BCM5700_C0 0x7200
+#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
+#define BGE_CHIPID_BCM5701_B0 0x0100
+#define BGE_CHIPID_BCM5701_B2 0x0102
+#define BGE_CHIPID_BCM5701_B5 0x0105
+#define BGE_CHIPID_BCM5703_A0 0x1000
+#define BGE_CHIPID_BCM5703_A1 0x1001
+#define BGE_CHIPID_BCM5703_A2 0x1002
+#define BGE_CHIPID_BCM5703_A3 0x1003
+#define BGE_CHIPID_BCM5703_B0 0x1100
+#define BGE_CHIPID_BCM5704_A0 0x2000
+#define BGE_CHIPID_BCM5704_A1 0x2001
+#define BGE_CHIPID_BCM5704_A2 0x2002
+#define BGE_CHIPID_BCM5704_A3 0x2003
+#define BGE_CHIPID_BCM5704_B0 0x2100
+#define BGE_CHIPID_BCM5705_A0 0x3000
+#define BGE_CHIPID_BCM5705_A1 0x3001
+#define BGE_CHIPID_BCM5705_A2 0x3002
+#define BGE_CHIPID_BCM5705_A3 0x3003
+#define BGE_CHIPID_BCM5750_A0 0x4000
+#define BGE_CHIPID_BCM5750_A1 0x4001
+#define BGE_CHIPID_BCM5750_A3 0x4003
+#define BGE_CHIPID_BCM5750_B0 0x4010
+#define BGE_CHIPID_BCM5750_B1 0x4101
+#define BGE_CHIPID_BCM5750_C0 0x4200
+#define BGE_CHIPID_BCM5750_C1 0x4201
+#define BGE_CHIPID_BCM5750_C2 0x4202
+#define BGE_CHIPID_BCM5714_A0 0x5000
+#define BGE_CHIPID_BCM5761_A0 0x5761000
+#define BGE_CHIPID_BCM5761_A1 0x5761100
+#define BGE_CHIPID_BCM5784_A0 0x5784000
+#define BGE_CHIPID_BCM5784_A1 0x5784100
+#define BGE_CHIPID_BCM5752_A0 0x6000
+#define BGE_CHIPID_BCM5752_A1 0x6001
+#define BGE_CHIPID_BCM5752_A2 0x6002
+#define BGE_CHIPID_BCM5714_B0 0x8000
+#define BGE_CHIPID_BCM5714_B3 0x8003
+#define BGE_CHIPID_BCM5715_A0 0x9000
+#define BGE_CHIPID_BCM5715_A1 0x9001
+#define BGE_CHIPID_BCM5715_A3 0x9003
+#define BGE_CHIPID_BCM5755_A0 0xa000
+#define BGE_CHIPID_BCM5755_A1 0xa001
+#define BGE_CHIPID_BCM5755_A2 0xa002
+#define BGE_CHIPID_BCM5755_C0 0xa200
+#define BGE_CHIPID_BCM5787_A0 0xb000
+#define BGE_CHIPID_BCM5787_A1 0xb001
+#define BGE_CHIPID_BCM5787_A2 0xb002
+#define BGE_CHIPID_BCM5906_A1 0xc001
+#define BGE_CHIPID_BCM5906_A2 0xc002
/* shorthand one */
-#define BGE_ASICREV(x) ((x) >> 28)
+#define BGE_ASICREV(x) ((x) >> 12)
#define BGE_ASICREV_BCM5700 0x07
#define BGE_ASICREV_BCM5701 0x00
#define BGE_ASICREV_BCM5703 0x01
@@ -302,9 +308,14 @@
#define BGE_ASICREV_BCM5755 0x0a
#define BGE_ASICREV_BCM5787 0x0b
#define BGE_ASICREV_BCM5906 0x0c
+#define BGE_ASICREV_USE_PRODID_REG 0x0f
+#define BGE_ASICREV_BCM5761 0x5761
+#define BGE_ASICREV_BCM5784 0x5784
+#define BGE_ASICREV_BCM5785 0x5785
+#define BGE_ASICREV_BCM57780 0x57780
/* chip revisions */
-#define BGE_CHIPREV(x) ((x) >> 24)
+#define BGE_CHIPREV(x) ((x) >> 8)
#define BGE_CHIPREV_5700_AX 0x70
#define BGE_CHIPREV_5700_BX 0x71
#define BGE_CHIPREV_5700_CX 0x72
@@ -314,6 +325,8 @@
#define BGE_CHIPREV_5704_BX 0x21
#define BGE_CHIPREV_5750_AX 0x40
#define BGE_CHIPREV_5750_BX 0x41
+#define BGE_CHIPREV_5761_AX 0x57611
+#define BGE_CHIPREV_5784_AX 0x57841
/* PCI DMA Read/Write Control register */
#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
@@ -784,8 +797,9 @@
#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
#define BGE_MIMODE_AUTOPOLL 0x00000010
+#define BGE_MIMODE_500KHZ_CONST 0x00008000
#define BGE_MIMODE_CLKCNT 0x001F0000
-
+#define BGE_MIMODE_BASE 0x000C0000
/*
* Send data initiator control registers.
@@ -845,6 +859,7 @@
#define BGE_SDCMODE_RESET 0x00000001
#define BGE_SDCMODE_ENABLE 0x00000002
#define BGE_SDCMODE_ATTN 0x00000004
+#define BGE_SDCMODE_CDELAY 0x00000010
/* Send Data completion status register */
#define BGE_SDCSTAT_ATTN 0x00000004
@@ -1362,6 +1377,9 @@
#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
+#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
+#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
+#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 22:13:42 +0000