switch back from roundup2() and roundup() to round_up()

2 files changed, 25 insertions, 25 deletions

diff --git a/sys/dev/pci/drm/radeon/evergreen_cs.c b/sys/dev/pci/drm/radeon/evergreen_cs.c
index 403e6eace77..db27b9deafe 100644
--- a/sys/dev/pci/drm/radeon/evergreen_cs.c
+++ b/sys/dev/pci/drm/radeon/evergreen_cs.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: evergreen_cs.c,v 1.4 2015/02/11 07:01:37 jsg Exp $	*/
+/*	$OpenBSD: evergreen_cs.c,v 1.5 2015/04/06 14:32:55 jsg Exp $	*/
 /*
  * Copyright 2010 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
@@ -510,9 +510,9 @@ static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
 
 	if (G_028ABC_LINEAR(track->htile_surface)) {
 		/* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
-		nbx = roundup2(nbx, 16 * 8);
+		nbx = round_up(nbx, 16 * 8);
 		/* height is npipes htiles aligned == npipes * 8 pixel aligned */
-		nby = roundup(nby, track->npipes * 8);
+		nby = round_up(nby, track->npipes * 8);
 	} else {
 		/* always assume 8x8 htile */
 		/* align is htile align * 8, htile align vary according to
@@ -521,23 +521,23 @@ static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
 		switch (track->npipes) {
 		case 8:
 			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-			nbx = roundup2(nbx, 64 * 8);
-			nby = roundup2(nby, 64 * 8);
+			nbx = round_up(nbx, 64 * 8);
+			nby = round_up(nby, 64 * 8);
 			break;
 		case 4:
 			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-			nbx = roundup2(nbx, 64 * 8);
-			nby = roundup2(nby, 32 * 8);
+			nbx = round_up(nbx, 64 * 8);
+			nby = round_up(nby, 32 * 8);
 			break;
 		case 2:
 			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-			nbx = roundup2(nbx, 32 * 8);
-			nby = roundup2(nby, 32 * 8);
+			nbx = round_up(nbx, 32 * 8);
+			nby = round_up(nby, 32 * 8);
 			break;
 		case 1:
 			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-			nbx = roundup2(nbx, 32 * 8);
-			nby = roundup2(nby, 16 * 8);
+			nbx = round_up(nbx, 32 * 8);
+			nby = round_up(nby, 16 * 8);
 			break;
 		default:
 			dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
diff --git a/sys/dev/pci/drm/radeon/r600_cs.c b/sys/dev/pci/drm/radeon/r600_cs.c
index 4dc72f2e453..dbafc402a80 100644
--- a/sys/dev/pci/drm/radeon/r600_cs.c
+++ b/sys/dev/pci/drm/radeon/r600_cs.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: r600_cs.c,v 1.5 2015/02/11 07:01:37 jsg Exp $	*/
+/*	$OpenBSD: r600_cs.c,v 1.6 2015/04/06 14:32:55 jsg Exp $	*/
 /*
  * Copyright 2008 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
@@ -660,9 +660,9 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
 		nby = height;
 		if (G_028D24_LINEAR(track->htile_surface)) {
 			/* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
-			nbx = roundup2(nbx, 16 * 8);
+			nbx = round_up(nbx, 16 * 8);
 			/* nby is npipes htiles aligned == npipes * 8 pixel aligned */
-			nby = roundup(nby, track->npipes * 8);
+			nby = round_up(nby, track->npipes * 8);
 		} else {
 			/* always assume 8x8 htile */
 			/* align is htile align * 8, htile align vary according to
@@ -671,23 +671,23 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
 			switch (track->npipes) {
 			case 8:
 				/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-				nbx = roundup2(nbx, 64 * 8);
-				nby = roundup2(nby, 64 * 8);
+				nbx = round_up(nbx, 64 * 8);
+				nby = round_up(nby, 64 * 8);
 				break;
 			case 4:
 				/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-				nbx = roundup2(nbx, 64 * 8);
-				nby = roundup2(nby, 32 * 8);
+				nbx = round_up(nbx, 64 * 8);
+				nby = round_up(nby, 32 * 8);
 				break;
 			case 2:
 				/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-				nbx = roundup2(nbx, 32 * 8);
-				nby = roundup2(nby, 32 * 8);
+				nbx = round_up(nbx, 32 * 8);
+				nby = round_up(nby, 32 * 8);
 				break;
 			case 1:
 				/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-				nbx = roundup2(nbx, 32 * 8);
-				nby = roundup2(nby, 16 * 8);
+				nbx = round_up(nbx, 32 * 8);
+				nby = round_up(nby, 16 * 8);
 				break;
 			default:
 				dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
@@ -1575,11 +1575,11 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
 		width = r600_mip_minify(w0, i);
 		nbx = r600_fmt_get_nblocksx(format, width);
 
-		nbx = roundup(nbx, block_align);
+		nbx = round_up(nbx, block_align);
 
 		height = r600_mip_minify(h0, i);
 		nby = r600_fmt_get_nblocksy(format, height);
-		nby = roundup(nby, height_align);
+		nby = round_up(nby, height_align);
 
 		depth = r600_mip_minify(d0, i);
 
@@ -1593,7 +1593,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
 			*l0_size = size;
 
 		if (i == 0 || i == 1)
-			offset = roundup(offset, base_align);
+			offset = round_up(offset, base_align);
 
 		offset += size;
 	}