diff options
| author | Brad Smith <brad@cvs.openbsd.org> | 2006-07-10 03:06:29 +0000 |
|---|---|---|
| committer | Brad Smith <brad@cvs.openbsd.org> | 2006-07-10 03:06:29 +0000 |
| commit | 95a5f9b79f742216a551b078c09336e824fda04d (patch) | |
| tree | 9dc1f0002ec0ffbcaaf76a597d8c382cc1611c55 /sys/dev/pci | |
| parent | a039d9359aa51d9d07bfe33fae14f4beae76f5b5 (diff) | |
add code for the interrupt holdoff support. bump NS_IHR_DELAY above 0 to
enable the support.
Diffstat (limited to 'sys/dev/pci')
| -rw-r--r-- | sys/dev/pci/if_sis.c | 8 | ||||
| -rw-r--r-- | sys/dev/pci/if_sisreg.h | 14 |
2 files changed, 20 insertions, 2 deletions
diff --git a/sys/dev/pci/if_sis.c b/sys/dev/pci/if_sis.c index c77296fe324..a0b5b8d7ab3 100644 --- a/sys/dev/pci/if_sis.c +++ b/sys/dev/pci/if_sis.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_sis.c,v 1.71 2006/05/28 00:04:24 jason Exp $ */ +/* $OpenBSD: if_sis.c,v 1.72 2006/07/10 03:06:28 brad Exp $ */ /* * Copyright (c) 1997, 1998, 1999 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. @@ -1650,6 +1650,12 @@ sis_init(void *xsc) sis_stop(sc); sc->sis_stopped = 0; +#if NS_IHR_DELAY > 0 + /* Configure interrupt holdoff register. */ + if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr == NS_SRR_16A) + CSR_WRITE_4(sc, NS_IHR, NS_IHR_VALUE); +#endif + mii = &sc->sc_mii; /* Set MAC address */ diff --git a/sys/dev/pci/if_sisreg.h b/sys/dev/pci/if_sisreg.h index c6ff985ace6..ea8c5858350 100644 --- a/sys/dev/pci/if_sisreg.h +++ b/sys/dev/pci/if_sisreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_sisreg.h,v 1.25 2006/03/25 03:21:56 brad Exp $ */ +/* $OpenBSD: if_sisreg.h,v 1.26 2006/07/10 03:06:28 brad Exp $ */ /* * Copyright (c) 1997, 1998, 1999 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. @@ -208,6 +208,18 @@ SIS_IMR_RX_IDLE|\ SIS_IMR_SYSERR) +/* Interrupt Holdoff Register */ +#define NS_IHR_HOLDCTL 0x00000100 + +/* + * Interrupt holdoff value for NS DP8316. We can have the chip + * delay interrupt delivery for a certain period. Units are in + * 100us, and the default is 100us holdoff. + */ +#define NS_IHR_DELAY 0 + +#define NS_IHR_VALUE (NS_IHR_HOLDCTL|NS_IHR_DELAY) + #define SIS_IER_INTRENB 0x00000001 #define SIS_PHYCTL_ACCESS 0x00000010 |