Support U160 on 53c1010 chips.

Add support for PPR negotiations and DT transfers,
and the preservation and restoration of the
SCNTL4 register which controls Ultra3 transfers.

Redo sync lookup, since the same period factor
can mean two things depending on whether you are
using DT or ST. Keep a minimum allowed ST period
factor, and a minimum allowd DT period factor for
each adapter.

Currently NO support for QAS or IUS or AIP.

2 files changed, 23 insertions, 20 deletions

diff --git a/sys/dev/pci/siop_pci_common.c b/sys/dev/pci/siop_pci_common.c
index 72f34553d5c..f7c86f36842 100644
--- a/sys/dev/pci/siop_pci_common.c
+++ b/sys/dev/pci/siop_pci_common.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: siop_pci_common.c,v 1.4 2001/03/10 05:04:06 krw Exp $ */
+/*	$OpenBSD: siop_pci_common.c,v 1.5 2001/04/15 06:01:30 krw Exp $ */
 /*	$NetBSD: siop_pci_common.c,v 1.6 2001/01/10 15:50:20 thorpej Exp $	*/
 
 /*
@@ -57,48 +57,48 @@ const struct siop_product_desc siop_products[] = {
 	{ PCI_PRODUCT_SYMBIOS_810,
 	0x00,
 	SF_PCI_RL | SF_CHIP_LS,
-	4, 8, 3, 250, 0
+	4, 8, 3, SF_CLOCK_2500, 0
 	},
 	{ PCI_PRODUCT_SYMBIOS_810,
 	0x10,
 	SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
-	4, 8, 3, 250, 0
+	4, 8, 3, SF_CLOCK_2500, 0
 	},
 	{ PCI_PRODUCT_SYMBIOS_815,
 	0x00,
 	SF_PCI_RL | SF_PCI_BOF,
-	4, 8, 3, 250, 0
+	4, 8, 3, SF_CLOCK_2500, 0
 	},
 	{ PCI_PRODUCT_SYMBIOS_820,
 	0x00,
 	SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
-	4, 8, 3, 250, 0
+	4, 8, 3, SF_CLOCK_2500, 0
 	},
 	{ PCI_PRODUCT_SYMBIOS_825,
 	0x00,
 	SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
-	4, 8, 3, 250, 0
+	4, 8, 3, SF_CLOCK_2500, 0
 	},
 	{ PCI_PRODUCT_SYMBIOS_825,
 	0x10,
 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_WIDE,
-	7, 8, 3, 250, 4096
+	7, 8, 3, SF_CLOCK_2500, 4096
 	},
 	{ PCI_PRODUCT_SYMBIOS_860,
 	0x00,
 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
 	SF_CHIP_PF | SF_CHIP_LS |
 	SF_BUS_ULTRA,
-	4, 8, 5, 125, 0
+	4, 8, 5, SF_CLOCK_1250, 0
 	},
 	{ PCI_PRODUCT_SYMBIOS_875,
 	0x00,
 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA | SF_BUS_WIDE,
-	7, 16, 5, 125, 4096
+	7, 16, 5, SF_CLOCK_1250, 4096
 	},
 	{ PCI_PRODUCT_SYMBIOS_875,
 	0x02,
@@ -106,7 +106,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA | SF_BUS_WIDE,
-	7, 16, 5, 125, 4096
+	7, 16, 5, SF_CLOCK_1250, 4096
 	},
 	{ PCI_PRODUCT_SYMBIOS_875J,
 	0x00,
@@ -114,7 +114,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA | SF_BUS_WIDE,
-	7, 16, 5, 125, 4096
+	7, 16, 5, SF_CLOCK_1250, 4096
 	},
 	{ PCI_PRODUCT_SYMBIOS_885,
 	0x00,
@@ -122,7 +122,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA | SF_BUS_WIDE,
-	7, 16, 5, 125, 4096
+	7, 16, 5, SF_CLOCK_1250, 4096
 	},
 	{ PCI_PRODUCT_SYMBIOS_895,
 	0x00,
@@ -130,7 +130,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
-	7, 31, 7, 62, 4096
+	7, 31, 7, SF_CLOCK_625, 4096
 	},
 	{ PCI_PRODUCT_SYMBIOS_895A,
 	0x00,
@@ -138,7 +138,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
-	7, 31, 7, 62, 8192
+	7, 31, 7, SF_CLOCK_625, 8192
 	},
 	{ PCI_PRODUCT_SYMBIOS_896,
 	0x00,
@@ -146,7 +146,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
-	7, 31, 7, 62, 8192
+	7, 31, 7, SF_CLOCK_625, 8192
 	},
 	{ PCI_PRODUCT_SYMBIOS_1010,
 	0x00,
@@ -154,7 +154,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
 	SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_C10 |
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
-	7, 31, 0, 62, 8192
+	7, 62, 0, SF_CLOCK_625, 8192
 	},
 	{ PCI_PRODUCT_SYMBIOS_1510D,
 	0x00,
@@ -162,7 +162,7 @@ const struct siop_product_desc siop_products[] = {
 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
 	SF_CHIP_LS | SF_CHIP_10REGS |
 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
-	7, 31, 7, 62, 4096
+	7, 31, 7, SF_CLOCK_625, 4096
 	},
 	{ 0,
 	0x00,
@@ -215,7 +215,7 @@ siop_pci_attach_common(sc, pa)
 	sc->siop.maxburst = sc->sc_pp->maxburst;
 	sc->siop.maxoff = sc->sc_pp->maxoff;
 	sc->siop.clock_div = sc->sc_pp->clock_div;
-	sc->siop.clock_period = sc->sc_pp->clock_period;
+	sc->siop.scf_index = sc->sc_pp->scf_index;
 	sc->siop.ram_size = sc->sc_pp->ram_size;
 
 	sc->siop.sc_reset = siop_pci_reset;
diff --git a/sys/dev/pci/siop_pci_common.h b/sys/dev/pci/siop_pci_common.h
index 641b36c7f79..39d640250fd 100644
--- a/sys/dev/pci/siop_pci_common.h
+++ b/sys/dev/pci/siop_pci_common.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: siop_pci_common.h,v 1.2 2001/02/20 00:32:30 krw Exp $ */
+/*	$OpenBSD: siop_pci_common.h,v 1.3 2001/04/15 06:01:31 krw Exp $ */
 /*	$NetBSD: siop_pci_common.h,v 1.2 2000/10/23 14:57:23 bouyer Exp $	*/
 
 /*
@@ -40,7 +40,10 @@ struct siop_product_desc {
 	u_int8_t maxburst;
 	u_int8_t maxoff;  /* maximum supported offset */
 	u_int8_t clock_div; /* clock divider to use for async. logic */
-	u_int8_t clock_period; /* clock period (ns * 10) */
+	u_int8_t scf_index; /* Index into a period_factor_to_scf.scf */
+#define     SF_CLOCK_2500	0
+#define	    SF_CLOCK_1250	1
+#define	    SF_CLOCK_625	2
 	int 	ram_size; /* size of RAM, if appropriate */
 };