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authorMark Kettenis <kettenis@cvs.openbsd.org>2011-10-13 13:09:30 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2011-10-13 13:09:30 +0000
commit6c6f2d19008ddad564db525921331ee0e982bdc7 (patch)
treeb772eb9dc21204aca9a0b3bcac7ed440812fbdc4 /sys/dev/pci
parent2b54d888d375c8a3a4c0b829273dacd387df9e2a (diff)
Make WOL support do something that actually makes sense; effectively
reverting most of the previous commit. Fixes unaligned read from PCI config space as well. ok & tested by stsp@
Diffstat (limited to 'sys/dev/pci')
-rw-r--r--sys/dev/pci/if_xl_pci.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/sys/dev/pci/if_xl_pci.c b/sys/dev/pci/if_xl_pci.c
index 4ce7cb99caa..9d135d7c4f3 100644
--- a/sys/dev/pci/if_xl_pci.c
+++ b/sys/dev/pci/if_xl_pci.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_xl_pci.c,v 1.37 2011/07/08 18:56:47 stsp Exp $ */
+/* $OpenBSD: if_xl_pci.c,v 1.38 2011/10/13 13:09:29 kettenis Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -268,14 +268,16 @@ xl_pci_attach(struct device *parent, struct device *self, void *aux)
}
#ifndef SMALL_KERNEL
- /* The card is WOL-capable if it supports PME# assertion
+ /*
+ * The card is WOL-capable if it supports PME# assertion
* from D3hot power state. Install a callback to configure
* PCI power state for WOL. It will be invoked when the
- * interface stops and WOL was enabled. */
- command = pci_conf_read(pc, pa->pa_tag, XL_PCI_PWRMGMTCAP);
+ * interface stops and WOL was enabled.
+ */
+ command = pci_conf_read(pc, pa->pa_tag, XL_PCI_CAPID);
if ((command >> 16) & XL_PME_CAP_D3_HOT) {
sc->wol_power = xl_pci_wol_power;
- sc->wol_power_arg = psc;
+ sc->wol_power_arg = psc;
}
#endif
}
@@ -366,6 +368,12 @@ void
xl_pci_wol_power(void *ppsc)
{
struct xl_pci_softc *psc = (struct xl_pci_softc*)ppsc;
+ u_int32_t command;
+
+ /* Make sure wake-up generation is enabled. */
+ command = pci_conf_read(psc->psc_pc, psc->psc_tag, XL_PCI_PWRMGMTCTRL);
+ command |= XL_PME_EN;
+ pci_conf_write(psc->psc_pc, psc->psc_tag, XL_PCI_PWRMGMTCTRL, command);
pci_set_powerstate(psc->psc_pc, psc->psc_tag, PCI_PMCSR_STATE_D3);
}