Fix various problems of auich on SiS 7012 based chips:

- rework auich_halt_pipe() and use it to ensure AUICH_RR is
  set only after DMA is halted (spec says to do so)

- rework auich_calibrate(): clear interrupt and event bits in
  AUICH_STS and ensure CIV counter is not changed.

- in the interrupt handler, set LVI to (qptr - 1) rather than
  the max value (bug introduced by previous commit)

All fixes are from Christopher Zimmermann <madroach at zakweb.de>,
Thanks!

tested on two different intel-based auich devices,
ok jakemsr

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