diff options
| author | Mats O Jansson <maja@cvs.openbsd.org> | 2010-06-27 12:05:19 +0000 |
|---|---|---|
| committer | Mats O Jansson <maja@cvs.openbsd.org> | 2010-06-27 12:05:19 +0000 |
| commit | 9190aa703c7dbeac82eb95dc41a5e8326206e2d1 (patch) | |
| tree | f402d87e2ad7e1b86382021c345edfc22fab9143 /sys/dev/usb/udl.h | |
| parent | 2f4de9c94a57e1ed574f0b22d1297764346f9aee (diff) | |
Add support for 800x480. Tested on Lilliput UM-70, MIMO UM-710 and UM-740.
ok matthiue@ and mglocker@. -moj
Diffstat (limited to 'sys/dev/usb/udl.h')
| -rw-r--r-- | sys/dev/usb/udl.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/sys/dev/usb/udl.h b/sys/dev/usb/udl.h index 87c49b65f67..d3bda91d6c6 100644 --- a/sys/dev/usb/udl.h +++ b/sys/dev/usb/udl.h @@ -1,4 +1,4 @@ -/* $OpenBSD: udl.h,v 1.16 2010/04/12 19:42:02 mglocker Exp $ */ +/* $OpenBSD: udl.h,v 1.17 2010/06/27 12:05:18 maja Exp $ */ /* * Copyright (c) 2009 Marcus Glocker <mglocker@openbsd.org> @@ -172,6 +172,11 @@ uint8_t udl_reg_vals_640x480_75[] = { /* 31.50 Mhz 75.7 Hz VESA std */ 0xff, 0xbf, 0x70, 0x02, 0x80, 0xf4, 0x8f, 0xff, 0xff, 0xff, 0xf9, 0x01, 0xe0, 0x01, 0x02, 0x9c, 0x18 }; +uint8_t udl_reg_vals_800x480_61[] = { /* 33.00 MHz 61.9 Hz */ + 0x00, 0x20, 0x3c, 0x7a, 0xc9, 0xf2, 0x6c, 0x48, 0xf9, 0x70, 0x53, 0xff, + 0xff, 0x21, 0x27, 0x03, 0x20, 0x91, 0xf3, 0xff, 0xff, 0xff, 0xf9, 0x01, + 0xe0, 0x01, 0x02, 0xc8, 0x19 +}; uint8_t udl_reg_vals_800x600_56[] = { /* 36.00 MHz 56.2 Hz VESA std */ 0x00, 0x65, 0x35, 0x48, 0xf4, 0xf2, 0x6c, 0x19, 0x18, 0xc9, 0x4b, 0xff, 0xff, 0x70, 0x35, 0x03, 0x20, 0x32, 0x31, 0xff, 0xff, 0xff, 0xfc, 0x02, @@ -278,6 +283,8 @@ static const struct udl_mode udl_modes[] = { { 640, 480, 67, DLALL, 3025, udl_reg_vals_640x480_67 }, { 640, 480, 72, DLALL, 3150, udl_reg_vals_640x480_72 }, { 640, 480, 75, DLALL, 3150, udl_reg_vals_640x480_75 }, + { 800, 480, 59, DLALL, 5000, udl_reg_vals_800x480_61 }, + { 800, 480, 61, DLALL, 3300, udl_reg_vals_800x480_61 }, { 800, 600, 56, DLALL, 3600, udl_reg_vals_800x600_56 }, { 800, 600, 60, DLALL, 4000, udl_reg_vals_800x600_60 }, { 800, 600, 72, DLALL, 5000, udl_reg_vals_800x600_72 }, |