diff options
author | Jonathan Gray <jsg@cvs.openbsd.org> | 2024-08-17 01:55:04 +0000 |
---|---|---|
committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2024-08-17 01:55:04 +0000 |
commit | 3c777c4841a44b7afecb6a14b10dca420dc71919 (patch) | |
tree | 001f0499ba7521fbfb3db73fad09f8961c4eabc1 /sys/dev/usb/xhci.c | |
parent | 1f84e9d0e797015ff0c6d16e1f5c019cbcea63f3 (diff) |
skip Controller Save State (CSS) and Controller Restore State (CRS)
on AMD 17h/1xh xHCI
avoids problem with resume after CRS was introduced in xhci.c rev 1.133
uhub0: device problem, disabling port 2
uhub1: device problem, disabling port 1
reported by brynet@ and reproduced on t495, ok kettenis@
Diffstat (limited to 'sys/dev/usb/xhci.c')
-rw-r--r-- | sys/dev/usb/xhci.c | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/sys/dev/usb/xhci.c b/sys/dev/usb/xhci.c index 75792693b70..d7a1fc0c9f1 100644 --- a/sys/dev/usb/xhci.c +++ b/sys/dev/usb/xhci.c @@ -1,4 +1,4 @@ -/* $OpenBSD: xhci.c,v 1.133 2024/08/15 17:17:05 kettenis Exp $ */ +/* $OpenBSD: xhci.c,v 1.134 2024/08/17 01:55:03 jsg Exp $ */ /* * Copyright (c) 2014-2015 Martin Pieuchot @@ -626,24 +626,25 @@ xhci_suspend(struct xhci_softc *sc) * will prevent the SoC from reaching its lowest idle state. * So save the state here. */ + if ((sc->sc_flags & XHCI_NOCSS) == 0) { + XOWRITE4(sc, XHCI_USBCMD, XHCI_CMD_CSS); /* Save state */ + hcr = XOREAD4(sc, XHCI_USBSTS); + for (i = 0; i < 100; i++) { + usb_delay_ms(&sc->sc_bus, 1); + hcr = XOREAD4(sc, XHCI_USBSTS) & XHCI_STS_SSS; + if (!hcr) + break; + } - XOWRITE4(sc, XHCI_USBCMD, XHCI_CMD_CSS); /* Save state */ - hcr = XOREAD4(sc, XHCI_USBSTS); - for (i = 0; i < 100; i++) { - usb_delay_ms(&sc->sc_bus, 1); - hcr = XOREAD4(sc, XHCI_USBSTS) & XHCI_STS_SSS; - if (!hcr) - break; - } + if (hcr) { + printf("%s: save state timeout\n", DEVNAME(sc)); + xhci_reset(sc); + return; + } - if (hcr) { - printf("%s: save state timeout\n", DEVNAME(sc)); - xhci_reset(sc); - return; + sc->sc_saved_state = 1; } - sc->sc_saved_state = 1; - /* Disable interrupts. */ XRWRITE4(sc, XHCI_IMOD(0), 0); XRWRITE4(sc, XHCI_IMAN(0), 0); |