Add mvneta(4), a driver for the Ethernet controller on the Armada

38x series (SoliodRun ClearFog, Turris Omnia) and the 37xx series
(ESPRESSObin).  Also add mvmdio(4), which is used to talk to the
MDIO bus.

ok kettenis@

5 files changed, 2579 insertions, 1 deletions

diff --git a/sys/dev/fdt/files.fdt b/sys/dev/fdt/files.fdt
index 4e128d54187..fa6198aa074 100644
--- a/sys/dev/fdt/files.fdt
+++ b/sys/dev/fdt/files.fdt
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.fdt,v 1.23 2017/08/25 20:00:35 patrick Exp $
+#	$OpenBSD: files.fdt,v 1.24 2017/08/25 20:09:34 patrick Exp $
 #
 # Config file and device description for machine-independent FDT code.
 # Included by ports that need it.
@@ -111,3 +111,11 @@ file	dev/fdt/dwdog.c			dwdog
 device	mvpinctrl
 attach	mvpinctrl at fdt
 file	dev/fdt/mvpinctrl.c		mvpinctrl
+
+device	mvmdio
+attach	mvmdio at fdt
+file	dev/fdt/mvmdio.c		mvmdio
+
+device	mvneta: ether, ifnet, mii, ifmedia
+attach	mvneta at fdt
+file	dev/fdt/if_mvneta.c		mvneta
diff --git a/sys/dev/fdt/if_mvneta.c b/sys/dev/fdt/if_mvneta.c
new file mode 100644
index 00000000000..bff95633672
--- /dev/null
+++ b/sys/dev/fdt/if_mvneta.c
@@ -0,0 +1,1529 @@
+/*	$OpenBSD: if_mvneta.c,v 1.1 2017/08/25 20:09:34 patrick Exp $	*/
+/*	$NetBSD: if_mvneta.c,v 1.41 2015/04/15 10:15:40 hsuenaga Exp $	*/
+/*
+ * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+#include <sys/endian.h>
+#include <sys/errno.h>
+#include <sys/kernel.h>
+#include <sys/mutex.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/types.h>
+#include <uvm/uvm_extern.h>
+#include <sys/mbuf.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_clock.h>
+#include <dev/ofw/ofw_pinctrl.h>
+#include <dev/ofw/fdt.h>
+
+#include <dev/fdt/if_mvnetareg.h>
+#include <dev/fdt/mvmdiovar.h>
+
+#ifdef __armv7__
+#include <armv7/marvell/mvmbusvar.h>
+#endif
+
+#include <net/if.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <net/bpf.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#ifdef MVNETA_DEBUG
+#define DPRINTF(x)	if (mvneta_debug) printf x
+#define DPRINTFN(n,x)	if (mvneta_debug >= (n)) printf x
+int mvneta_debug = MVNETA_DEBUG;
+#else
+#define DPRINTF(x)
+#define DPRINTFN(n,x)
+#endif
+
+#define MVNETA_READ(sc, reg) \
+	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
+#define MVNETA_WRITE(sc, reg, val) \
+	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+#define MVNETA_READ_FILTER(sc, reg, val, c) \
+	bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
+#define MVNETA_WRITE_FILTER(sc, reg, val, c) \
+	bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
+
+#define MVNETA_LINKUP_READ(sc) \
+	MVNETA_READ(sc, MVNETA_PS0)
+#define MVNETA_IS_LINKUP(sc)	(MVNETA_LINKUP_READ(sc) & MVNETA_PS0_LINKUP)
+
+#define MVNETA_TX_RING_CNT	256
+#define MVNETA_TX_RING_MSK	(MVNETA_TX_RING_CNT - 1)
+#define MVNETA_TX_RING_NEXT(x)	(((x) + 1) & MVNETA_TX_RING_MSK)
+#define MVNETA_TX_QUEUE_CNT	1
+#define MVNETA_RX_RING_CNT	256
+#define MVNETA_RX_RING_MSK	(MVNETA_RX_RING_CNT - 1)
+#define MVNETA_RX_RING_NEXT(x)	(((x) + 1) & MVNETA_RX_RING_MSK)
+#define MVNETA_RX_QUEUE_CNT	1
+
+CTASSERT(MVNETA_TX_RING_CNT > 1 && MVNETA_TX_RING_NEXT(MVNETA_TX_RING_CNT) ==
+	(MVNETA_TX_RING_CNT + 1) % MVNETA_TX_RING_CNT);
+CTASSERT(MVNETA_RX_RING_CNT > 1 && MVNETA_RX_RING_NEXT(MVNETA_RX_RING_CNT) ==
+	(MVNETA_RX_RING_CNT + 1) % MVNETA_RX_RING_CNT);
+
+#define MVNETA_NTXSEG		30
+
+struct mvneta_dmamem {
+	bus_dmamap_t		mdm_map;
+	bus_dma_segment_t	mdm_seg;
+	size_t			mdm_size;
+	caddr_t			mdm_kva;
+};
+#define MVNETA_DMA_MAP(_mdm)	((_mdm)->mdm_map)
+#define MVNETA_DMA_LEN(_mdm)	((_mdm)->mdm_size)
+#define MVNETA_DMA_DVA(_mdm)	((_mdm)->mdm_map->dm_segs[0].ds_addr)
+#define MVNETA_DMA_KVA(_mdm)	((void *)(_mdm)->mdm_kva)
+
+struct mvneta_buf {
+	bus_dmamap_t	tb_map;
+	struct mbuf	*tb_m;
+};
+
+struct mvneta_softc {
+	struct device sc_dev;
+	struct device *sc_mdio;
+
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+	bus_dma_tag_t sc_dmat;
+
+	struct arpcom sc_ac;
+#define sc_enaddr sc_ac.ac_enaddr
+	struct mii_data sc_mii;
+#define sc_media sc_mii.mii_media
+
+	struct timeout sc_tick_ch;
+
+	struct mvneta_dmamem	*sc_txring;
+	struct mvneta_buf	*sc_txbuf;
+	struct mvneta_tx_desc	*sc_txdesc;
+	int			 sc_tx_prod;	/* next free tx desc */
+	int			 sc_tx_cnt;	/* amount of tx sent */
+	int			 sc_tx_cons;	/* first tx desc sent */
+
+	struct mvneta_dmamem	*sc_rxring;
+	struct mvneta_buf	*sc_rxbuf;
+	struct mvneta_rx_desc	*sc_rxdesc;
+	int			 sc_rx_prod;	/* next rx desc to fill */
+	struct if_rxring	 sc_rx_ring;
+	int			 sc_rx_cons;	/* next rx desc recvd */
+
+	enum {
+		PHY_MODE_QSGMII,
+		PHY_MODE_SGMII,
+		PHY_MODE_RGMII,
+		PHY_MODE_RGMII_ID,
+	}			 sc_phy_mode;
+	int			 sc_fixed_link;
+	int			 sc_phy;
+	int			 sc_link;
+};
+
+
+int mvneta_miibus_readreg(struct device *, int, int);
+void mvneta_miibus_writereg(struct device *, int, int, int);
+void mvneta_miibus_statchg(struct device *);
+
+void mvneta_wininit(struct mvneta_softc *);
+
+/* Gigabit Ethernet Port part functions */
+int mvneta_match(struct device *, void *, void *);
+void mvneta_attach(struct device *, struct device *, void *);
+void mvneta_attach_deferred(struct device *);
+
+void mvneta_tick(void *);
+int mvneta_intr(void *);
+
+void mvneta_start(struct ifnet *);
+int mvneta_ioctl(struct ifnet *, u_long, caddr_t);
+void mvneta_port_up(struct mvneta_softc *);
+int mvneta_up(struct mvneta_softc *);
+void mvneta_down(struct mvneta_softc *);
+void mvneta_watchdog(struct ifnet *);
+
+int mvneta_mediachange(struct ifnet *);
+void mvneta_mediastatus(struct ifnet *, struct ifmediareq *);
+
+int mvneta_encap(struct mvneta_softc *, struct mbuf *, uint32_t *);
+void mvneta_rx_proc(struct mvneta_softc *);
+void mvneta_tx_proc(struct mvneta_softc *);
+uint8_t mvneta_crc8(const uint8_t *, size_t);
+void mvneta_filter_setup(struct mvneta_softc *);
+
+struct mvneta_dmamem *mvneta_dmamem_alloc(struct mvneta_softc *,
+    bus_size_t, bus_size_t);
+void mvneta_dmamem_free(struct mvneta_softc *, struct mvneta_dmamem *);
+void mvneta_fill_rx_ring(struct mvneta_softc *);
+
+struct cfdriver mvneta_cd = {
+	NULL, "mvneta", DV_IFNET
+};
+
+struct cfattach mvneta_ca = {
+	sizeof (struct mvneta_softc), mvneta_match, mvneta_attach,
+};
+
+int
+mvneta_miibus_readreg(struct device *dev, int phy, int reg)
+{
+	struct mvneta_softc *sc = (struct mvneta_softc *) dev;
+	return mvmdio_miibus_readreg(sc->sc_mdio, phy, reg);
+}
+
+void
+mvneta_miibus_writereg(struct device *dev, int phy, int reg, int val)
+{
+	struct mvneta_softc *sc = (struct mvneta_softc *) dev;
+	return mvmdio_miibus_writereg(sc->sc_mdio, phy, reg, val);
+}
+
+void
+mvneta_miibus_statchg(struct device *self)
+{
+	struct mvneta_softc *sc = (struct mvneta_softc *)self;
+
+	if (sc->sc_mii.mii_media_status & IFM_ACTIVE) {
+		uint32_t panc = MVNETA_READ(sc, MVNETA_PANC);
+
+		panc &= ~(MVNETA_PANC_SETMIISPEED |
+			  MVNETA_PANC_SETGMIISPEED |
+			  MVNETA_PANC_SETFULLDX);
+
+		switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
+		case IFM_1000_SX:
+		case IFM_1000_LX:
+		case IFM_1000_CX:
+		case IFM_1000_T:
+			panc |= MVNETA_PANC_SETGMIISPEED;
+			break;
+		case IFM_100_TX:
+			panc |= MVNETA_PANC_SETMIISPEED;
+			break;
+		case IFM_10_T:
+			break;
+		}
+
+		if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX)
+			panc |= MVNETA_PANC_SETFULLDX;
+
+		MVNETA_WRITE(sc, MVNETA_PANC, panc);
+	}
+
+	if (!!(sc->sc_mii.mii_media_status & IFM_ACTIVE) != sc->sc_link) {
+		sc->sc_link = !sc->sc_link;
+
+		if (sc->sc_link) {
+			uint32_t panc = MVNETA_READ(sc, MVNETA_PANC);
+			panc &= ~MVNETA_PANC_FORCELINKFAIL;
+			panc |= MVNETA_PANC_FORCELINKPASS;
+			MVNETA_WRITE(sc, MVNETA_PANC, panc);
+			mvneta_port_up(sc);
+		} else {
+			uint32_t panc = MVNETA_READ(sc, MVNETA_PANC);
+			panc &= ~MVNETA_PANC_FORCELINKPASS;
+			panc |= MVNETA_PANC_FORCELINKFAIL;
+			MVNETA_WRITE(sc, MVNETA_PANC, panc);
+		}
+	}
+}
+
+void
+mvneta_enaddr_write(struct mvneta_softc *sc)
+{
+	uint32_t maddrh, maddrl;
+	maddrh  = sc->sc_enaddr[0] << 24;
+	maddrh |= sc->sc_enaddr[1] << 16;
+	maddrh |= sc->sc_enaddr[2] << 8;
+	maddrh |= sc->sc_enaddr[3];
+	maddrl  = sc->sc_enaddr[4] << 8;
+	maddrl |= sc->sc_enaddr[5];
+	MVNETA_WRITE(sc, MVNETA_MACAH, maddrh);
+	MVNETA_WRITE(sc, MVNETA_MACAL, maddrl);
+}
+
+void
+mvneta_wininit(struct mvneta_softc *sc)
+{
+#ifdef __armv7__
+	uint32_t en;
+	int i;
+
+	if (mvmbus_dram_info == NULL)
+		panic("%s: mbus dram information not set up",
+		    sc->sc_dev.dv_xname);
+
+	for (i = 0; i < MVNETA_NWINDOW; i++) {
+		MVNETA_WRITE(sc, MVNETA_BASEADDR(i), 0);
+		MVNETA_WRITE(sc, MVNETA_S(i), 0);
+
+		if (i < MVNETA_NREMAP)
+			MVNETA_WRITE(sc, MVNETA_HA(i), 0);
+	}
+
+	en = MVNETA_BARE_EN_MASK;
+
+	for (i = 0; i < mvmbus_dram_info->numcs; i++) {
+		struct mbus_dram_window *win = &mvmbus_dram_info->cs[i];
+
+		MVNETA_WRITE(sc, MVNETA_BASEADDR(i),
+		    MVNETA_BASEADDR_TARGET(mvmbus_dram_info->targetid) |
+		    MVNETA_BASEADDR_ATTR(win->attr)	|
+		    MVNETA_BASEADDR_BASE(win->base));
+		MVNETA_WRITE(sc, MVNETA_S(i), MVNETA_S_SIZE(win->size));
+
+		en &= ~(1 << i);
+	}
+
+	MVNETA_WRITE(sc, MVNETA_BARE, en);
+#endif
+}
+
+int
+mvneta_match(struct device *parent, void *cfdata, void *aux)
+{
+	struct fdt_attach_args *faa = aux;
+
+	return OF_is_compatible(faa->fa_node, "marvell,armada-370-neta");
+}
+
+void
+mvneta_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct mvneta_softc *sc = (struct mvneta_softc *) self;
+	struct fdt_attach_args *faa = aux;
+	struct ifnet *ifp;
+	int i, len, node;
+	char *phy_mode;
+
+	printf("\n");
+
+	sc->sc_iot = faa->fa_iot;
+	timeout_set(&sc->sc_tick_ch, mvneta_tick, sc);
+	if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
+	    faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
+		printf("%s: cannot map registers\n", self->dv_xname);
+		return;
+	}
+	sc->sc_dmat = faa->fa_dmat;
+
+	clock_enable(faa->fa_node, NULL);
+
+	pinctrl_byname(faa->fa_node, "default");
+
+	len = OF_getproplen(faa->fa_node, "phy-mode");
+	if (len <= 0) {
+		printf("%s: cannot extract phy-mode\n", self->dv_xname);
+		return;
+	}
+
+	phy_mode = malloc(len, M_TEMP, M_WAITOK);
+	OF_getprop(faa->fa_node, "phy-mode", phy_mode, len);
+	if (!strncmp(phy_mode, "qsgmii", strlen("qsgmii")))
+		sc->sc_phy_mode = PHY_MODE_QSGMII;
+	else if (!strncmp(phy_mode, "sgmii", strlen("sgmii")))
+		sc->sc_phy_mode = PHY_MODE_SGMII;
+	else if (!strncmp(phy_mode, "rgmii-id", strlen("rgmii-id")))
+		sc->sc_phy_mode = PHY_MODE_RGMII_ID;
+	else if (!strncmp(phy_mode, "rgmii", strlen("rgmii")))
+		sc->sc_phy_mode = PHY_MODE_RGMII;
+	else {
+		printf("%s: cannot use phy-mode %s\n", self->dv_xname,
+		    phy_mode);
+		return;
+	}
+	free(phy_mode, M_TEMP, len);
+
+	/* TODO: check child's name to be "fixed-link" */
+	if (OF_getproplen(faa->fa_node, "fixed-link") >= 0 ||
+	    OF_child(faa->fa_node))
+		sc->sc_fixed_link = 1;
+
+	if (!sc->sc_fixed_link) {
+		node = OF_getnodebyphandle(OF_getpropint(faa->fa_node,
+		    "phy", 0));
+		if (!node) {
+			printf("%s: cannot find phy in fdt\n", self->dv_xname);
+			return;
+		}
+
+		if ((sc->sc_phy = OF_getpropint(node, "reg", -1)) == -1) {
+			printf("%s: cannot extract phy addr\n", self->dv_xname);
+			return;
+		}
+	}
+
+	mvneta_wininit(sc);
+
+	if (OF_getproplen(faa->fa_node, "local-mac-address") ==
+	    ETHER_ADDR_LEN) {
+		OF_getprop(faa->fa_node, "local-mac-address",
+		    sc->sc_enaddr, ETHER_ADDR_LEN);
+		mvneta_enaddr_write(sc);
+	} else {
+		uint32_t maddrh, maddrl;
+		maddrh = MVNETA_READ(sc, MVNETA_MACAH);
+		maddrl = MVNETA_READ(sc, MVNETA_MACAL);
+		if (maddrh || maddrl) {
+			sc->sc_enaddr[0] = maddrh >> 24;
+			sc->sc_enaddr[1] = maddrh >> 16;
+			sc->sc_enaddr[2] = maddrh >> 8;
+			sc->sc_enaddr[3] = maddrh >> 0;
+			sc->sc_enaddr[4] = maddrl >> 8;
+			sc->sc_enaddr[5] = maddrl >> 0;
+		} else
+			ether_fakeaddr(&sc->sc_ac.ac_if);
+	}
+
+	printf("%s: Ethernet address %s\n", self->dv_xname,
+	    ether_sprintf(sc->sc_enaddr));
+
+	/* disable port */
+	MVNETA_WRITE(sc, MVNETA_PMACC0,
+	    MVNETA_READ(sc, MVNETA_PMACC0) & ~MVNETA_PMACC0_PORTEN);
+	delay(200);
+
+	/* clear all cause registers */
+	MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0);
+	MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0);
+	MVNETA_WRITE(sc, MVNETA_PMIC, 0);
+
+	/* mask all interrupts */
+	MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0);
+	MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0);
+	MVNETA_WRITE(sc, MVNETA_PMIM, 0);
+	MVNETA_WRITE(sc, MVNETA_PIE, 0);
+
+	/* enable MBUS Retry bit16 */
+	MVNETA_WRITE(sc, MVNETA_ERETRY, 0x20);
+
+	/* enable access for CPU0 */
+	MVNETA_WRITE(sc, MVNETA_PCP2Q(0),
+	    MVNETA_PCP2Q_RXQAE_ALL | MVNETA_PCP2Q_TXQAE_ALL);
+
+	/* reset RX and TX DMAs */
+	MVNETA_WRITE(sc, MVNETA_PRXINIT, MVNETA_PRXINIT_RXDMAINIT);
+	MVNETA_WRITE(sc, MVNETA_PTXINIT, MVNETA_PTXINIT_TXDMAINIT);
+
+	/* disable legacy WRR, disable EJP, release from reset */
+	MVNETA_WRITE(sc, MVNETA_TQC_1, 0);
+	for (i = 0; i < MVNETA_TX_QUEUE_CNT; i++) {
+		MVNETA_WRITE(sc, MVNETA_TQTBCOUNT(i), 0);
+		MVNETA_WRITE(sc, MVNETA_TQTBCONFIG(i), 0);
+	}
+
+	MVNETA_WRITE(sc, MVNETA_PRXINIT, 0);
+	MVNETA_WRITE(sc, MVNETA_PTXINIT, 0);
+
+	/* set port acceleration mode */
+	MVNETA_WRITE(sc, MVNETA_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM);
+
+	MVNETA_WRITE(sc, MVNETA_PXC, MVNETA_PXC_AMNOTXES | MVNETA_PXC_RXCS);
+	MVNETA_WRITE(sc, MVNETA_PXCX, 0);
+	MVNETA_WRITE(sc, MVNETA_PMFS, 64);
+
+	/* Set SDC register except IPGINT bits */
+	MVNETA_WRITE(sc, MVNETA_SDC,
+	    MVNETA_SDC_RXBSZ_16_64BITWORDS |
+	    MVNETA_SDC_BLMR |	/* Big/Little Endian Receive Mode: No swap */
+	    MVNETA_SDC_BLMT |	/* Big/Little Endian Transmit Mode: No swap */
+	    MVNETA_SDC_TXBSZ_16_64BITWORDS);
+
+	/* XXX: Disable PHY polling in hardware */
+	MVNETA_WRITE(sc, MVNETA_EUC,
+	    MVNETA_READ(sc, MVNETA_EUC) & ~MVNETA_EUC_POLLING);
+
+	/* Disable Auto-Negotiation */
+	MVNETA_WRITE(sc, MVNETA_PANC,
+	    MVNETA_READ(sc, MVNETA_PANC) & ~(MVNETA_PANC_INBANDANEN |
+	    MVNETA_PANC_ANSPEEDEN | MVNETA_PANC_ANDUPLEXEN));
+	MVNETA_WRITE(sc, MVNETA_OMSCD,
+	    MVNETA_READ(sc, MVNETA_OMSCD) & ~MVNETA_OMSCD_1MS_CLOCK_ENABLE);
+	MVNETA_WRITE(sc, MVNETA_PMACC2,
+	    MVNETA_READ(sc, MVNETA_PMACC2) & ~MVNETA_PMACC2_INBANDAN);
+
+	/* clear uni-/multicast tables */
+	uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT];
+	memset(dfut, 0, sizeof(dfut));
+	memset(dfsmt, 0, sizeof(dfut));
+	memset(dfomt, 0, sizeof(dfut));
+	MVNETA_WRITE_FILTER(sc, MVNETA_DFUT, dfut, MVNETA_NDFUT);
+	MVNETA_WRITE_FILTER(sc, MVNETA_DFSMT, dfut, MVNETA_NDFSMT);
+	MVNETA_WRITE_FILTER(sc, MVNETA_DFOMT, dfut, MVNETA_NDFOMT);
+
+	MVNETA_WRITE(sc, MVNETA_PIE,
+	    MVNETA_PIE_RXPKTINTRPTENB_ALL | MVNETA_PIE_TXPKTINTRPTENB_ALL);
+
+	MVNETA_WRITE(sc, MVNETA_EUIC, 0);
+
+	/* Setup phy. */
+	uint32_t ctrl = MVNETA_READ(sc, MVNETA_PMACC2);
+	switch (sc->sc_phy_mode) {
+	case PHY_MODE_QSGMII:
+		MVNETA_WRITE(sc, MVNETA_SERDESCFG,
+		    MVNETA_SERDESCFG_QSGMII_PROTO);
+		ctrl |= MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN;
+		break;
+	case PHY_MODE_SGMII:
+		MVNETA_WRITE(sc, MVNETA_SERDESCFG,
+		    MVNETA_SERDESCFG_SGMII_PROTO);
+		ctrl |= MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN;
+		break;
+	case PHY_MODE_RGMII:
+	case PHY_MODE_RGMII_ID:
+		ctrl |= MVNETA_PMACC2_RGMIIEN;
+		break;
+	}
+
+	ctrl &= ~MVNETA_PMACC2_PORTMACRESET;
+	MVNETA_WRITE(sc, MVNETA_PMACC2, ctrl);
+
+	while (MVNETA_READ(sc, MVNETA_PMACC2) & MVNETA_PMACC2_PORTMACRESET)
+		;
+
+	arm_intr_establish_fdt(faa->fa_node, IPL_NET, mvneta_intr, sc,
+	    sc->sc_dev.dv_xname);
+
+	ifp = &sc->sc_ac.ac_if;
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_start = mvneta_start;
+	ifp->if_ioctl = mvneta_ioctl;
+	ifp->if_watchdog = mvneta_watchdog;
+	ifp->if_capabilities = IFCAP_VLAN_MTU;
+
+#if notyet
+	/*
+	 * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
+	 */
+	ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 |
+				IFCAP_CSUM_UDPv4;
+
+	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
+	/*
+	 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums.
+	 */
+	ifp->if_capabilities &= ~IFCAP_CSUM_TCPv4;
+#endif
+
+	IFQ_SET_MAXLEN(&ifp->if_snd, max(MVNETA_TX_RING_CNT - 1, IFQ_MAXLEN));
+	strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof(ifp->if_xname));
+
+	/*
+	 * Do MII setup.
+	 */
+	sc->sc_mii.mii_ifp = ifp;
+	sc->sc_mii.mii_readreg = mvneta_miibus_readreg;
+	sc->sc_mii.mii_writereg = mvneta_miibus_writereg;
+	sc->sc_mii.mii_statchg = mvneta_miibus_statchg;
+
+	ifmedia_init(&sc->sc_mii.mii_media, 0,
+	    mvneta_mediachange, mvneta_mediastatus);
+
+	if (!sc->sc_fixed_link) {
+		extern void *mvmdio_sc;
+		sc->sc_mdio = mvmdio_sc;
+
+		if (sc->sc_mdio == NULL) {
+			config_defer(self, mvneta_attach_deferred);
+			return;
+		}
+
+		mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phy,
+		    MII_OFFSET_ANY, 0);
+		if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
+			printf("%s: no PHY found!\n", self->dv_xname);
+			ifmedia_add(&sc->sc_mii.mii_media,
+			    IFM_ETHER|IFM_MANUAL, 0, NULL);
+			ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
+		} else
+			ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+	} else {
+		ifmedia_add(&sc->sc_mii.mii_media,
+		    IFM_ETHER|IFM_MANUAL, 0, NULL);
+		ifmedia_set(&sc->sc_mii.mii_media,
+		    IFM_ETHER|IFM_MANUAL);
+
+		sc->sc_mii.mii_media_status = IFM_AVALID|IFM_ACTIVE;
+		sc->sc_mii.mii_media_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
+		mvneta_miibus_statchg(self);
+
+		ifp->if_baudrate = ifmedia_baudrate(sc->sc_mii.mii_media_active);
+		ifp->if_link_state = LINK_STATE_FULL_DUPLEX;
+	}
+
+	/*
+	 * Call MI attach routines.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+	return;
+}
+
+void
+mvneta_attach_deferred(struct device *self)
+{
+	struct mvneta_softc *sc = (struct mvneta_softc *) self;
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+
+	extern void *mvmdio_sc;
+	sc->sc_mdio = mvmdio_sc;
+	if (sc->sc_mdio == NULL) {
+		printf("%s: mdio bus not yet attached\n", self->dv_xname);
+		return;
+	}
+
+	mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phy,
+	    MII_OFFSET_ANY, 0);
+	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
+		printf("%s: no PHY found!\n", self->dv_xname);
+		ifmedia_add(&sc->sc_mii.mii_media,
+		    IFM_ETHER|IFM_MANUAL, 0, NULL);
+		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
+	} else
+		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+
+	/*
+	 * Call MI attach routines.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+	return;
+}
+
+void
+mvneta_tick(void *arg)
+{
+	struct mvneta_softc *sc = arg;
+	struct mii_data *mii = &sc->sc_mii;
+	int s;
+
+	s = splnet();
+	mii_tick(mii);
+	splx(s);
+
+	timeout_add(&sc->sc_tick_ch, hz);
+}
+
+int
+mvneta_intr(void *arg)
+{
+	struct mvneta_softc *sc = arg;
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+	uint32_t ic;
+
+	if (!(ifp->if_flags & IFF_RUNNING))
+		return 1;
+
+	ic = MVNETA_READ(sc, MVNETA_PRXTXTIC);
+
+	if (ic & MVNETA_PRXTXTI_TBTCQ(0))
+		mvneta_tx_proc(sc);
+
+	if (ic & MVNETA_PRXTXTI_RBICTAPQ(0))
+		mvneta_rx_proc(sc);
+
+	if (!IFQ_IS_EMPTY(&ifp->if_snd))
+		mvneta_start(ifp);
+
+	return 1;
+}
+
+void
+mvneta_start(struct ifnet *ifp)
+{
+	struct mvneta_softc *sc = ifp->if_softc;
+	struct mbuf *m_head = NULL;
+	int idx;
+
+	DPRINTFN(3, ("mvneta_start (idx %d)\n", sc->sc_tx_prod));
+
+	if (!(ifp->if_flags & IFF_RUNNING))
+		return;
+	if (ifq_is_oactive(&ifp->if_snd))
+		return;
+	if (IFQ_IS_EMPTY(&ifp->if_snd))
+		return;
+
+	/* If Link is DOWN, can't start TX */
+	if (!MVNETA_IS_LINKUP(sc))
+		return;
+
+	bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 0,
+	    MVNETA_DMA_LEN(sc->sc_txring),
+	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	idx = sc->sc_tx_prod;
+	while (sc->sc_tx_cnt < MVNETA_TX_RING_CNT) {
+		m_head = ifq_deq_begin(&ifp->if_snd);
+		if (m_head == NULL)
+			break;
+
+		/*
+		 * Pack the data into the transmit ring. If we
+		 * don't have room, set the OACTIVE flag and wait
+		 * for the NIC to drain the ring.
+		 */
+		if (mvneta_encap(sc, m_head, &idx)) {
+			ifq_deq_rollback(&ifp->if_snd, m_head);
+			ifq_set_oactive(&ifp->if_snd);
+			break;
+		}
+
+		/* now we are committed to transmit the packet */
+		ifq_deq_commit(&ifp->if_snd, m_head);
+
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+#if NBPFILTER > 0
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
+#endif
+	}
+
+	if (sc->sc_tx_prod != idx) {
+		sc->sc_tx_prod = idx;
+
+		/*
+		 * Set a timeout in case the chip goes out to lunch.
+		 */
+		ifp->if_timer = 5;
+	}
+}
+
+int
+mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr)
+{
+	struct mvneta_softc *sc = ifp->if_softc;
+	struct ifreq *ifr = (struct ifreq *)addr;
+	int s, error = 0;
+
+	s = splnet();
+
+	switch (cmd) {
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+		/* FALLTHROUGH */
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_flags & IFF_RUNNING)
+				error = ENETRESET;
+			else
+				mvneta_up(sc);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				mvneta_down(sc);
+		}
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		DPRINTFN(2, ("mvneta_ioctl MEDIA\n"));
+		error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
+		break;
+	case SIOCGIFRXR:
+		error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data,
+		    NULL, MCLBYTES, &sc->sc_rx_ring);
+		break;
+	default:
+		DPRINTFN(2, ("mvneta_ioctl ETHER\n"));
+		error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr);
+		break;
+	}
+
+	if (error == ENETRESET) {
+		if (ifp->if_flags & IFF_RUNNING) {
+			mvneta_filter_setup(sc);
+		}
+		error = 0;
+	}
+
+	splx(s);
+
+	return error;
+}
+
+void
+mvneta_port_up(struct mvneta_softc *sc)
+{
+	/* Enable port RX/TX. */
+	MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_ENQ(0));
+	MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(0));
+}
+
+int
+mvneta_up(struct mvneta_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+	struct mvneta_buf *txb, *rxb;
+	int i;
+
+	DPRINTFN(2, ("mvneta_up\n"));
+
+	/* Allocate Tx descriptor ring. */
+	sc->sc_txring = mvneta_dmamem_alloc(sc,
+	    MVNETA_TX_RING_CNT * sizeof(struct mvneta_tx_desc), 32);
+	sc->sc_txdesc = MVNETA_DMA_KVA(sc->sc_txring);
+
+	sc->sc_txbuf = malloc(sizeof(struct mvneta_buf) * MVNETA_TX_RING_CNT,
+	    M_DEVBUF, M_WAITOK);
+
+	for (i = 0; i < MVNETA_TX_RING_CNT; i++) {
+		txb = &sc->sc_txbuf[i];
+		bus_dmamap_create(sc->sc_dmat, MCLBYTES, MVNETA_NTXSEG,
+		    MCLBYTES, 0, BUS_DMA_WAITOK, &txb->tb_map);
+		txb->tb_m = NULL;
+	}
+
+	sc->sc_tx_prod = sc->sc_tx_cons = 0;
+	sc->sc_tx_cnt = 0;
+
+	/* Allocate Rx descriptor ring. */
+	sc->sc_rxring = mvneta_dmamem_alloc(sc,
+	    MVNETA_RX_RING_CNT * sizeof(struct mvneta_rx_desc), 32);
+	sc->sc_rxdesc = MVNETA_DMA_KVA(sc->sc_rxring);
+
+	sc->sc_rxbuf = malloc(sizeof(struct mvneta_buf) * MVNETA_RX_RING_CNT,
+	    M_DEVBUF, M_WAITOK);
+
+	for (i = 0; i < MVNETA_RX_RING_CNT; i++) {
+		rxb = &sc->sc_rxbuf[i];
+		bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
+		    MCLBYTES, 0, BUS_DMA_WAITOK, &rxb->tb_map);
+		rxb->tb_m = NULL;
+	}
+
+	/* Set Rx descriptor ring data. */
+	MVNETA_WRITE(sc, MVNETA_PRXDQA(0), MVNETA_DMA_DVA(sc->sc_rxring));
+	MVNETA_WRITE(sc, MVNETA_PRXDQS(0), MVNETA_RX_RING_CNT |
+	    ((MCLBYTES >> 3) << 19));
+	MVNETA_WRITE(sc, MVNETA_PRXDQTH(0), 0);
+	MVNETA_WRITE(sc, MVNETA_PRXC(0), 0);
+
+	/* Set Tx queue bandwidth. */
+	MVNETA_WRITE(sc, MVNETA_TQTBCOUNT(0), 0x03ffffff);
+	MVNETA_WRITE(sc, MVNETA_TQTBCONFIG(0), 0x03ffffff);
+
+	/* Set Tx descriptor ring data. */
+	MVNETA_WRITE(sc, MVNETA_PTXDQA(0), MVNETA_DMA_DVA(sc->sc_txring));
+	MVNETA_WRITE(sc, MVNETA_PTXDQS(0),
+	    MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT));
+
+	sc->sc_rx_prod = sc->sc_rx_cons = 0;
+
+	if_rxr_init(&sc->sc_rx_ring, 2, MVNETA_RX_RING_CNT);
+	mvneta_fill_rx_ring(sc);
+
+	/* TODO: correct frame size */
+	MVNETA_WRITE(sc, MVNETA_PMACC0,
+	    MVNETA_PMACC0_FRAMESIZELIMIT(MCLBYTES - MVNETA_HWHEADER_SIZE));
+
+	/* set max MTU */
+	MVNETA_WRITE(sc, MVNETA_TXMTU, MVNETA_TXMTU_MAX);
+	MVNETA_WRITE(sc, MVNETA_TXTKSIZE, 0xffffffff);
+	MVNETA_WRITE(sc, MVNETA_TXQTKSIZE(0), 0x7fffffff);
+
+	/* enable port */
+	MVNETA_WRITE(sc, MVNETA_PMACC0,
+	    MVNETA_READ(sc, MVNETA_PMACC0) | MVNETA_PMACC0_PORTEN);
+
+	mvneta_enaddr_write(sc);
+
+	mvneta_filter_setup(sc);
+
+	if (!sc->sc_fixed_link)
+		mii_mediachg(&sc->sc_mii);
+
+	if (sc->sc_link)
+		mvneta_port_up(sc);
+
+	/* Enable interrupt masks */
+	MVNETA_WRITE(sc, MVNETA_PRXTXTIM,
+	    MVNETA_PRXTXTI_RBICTAPQ(0) |
+	    MVNETA_PRXTXTI_TBTCQ(0));
+
+	timeout_add(&sc->sc_tick_ch, hz);
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifq_clr_oactive(&ifp->if_snd);
+
+	return 0;
+}
+
+void
+mvneta_down(struct mvneta_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+	uint32_t reg, txinprog, txfifoemp;
+	struct mvneta_buf *txb, *rxb;
+	int i, cnt;
+
+	DPRINTFN(2, ("mvneta_down\n"));
+
+	timeout_del(&sc->sc_tick_ch);
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg = MVNETA_READ(sc, MVNETA_RQC);
+	if (reg & MVNETA_RQC_ENQ_MASK)
+		/* Issue stop command for active channels only */
+		MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_DISQ_DISABLE(reg));
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	if (MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_ENQ(0))
+		MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_DISQ(0));
+
+	txinprog = MVNETA_PS_TXINPROG_(0);
+	txfifoemp = MVNETA_PS_TXFIFOEMP_(0);
+
+#define RX_DISABLE_TIMEOUT		0x1000000
+#define TX_FIFO_EMPTY_TIMEOUT		0x1000000
+	/* Wait for all Rx activity to terminate. */
+	cnt = 0;
+	do {
+		if (cnt >= RX_DISABLE_TIMEOUT) {
+			printf("%s: timeout for RX stopped. rqc 0x%x\n",
+			    sc->sc_dev.dv_xname, reg);
+			break;
+		}
+		cnt++;
+
+		/*
+		 * Check Receive Queue Command register that all Rx queues
+		 * are stopped
+		 */
+		reg = MVNETA_READ(sc, MVNETA_RQC);
+	} while (reg & 0xff);
+
+	/* Double check to verify that TX FIFO is empty */
+	cnt = 0;
+	while (1) {
+		do {
+			if (cnt >= TX_FIFO_EMPTY_TIMEOUT) {
+				printf("%s: timeout for TX FIFO empty. status "
+				    "0x%x\n", sc->sc_dev.dv_xname, reg);
+				break;
+			}
+			cnt++;
+
+			reg = MVNETA_READ(sc, MVNETA_PS);
+		} while (!(reg & txfifoemp) || reg & txinprog);
+
+		if (cnt >= TX_FIFO_EMPTY_TIMEOUT)
+			break;
+
+		/* Double check */
+		reg = MVNETA_READ(sc, MVNETA_PS);
+		if (reg & txfifoemp && !(reg & txinprog))
+			break;
+		else
+			printf("%s: TX FIFO empty double check failed."
+			    " %d loops, status 0x%x\n", sc->sc_dev.dv_xname,
+			    cnt, reg);
+	}
+
+	delay(200);
+
+	/* disable port */
+	MVNETA_WRITE(sc, MVNETA_PMACC0,
+	    MVNETA_READ(sc, MVNETA_PMACC0) & ~MVNETA_PMACC0_PORTEN);
+	delay(200);
+
+	/* clear all cause registers */
+	MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0);
+	MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0);
+	MVNETA_WRITE(sc, MVNETA_PMIC, 0);
+
+	/* mask all interrupts */
+	MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0);
+	MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0);
+	MVNETA_WRITE(sc, MVNETA_PMIM, 0);
+
+	/* Free RX and TX mbufs still in the queues. */
+	for (i = 0; i < MVNETA_TX_RING_CNT; i++) {
+		txb = &sc->sc_txbuf[i];
+		if (txb->tb_m) {
+			bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0,
+			    txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+			bus_dmamap_unload(sc->sc_dmat, txb->tb_map);
+			m_freem(txb->tb_m);
+		}
+		bus_dmamap_destroy(sc->sc_dmat, txb->tb_map);
+	}
+
+	mvneta_dmamem_free(sc, sc->sc_txring);
+	free(sc->sc_txbuf, M_DEVBUF, 0);
+
+	for (i = 0; i < MVNETA_RX_RING_CNT; i++) {
+		rxb = &sc->sc_rxbuf[i];
+		if (rxb->tb_m) {
+			bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0,
+			    rxb->tb_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(sc->sc_dmat, rxb->tb_map);
+			m_freem(rxb->tb_m);
+		}
+		bus_dmamap_destroy(sc->sc_dmat, rxb->tb_map);
+	}
+
+	mvneta_dmamem_free(sc, sc->sc_rxring);
+	free(sc->sc_rxbuf, M_DEVBUF, 0);
+
+	/* reset RX and TX DMAs */
+	MVNETA_WRITE(sc, MVNETA_PRXINIT, MVNETA_PRXINIT_RXDMAINIT);
+	MVNETA_WRITE(sc, MVNETA_PTXINIT, MVNETA_PTXINIT_TXDMAINIT);
+	MVNETA_WRITE(sc, MVNETA_PRXINIT, 0);
+	MVNETA_WRITE(sc, MVNETA_PTXINIT, 0);
+
+	ifp->if_flags &= ~IFF_RUNNING;
+	ifq_clr_oactive(&ifp->if_snd);
+}
+
+void
+mvneta_watchdog(struct ifnet *ifp)
+{
+	struct mvneta_softc *sc = ifp->if_softc;
+
+	/*
+	 * Reclaim first as there is a possibility of losing Tx completion
+	 * interrupts.
+	 */
+	mvneta_tx_proc(sc);
+	if (sc->sc_tx_cnt != 0) {
+		printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
+
+		ifp->if_oerrors++;
+	}
+}
+
+/*
+ * Set media options.
+ */
+int
+mvneta_mediachange(struct ifnet *ifp)
+{
+	struct mvneta_softc *sc = ifp->if_softc;
+
+	if (LIST_FIRST(&sc->sc_mii.mii_phys))
+		mii_mediachg(&sc->sc_mii);
+
+	return (0);
+}
+
+/*
+ * Report current media status.
+ */
+void
+mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct mvneta_softc *sc = ifp->if_softc;
+
+	if (LIST_FIRST(&sc->sc_mii.mii_phys)) {
+		mii_pollstat(&sc->sc_mii);
+		ifmr->ifm_active = sc->sc_mii.mii_media_active;
+		ifmr->ifm_status = sc->sc_mii.mii_media_status;
+	}
+
+	if (sc->sc_fixed_link) {
+		ifmr->ifm_active = sc->sc_mii.mii_media_active;
+		ifmr->ifm_status = sc->sc_mii.mii_media_status;
+	}
+}
+
+int
+mvneta_encap(struct mvneta_softc *sc, struct mbuf *m, uint32_t *idx)
+{
+	struct mvneta_tx_desc *txd;
+	bus_dmamap_t map;
+	uint32_t cmdsts;
+	int i, current, first, last;
+
+	DPRINTFN(3, ("mvneta_encap\n"));
+
+	first = last = current = *idx;
+	map = sc->sc_txbuf[current].tb_map;
+
+	if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT))
+		return (ENOBUFS);
+
+	if (map->dm_nsegs > (MVNETA_TX_RING_CNT - sc->sc_tx_cnt - 2)) {
+		bus_dmamap_unload(sc->sc_dmat, map);
+		return (ENOBUFS);
+	}
+
+	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
+	    BUS_DMASYNC_PREWRITE);
+
+	DPRINTFN(2, ("mvneta_encap: dm_nsegs=%d\n", map->dm_nsegs));
+
+	cmdsts = MVNETA_TX_L4_CSUM_NOT;
+#if notyet
+	int m_csumflags;
+	if (m_csumflags & M_CSUM_IPv4)
+		cmdsts |= MVNETA_TX_GENERATE_IP_CHKSUM;
+	if (m_csumflags & M_CSUM_TCPv4)
+		cmdsts |=
+		    MVNETA_TX_GENERATE_L4_CHKSUM | MVNETA_TX_L4_TYPE_TCP;
+	if (m_csumflags & M_CSUM_UDPv4)
+		cmdsts |=
+		    MVNETA_TX_GENERATE_L4_CHKSUM | MVNETA_TX_L4_TYPE_UDP;
+	if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
+		const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t);
+
+		cmdsts |= MVNETA_TX_IP_NO_FRAG |
+		    MVNETA_TX_IP_HEADER_LEN(iphdr_unitlen);	/* unit is 4B */
+	}
+#endif
+
+	for (i = 0; i < map->dm_nsegs; i++) {
+		txd = &sc->sc_txdesc[current];
+		memset(txd, 0, sizeof(*txd));
+		txd->bufptr = map->dm_segs[i].ds_addr;
+		txd->bytecnt = map->dm_segs[i].ds_len;
+		txd->cmdsts = cmdsts |
+		    MVNETA_TX_ZERO_PADDING;
+		if (i == 0)
+		    txd->cmdsts |= MVNETA_TX_FIRST_DESC;
+		if (i == (map->dm_nsegs - 1))
+		    txd->cmdsts |= MVNETA_TX_LAST_DESC;
+
+		bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring),
+		    current * sizeof(*txd), sizeof(*txd),
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+		last = current;
+		current = MVNETA_TX_RING_NEXT(current);
+		KASSERT(current != sc->sc_tx_cons);
+	}
+
+	KASSERT(sc->sc_txbuf[last].tb_m == NULL);
+	sc->sc_txbuf[first].tb_map = sc->sc_txbuf[last].tb_map;
+	sc->sc_txbuf[last].tb_map = map;
+	sc->sc_txbuf[last].tb_m = m;
+
+	sc->sc_tx_cnt += map->dm_nsegs;
+	*idx = current;
+
+	/* Let him know we sent another packet. */
+	MVNETA_WRITE(sc, MVNETA_PTXSU(0), map->dm_nsegs);
+
+	DPRINTFN(3, ("mvneta_encap: completed successfully\n"));
+
+	return 0;
+}
+
+void
+mvneta_rx_proc(struct mvneta_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+	struct mvneta_rx_desc *rxd;
+	struct mvneta_buf *rxb;
+	struct mbuf_list ml = MBUF_LIST_INITIALIZER();
+	struct mbuf *m;
+	uint32_t rxstat;
+	int i, idx, len, ready;
+
+	DPRINTFN(3, ("%s: %d\n", __func__, sc->sc_rx_cons));
+
+	if (!(ifp->if_flags & IFF_RUNNING))
+		return;
+
+	bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_rxring), 0,
+	    MVNETA_DMA_LEN(sc->sc_rxring),
+	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	ready = MVNETA_PRXS_ODC(MVNETA_READ(sc, MVNETA_PRXS(0)));
+	MVNETA_WRITE(sc, MVNETA_PRXSU(0), ready);
+
+	for (i = 0; i < ready; i++) {
+		idx = sc->sc_rx_cons;
+		KASSERT(idx < MVNETA_RX_RING_CNT);
+
+		rxd = &sc->sc_rxdesc[idx];
+
+#ifdef DIAGNOSTIC
+		if ((rxd->cmdsts &
+		    (MVNETA_RX_LAST_DESC | MVNETA_RX_FIRST_DESC)) !=
+		    (MVNETA_RX_LAST_DESC | MVNETA_RX_FIRST_DESC))
+			panic("%s: buffer size is smaller than packet",
+			    __func__);
+#endif
+
+		len = rxd->bytecnt;
+		rxb = &sc->sc_rxbuf[idx];
+		KASSERT(rxb->tb_m);
+
+		bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0,
+		    len, BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(sc->sc_dmat, rxb->tb_map);
+
+		m = rxb->tb_m;
+		rxb->tb_m = NULL;
+		m->m_pkthdr.len = m->m_len = len;
+
+		rxstat = rxd->cmdsts;
+		if (rxstat & MVNETA_ERROR_SUMMARY) {
+#if 0
+			int err = rxstat & MVNETA_RX_ERROR_CODE_MASK;
+
+			if (err == MVNETA_RX_CRC_ERROR)
+				ifp->if_ierrors++;
+			if (err == MVNETA_RX_OVERRUN_ERROR)
+				ifp->if_ierrors++;
+			if (err == MVNETA_RX_MAX_FRAME_LEN_ERROR)
+				ifp->if_ierrors++;
+			if (err == MVNETA_RX_RESOURCE_ERROR)
+				ifp->if_ierrors++;
+#else
+			ifp->if_ierrors++;
+#endif
+			panic("%s: handle input errors", __func__);
+			continue;
+		}
+
+#if notyet
+		if (rxstat & MVNETA_RX_IP_FRAME_TYPE) {
+			int flgs = 0;
+
+			/* Check IPv4 header checksum */
+			flgs |= M_CSUM_IPv4;
+			if (!(rxstat & MVNETA_RX_IP_HEADER_OK))
+				flgs |= M_CSUM_IPv4_BAD;
+			else if ((bufsize & MVNETA_RX_IP_FRAGMENT) == 0) {
+				/*
+				 * Check TCPv4/UDPv4 checksum for
+				 * non-fragmented packet only.
+				 *
+				 * It seemd that sometimes
+				 * MVNETA_RX_L4_CHECKSUM_OK bit was set to 0
+				 * even if the checksum is correct and the
+				 * packet was not fragmented. So we don't set
+				 * M_CSUM_TCP_UDP_BAD even if csum bit is 0.
+				 */
+
+				if (((rxstat & MVNETA_RX_L4_TYPE_MASK) ==
+					MVNETA_RX_L4_TYPE_TCP) &&
+				    ((rxstat & MVNETA_RX_L4_CHECKSUM_OK) != 0))
+					flgs |= M_CSUM_TCPv4;
+				else if (((rxstat & MVNETA_RX_L4_TYPE_MASK) ==
+					MVNETA_RX_L4_TYPE_UDP) &&
+				    ((rxstat & MVNETA_RX_L4_CHECKSUM_OK) != 0))
+					flgs |= M_CSUM_UDPv4;
+			}
+			m->m_pkthdr.csum_flags = flgs;
+		}
+#endif
+
+		/* Skip on first 2byte (HW header) */
+		m_adj(m, MVNETA_HWHEADER_SIZE);
+
+		ml_enqueue(&ml, m);
+
+		if_rxr_put(&sc->sc_rx_ring, 1);
+
+		sc->sc_rx_cons = MVNETA_RX_RING_NEXT(idx);
+	}
+
+	mvneta_fill_rx_ring(sc);
+
+	if_input(ifp, &ml);
+}
+
+void
+mvneta_tx_proc(struct mvneta_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+	struct mvneta_tx_desc *txd;
+	struct mvneta_buf *txb;
+	int i, idx, sent;
+
+	DPRINTFN(3, ("%s\n", __func__));
+
+	if (!(ifp->if_flags & IFF_RUNNING))
+		return;
+
+	bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 0,
+	    MVNETA_DMA_LEN(sc->sc_txring),
+	    BUS_DMASYNC_POSTREAD);
+
+	sent = MVNETA_PTXS_TBC(MVNETA_READ(sc, MVNETA_PTXS(0)));
+	MVNETA_WRITE(sc, MVNETA_PTXSU(0), MVNETA_PTXSU_NORB(sent));
+
+	for (i = 0; i < sent; i++) {
+		idx = sc->sc_tx_cons;
+		KASSERT(idx < MVNETA_TX_RING_CNT);
+
+		txd = &sc->sc_txdesc[idx];
+		txb = &sc->sc_txbuf[idx];
+		if (txb->tb_m) {
+			bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0,
+			    txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+			bus_dmamap_unload(sc->sc_dmat, txb->tb_map);
+
+			m_freem(txb->tb_m);
+			txb->tb_m = NULL;
+		}
+
+		ifq_clr_oactive(&ifp->if_snd);
+
+		sc->sc_tx_cnt--;
+
+		if (txd->cmdsts & MVNETA_ERROR_SUMMARY) {
+			int err = txd->cmdsts & MVNETA_TX_ERROR_CODE_MASK;
+
+			if (err == MVNETA_TX_LATE_COLLISION_ERROR)
+				ifp->if_collisions++;
+			if (err == MVNETA_TX_UNDERRUN_ERROR)
+				ifp->if_oerrors++;
+			if (err == MVNETA_TX_EXCESSIVE_COLLISION_ERRO)
+				ifp->if_collisions++;
+		}
+
+		sc->sc_tx_cons = MVNETA_TX_RING_NEXT(sc->sc_tx_cons);
+	}
+
+	if (sc->sc_tx_cnt == 0)
+		ifp->if_timer = 0;
+}
+
+uint8_t
+mvneta_crc8(const uint8_t *data, size_t size)
+{
+	int bit;
+	uint8_t byte;
+	uint8_t crc = 0;
+	const uint8_t poly = 0x07;
+
+	while(size--)
+	  for (byte = *data++, bit = NBBY-1; bit >= 0; bit--)
+	    crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0);
+
+	return crc;
+}
+
+CTASSERT(MVNETA_NDFSMT == MVNETA_NDFOMT);
+
+void
+mvneta_filter_setup(struct mvneta_softc *sc)
+{
+	struct arpcom *ac = &sc->sc_ac;
+	struct ifnet *ifp = &sc->sc_ac.ac_if;
+	struct ether_multi *enm;
+	struct ether_multistep step;
+	uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT];
+	uint32_t pxc;
+	int i;
+	const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00};
+
+	memset(dfut, 0, sizeof(dfut));
+	memset(dfsmt, 0, sizeof(dfsmt));
+	memset(dfomt, 0, sizeof(dfomt));
+
+	if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) {
+		goto allmulti;
+	}
+
+	ETHER_FIRST_MULTI(step, ac, enm);
+	while (enm != NULL) {
+		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
+			/* ranges are complex and somewhat rare */
+			goto allmulti;
+		}
+		/* chip handles some IPv4 multicast specially */
+		if (memcmp(enm->enm_addrlo, special, 5) == 0) {
+			i = enm->enm_addrlo[5];
+			dfsmt[i>>2] |=
+			    MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
+		} else {
+			i = mvneta_crc8(enm->enm_addrlo, ETHER_ADDR_LEN);
+			dfomt[i>>2] |=
+			    MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
+		}
+
+		ETHER_NEXT_MULTI(step, enm);
+	}
+	goto set;
+
+allmulti:
+	if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) {
+		for (i = 0; i < MVNETA_NDFSMT; i++) {
+			dfsmt[i] = dfomt[i] =
+			    MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
+			    MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
+			    MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
+			    MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
+		}
+	}
+
+set:
+	pxc = MVNETA_READ(sc, MVNETA_PXC);
+	pxc &= ~MVNETA_PXC_UPM;
+	pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP;
+	if (ifp->if_flags & IFF_BROADCAST) {
+		pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP);
+	}
+	if (ifp->if_flags & IFF_PROMISC) {
+		pxc |= MVNETA_PXC_UPM;
+	}
+	MVNETA_WRITE(sc, MVNETA_PXC, pxc);
+
+	/* Set Destination Address Filter Unicast Table */
+	i = sc->sc_enaddr[5] & 0xf;		/* last nibble */
+	dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
+	MVNETA_WRITE_FILTER(sc, MVNETA_DFUT, dfut, MVNETA_NDFUT);
+
+	/* Set Destination Address Filter Multicast Tables */
+	MVNETA_WRITE_FILTER(sc, MVNETA_DFSMT, dfsmt, MVNETA_NDFSMT);
+	MVNETA_WRITE_FILTER(sc, MVNETA_DFOMT, dfomt, MVNETA_NDFOMT);
+}
+
+struct mvneta_dmamem *
+mvneta_dmamem_alloc(struct mvneta_softc *sc, bus_size_t size, bus_size_t align)
+{
+	struct mvneta_dmamem *mdm;
+	int nsegs;
+
+	mdm = malloc(sizeof(*mdm), M_DEVBUF, M_WAITOK | M_ZERO);
+	mdm->mdm_size = size;
+
+	if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+	    BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &mdm->mdm_map) != 0)
+		goto mdmfree;
+
+	if (bus_dmamem_alloc(sc->sc_dmat, size, align, 0, &mdm->mdm_seg, 1,
+	    &nsegs, BUS_DMA_WAITOK) != 0)
+		goto destroy;
+
+	if (bus_dmamem_map(sc->sc_dmat, &mdm->mdm_seg, nsegs, size,
+	    &mdm->mdm_kva, BUS_DMA_WAITOK|BUS_DMA_COHERENT) != 0)
+		goto free;
+
+	if (bus_dmamap_load(sc->sc_dmat, mdm->mdm_map, mdm->mdm_kva, size,
+	    NULL, BUS_DMA_WAITOK) != 0)
+		goto unmap;
+
+	bzero(mdm->mdm_kva, size);
+
+	return (mdm);
+
+unmap:
+	bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, size);
+free:
+	bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1);
+destroy:
+	bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map);
+mdmfree:
+	free(mdm, M_DEVBUF, 0);
+
+	return (NULL);
+}
+
+void
+mvneta_dmamem_free(struct mvneta_softc *sc, struct mvneta_dmamem *mdm)
+{
+	bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, mdm->mdm_size);
+	bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1);
+	bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map);
+	free(mdm, M_DEVBUF, 0);
+}
+
+struct mbuf *
+mvneta_alloc_mbuf(struct mvneta_softc *sc, bus_dmamap_t map)
+{
+	struct mbuf *m = NULL;
+
+	m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES);
+	if (!m)
+		return (NULL);
+	m->m_len = m->m_pkthdr.len = MCLBYTES;
+
+	if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) {
+		printf("%s: could not load mbuf DMA map", sc->sc_dev.dv_xname);
+		m_freem(m);
+		return (NULL);
+	}
+
+	bus_dmamap_sync(sc->sc_dmat, map, 0,
+	    m->m_pkthdr.len, BUS_DMASYNC_PREREAD);
+
+	return (m);
+}
+
+void
+mvneta_fill_rx_ring(struct mvneta_softc *sc)
+{
+	struct mvneta_rx_desc *rxd;
+	struct mvneta_buf *rxb;
+	u_int slots;
+
+	for (slots = if_rxr_get(&sc->sc_rx_ring, MVNETA_RX_RING_CNT);
+	    slots > 0; slots--) {
+		rxb = &sc->sc_rxbuf[sc->sc_rx_prod];
+		rxb->tb_m = mvneta_alloc_mbuf(sc, rxb->tb_map);
+		if (rxb->tb_m == NULL)
+			break;
+
+		rxd = &sc->sc_rxdesc[sc->sc_rx_prod];
+		memset(rxd, 0, sizeof(*rxd));
+		rxd->bufptr = rxb->tb_map->dm_segs[0].ds_addr;
+
+		bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_rxring),
+		    sc->sc_rx_prod * sizeof(*rxd), sizeof(*rxd),
+		    BUS_DMASYNC_PREWRITE);
+
+		sc->sc_rx_prod = MVNETA_RX_RING_NEXT(sc->sc_rx_prod);
+
+		/* Tell him that there's a new free desc. */
+		MVNETA_WRITE(sc, MVNETA_PRXSU(0),
+		    MVNETA_PRXSU_NOOFNEWDESCRIPTORS(1));
+	}
+
+	if_rxr_put(&sc->sc_rx_ring, slots);
+}
diff --git a/sys/dev/fdt/if_mvnetareg.h b/sys/dev/fdt/if_mvnetareg.h
new file mode 100644
index 00000000000..cd851c64bbe
--- /dev/null
+++ b/sys/dev/fdt/if_mvnetareg.h
@@ -0,0 +1,845 @@
+/*	$OpenBSD: if_mvnetareg.h,v 1.1 2017/08/25 20:09:34 patrick Exp $	*/
+/*	$NetBSD: mvnetareg.h,v 1.8 2013/12/23 02:23:25 kiyohara Exp $	*/
+/*
+ * Copyright (c) 2007, 2013 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _MVNETAREG_H_
+#define _MVNETAREG_H_
+
+#define MVNETA_NWINDOW		6
+#define MVNETA_NREMAP		4
+
+#define MVNETA_PHY_TIMEOUT	10000	/* msec */
+
+/*
+ * Ethernet Unit Registers
+ */
+
+#define MVNETA_PRXC(q)		(0x1400 + ((q) << 2)) /*Port RX queues Config*/
+#define MVNETA_PRXSNP(q)	(0x1420 + ((q) << 2)) /* Port RX queues Snoop */
+#define MVNETA_PRXF01(q)	(0x1440 + ((q) << 2)) /* Port RX Prefetch 0_1 */
+#define MVNETA_PRXF23(q)	(0x1460 + ((q) << 2)) /* Port RX Prefetch 2_3 */
+#define MVNETA_PRXDQA(q)	(0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/
+#define MVNETA_PRXDQS(q)	(0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/
+#define MVNETA_PRXDQTH(q)	(0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/
+#define MVNETA_PRXS(q)		(0x14e0 + ((q) << 2)) /*Port RX queues Status */
+#define MVNETA_PRXSU(q)		(0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/
+#define MVNETA_PPLBSZ(q)	(0x1700 + ((q) << 2)) /* P Pool n Buffer Size */
+#define MVNETA_PRXFC		0x1710	/* Port RX Flow Control */
+#define MVNETA_PRXTXP		0x1714	/* Port RX_TX Pause */
+#define MVNETA_PRXFCG		0x1718	/* Port RX Flow Control Generation */
+#define MVNETA_PRXINIT		0x1cc0	/* Port RX Initialization */
+#define MVNETA_RXCTRL		0x1d00	/* RX Control */
+#define MVNETA_RXHWFWD(n)	(0x1d10 + (((n) & ~0x1) << 1))
+				/* RX Hardware Forwarding (0_1, 2_3,..., 8_9) */
+#define MVNETA_RXHWFWDPTR	0x1d30	/* RX Hardware Forwarding Pointer */
+#define MVNETA_RXHWFWDTH	0x1d40	/* RX Hardware Forwarding Threshold */
+#define MVNETA_RXHWFWDDQA	0x1d44	/* RX Hw Fwd Descriptors Queue Address*/
+#define MVNETA_RXHWFWDQS	0x1d48	/* RX Hw Fwd Descriptors Queue Size */
+#define MVNETA_RXHWFWDQENB	0x1d4c	/* RX Hw Fwd Queue Enable */
+#define MVNETA_RXHWFWDACPT	0x1d50	/* RX Hw Forwarding Accepted Counter */
+#define MVNETA_RXHWFWDYDSCRD	0x1d54	/* RX Hw Fwd Yellow Discarded Counter */
+#define MVNETA_RXHWFWDGDSCRD	0x1d58	/* RX Hw Fwd Green Discarded Counter */
+#define MVNETA_RXHWFWDTHDSCRD	0x1d5c	/*RX HwFwd Threshold Discarded Counter*/
+#define MVNETA_RXHWFWDTXGAP	0x1d6c	/*RX Hardware Forwarding TX Access Gap*/
+
+/* Ethernet Unit Global Registers */
+#define MVNETA_PHYADDR		0x2000
+#define MVNETA_SMI		0x2004
+#define MVNETA_EUDA		0x2008	/* Ethernet Unit Default Address */
+#define MVNETA_EUDID		0x200c	/* Ethernet Unit Default ID */
+#define MVNETA_ERETRY		0x2010	/* Ethernet Unit MBUS Retry */
+#define MVNETA_EU 		0x2014	/* Ethernet Unit Reserved */
+#define MVNETA_EUIC 		0x2080	/* Ethernet Unit Interrupt Cause */
+#define MVNETA_EUIM 		0x2084	/* Ethernet Unit Interrupt Mask */
+#define MVNETA_EUEA 		0x2094	/* Ethernet Unit Error Address */
+#define MVNETA_EUIAE 		0x2098	/* Ethernet Unit Internal Addr Error */
+#define MVNETA_EUPCR 		0x20a0	/* EthernetUnit Port Pads Calibration */
+#define MVNETA_EUC 		0x20b0	/* Ethernet Unit Control */
+
+#define MVNETA_BASEADDR(n)	(0x2200 + ((n) << 3))	/* Base Address */
+#define MVNETA_S(n)		(0x2204 + ((n) << 3))	/* Size */
+#define MVNETA_HA(n)		(0x2280 + ((n) << 2))	/* High Address Remap */
+#define MVNETA_BARE 		0x2290	/* Base Address Enable */
+#define MVNETA_EPAP 		0x2294	/* Ethernet Port Access Protect */
+
+/* Ethernet Unit Port Registers */
+#define MVNETA_PXC		0x2400	/* Port Configuration */
+#define MVNETA_PXCX		0x2404	/* Port Configuration Extend */
+#define MVNETA_MIISP		0x2408	/* MII Serial Parameters */
+#define MVNETA_GMIISP		0x240c	/* GMII Serial Params */
+#define MVNETA_EVLANE		0x2410	/* VLAN EtherType */
+#define MVNETA_MACAL		0x2414	/* MAC Address Low */
+#define MVNETA_MACAH		0x2418	/* MAC Address High */
+#define MVNETA_SDC		0x241c	/* SDMA Configuration */
+#define MVNETA_DSCP(n)		(0x2420 + ((n) << 2))
+#define MVNETA_PSC		0x243c	/* Port Serial Control0 */
+#define MVNETA_VPT2P		0x2440	/* VLAN Priority Tag to Priority */
+#define MVNETA_PS		0x2444	/* Ethernet Port Status */
+#define MVNETA_TQC		0x2448	/* Transmit Queue Command */
+#define MVNETA_PSC1		0x244c	/* Port Serial Control1 */
+#define MVNETA_MH		0x2454	/* Marvell Header */
+#define MVNETA_MTU		0x2458	/* Max Transmit Unit */
+#define MVNETA_IC		0x2460	/* Port Interrupt Cause */
+#define MVNETA_ICE		0x2464	/* Port Interrupt Cause Extend */
+#define MVNETA_PIM		0x2468	/* Port Interrupt Mask */
+#define MVNETA_PEIM		0x246c	/* Port Extend Interrupt Mask */
+#define MVNETA_PRFUT		0x2470	/* Port Rx FIFO Urgent Threshold */
+#define MVNETA_PTFUT		0x2474	/* Port Tx FIFO Urgent Threshold */
+#define MVNETA_PXTFTT		0x2478	/* Port Tx FIFO Threshold */
+#define MVNETA_PMFS		0x247c	/* Port Rx Minimal Frame Size */
+#define MVNETA_PXDFC		0x2484	/* Port Rx Discard Frame Counter */
+#define MVNETA_POFC		0x2488	/* Port Overrun Frame Counter */
+#define MVNETA_PIAE		0x2494	/* Port Internal Address Error */
+#define MVNETA_AIP0ADR		0x2498	/* Arp IP0 Address */
+#define MVNETA_AIP1ADR		0x249c	/* Arp IP1 Address */
+#define MVNETA_SERDESCFG	0x24a0	/* Serdes Configuration */
+#define MVNETA_SERDESSTS	0x24a4	/* Serdes Status */
+#define MVNETA_ETP		0x24bc	/* Ethernet Type Priority */
+#define MVNETA_TQFPC		0x24dc	/* Transmit Queue Fixed Priority Cfg */
+#define MVNETA_TQC_1		0x24e4
+#define MVNETA_OMSCD		0x24f4	/* One mS Clock Divider */
+#define MVNETA_PFCCD		0x24f8	/* Periodic Flow Control Clock Divider*/
+#define MVNETA_PACC		0x2500	/* Port Acceleration Mode */
+#define MVNETA_PBMADDR		0x2504	/* Port BM Address */
+#define MVNETA_PV		0x25bc	/* Port Version */
+#define MVNETA_CRDP(n)		(0x260c + ((n) << 4))
+			/* Ethernet Current Receive Descriptor Pointers */
+#define MVNETA_RQC		0x2680	/* Receive Queue Command */
+#define MVNETA_TCSDP		0x2684	/* Tx Current Served Desc Pointer */
+#define MVNETA_TCQDP		0x26c0	/* Tx Current Queue Desc Pointer */
+#define MVNETA_TQTBCOUNT(q)	(0x2700 + ((q) << 4))
+				/* Transmit Queue Token-Bucket Counter */
+#define MVNETA_TQTBCONFIG(q)	(0x2704 + ((q) << 4))
+				/* Transmit Queue Token-Bucket Configuration */
+#define MVNETA_TQAC(q)		(0x2708 + ((q) << 4))
+				/* Transmit Queue Arbiter Configuration */
+
+#define MVNETA_PCP2Q(cpu)	(0x2540 + ((cpu) << 2))	/* Port CPUn to Queue */
+#define MVNETA_PRXITTH(q)	(0x2540 + ((q) << 2) /* Port RX Intr Threshold*/
+#define MVNETA_PRXTXTIC		0x25a0	/*Port RX_TX Threshold Interrupt Cause*/
+#define MVNETA_PRXTXTIM		0x25a4	/*Port RX_TX Threshold Interrupt Mask */
+#define MVNETA_PRXTXIC		0x25a8	/* Port RX_TX Interrupt Cause */
+#define MVNETA_PRXTXIM		0x25ac	/* Port RX_TX Interrupt Mask */
+#define MVNETA_PMIC		0x25b0	/* Port Misc Interrupt Cause */
+#define MVNETA_PMIM		0x25b4	/* Port Misc Interrupt Mask */
+#define MVNETA_PIE		0x25b8	/* Port Interrupt Enable */
+
+#define MVNETA_PMACC0		0x2c00	/* Port MAC Control 0 */
+#define MVNETA_PMACC1		0x2c04	/* Port MAC Control 1 */
+#define MVNETA_PMACC2		0x2c08	/* Port MAC Control 2 */
+#define MVNETA_PANC		0x2c0c	/* Port Auto-Negotiation Configuration*/
+#define MVNETA_PS0		0x2c10	/* Port Status 0 */
+#define MVNETA_PSPC		0x2c14	/* Port Serial Parameters Config */
+#define MVNETA_PIC_2		0x2c20	/* Port Interrupt Cause */
+#define MVNETA_PIM_2		0x2c24	/* Port Interrupt Mask */
+#define MVNETA_PPRBSS		0x2c38	/* Port PRBS Status */
+#define MVNETA_PPRBSEC		0x2c3c	/* Port PRBS Error Counter */
+#define MVNETA_PMACC3		0x2c48	/* Port MAC Control 3 */
+#define MVNETA_CCFCPST(p)	(0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/
+#define MVNETA_PMACC4		0x2c90	/* Port MAC Control 4 */
+#define MVNETA_PSP1C		0x2c94	/* Port Serial Parameters 1 Config */
+#define MVNETA_LPIC0		0x2cc0	/* LowPowerIdle control 0 */
+#define MVNETA_LPIC1		0x2cc4	/* LPI control 1 */
+#define MVNETA_LPIC2		0x2cc8	/* LPI control 2 */
+#define MVNETA_LPIS		0x2ccc	/* LPI status */
+#define MVNETA_LPIC		0x2cd0	/* LPI counter */
+
+#define MVNETA_PPLLC		0x2e04	/* Power and PLL Control */
+#define MVNETA_DLE		0x2e8c	/* Digital Loopback Enable */
+#define MVNETA_RCS		0x2f18	/* Reference Clock Select */
+
+/* MAC MIB Counters 		0x3000 - 0x307c */
+
+/* Rx DMA Wake on LAN Registers	0x3690 - 0x36b8 */
+
+#define MVNETA_NDFSMT		 0x40
+#define MVNETA_DFSMT		0x3400
+			/* Destination Address Filter Special Multicast Table */
+#define MVNETA_NDFOMT		 0x40
+#define MVNETA_DFOMT		0x3500
+			/* Destination Address Filter Other Multicast Table */
+#define MVNETA_NDFUT		  0x4
+#define MVNETA_DFUT		0x3600
+			/* Destination Address Filter Unicast Table */
+
+#define MVNETA_PTXDQA(q)	(0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/
+#define MVNETA_PTXDQS(q)	(0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/
+#define MVNETA_PTXS(q)		(0x3c40 + ((q) << 2)) /* Port TX queues Status*/
+#define MVNETA_PTXSU(q)		(0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/
+#define MVNETA_PTXDI(q)		(0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/
+#define MVNETA_TXTBC(q)		(0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
+#define MVNETA_PTXINIT		0x3cf0	/* Port TX Initialization */
+#define MVNETA_PTXDOSD		0x3cf4	/* Port TX Disable Outstanding Reads */
+
+#define MVNETA_TXBADFCS		0x3cc0	/*Tx Bad FCS Transmitted Pckts Counter*/
+#define MVNETA_TXDROPPED	0x3cc4	/* Tx Dropped Packets Counter */
+#define MVNETA_TXNB		0x3cfc	/* Tx Number of New Bytes */
+#define MVNETA_TXGB		0x3d00	/* Tx Green Number of Bytes */
+#define MVNETA_TXYB		0x3d04	/* Tx Yellow Number of Bytes */
+
+/* Tx DMA Packet Modification Registers	0x3d00 - 0x3dff */
+
+/* Tx DMA Queue Arbiter Registers	0x3e00 - 0x3eff */
+#define MVNETA_TXMTU		0x3e0c	/* Tx Max MTU */
+#define MVNETA_TXMTU_MAX	0x3ffff
+#define MVNETA_TXTKSIZE		0x3e14	/* Tx Token Size */
+#define MVNETA_TXQTKSIZE(q)	(0x3e40 + ((q) << 2)) /* Tx Token Size */
+
+
+/* PHY Address (MVNETA_PHYADDR) */
+#define MVNETA_PHYADDR_PHYAD_MASK	0x1f
+#define MVNETA_PHYADDR_PHYAD(port, phy)	((phy) << ((port) * 5))
+
+/* SMI register fields (MVNETA_SMI) */
+#define MVNETA_SMI_DATA_MASK		0x0000ffff
+#define MVNETA_SMI_PHYAD(phy)		(((phy) & 0x1f) << 16)
+#define MVNETA_SMI_REGAD(reg)		(((reg) & 0x1f) << 21)
+#define MVNETA_SMI_OPCODE_WRITE		(0 << 26)
+#define MVNETA_SMI_OPCODE_READ		(1 << 26)
+#define MVNETA_SMI_READVALID		(1 << 27)
+#define MVNETA_SMI_BUSY			(1 << 28)
+
+/* Ethernet Unit Default ID (MVNETA_EUDID) */
+#define MVNETA_EUDID_DIDR_MASK		0x0000000f
+#define MVNETA_EUDID_DATTR_MASK		0x00000ff0
+
+/* Ethernet Unit Reserved (MVNETA_EU) */
+#define MVNETA_EU_FASTMDC 		(1 << 0)
+#define MVNETA_EU_ACCS 			(1 << 1)
+
+/* Ethernet Unit Interrupt Cause (MVNETA_EUIC) */
+#define MVNETA_EUIC_ETHERINTSUM 	(1 << 0)
+#define MVNETA_EUIC_PARITY 		(1 << 1)
+#define MVNETA_EUIC_ADDRVIOL		(1 << 2)
+#define MVNETA_EUIC_ADDRVNOMATCH	(1 << 3)
+#define MVNETA_EUIC_SMIDONE		(1 << 4)
+#define MVNETA_EUIC_COUNTWA		(1 << 5)
+#define MVNETA_EUIC_INTADDRERR		(1 << 7)
+#define MVNETA_EUIC_PORT0DPERR		(1 << 9)
+#define MVNETA_EUIC_TOPDPERR		(1 << 12)
+
+/* Ethernet Unit Internal Addr Error (MVNETA_EUIAE) */
+#define MVNETA_EUIAE_INTADDR_MASK 	0x000001ff
+
+/* Ethernet Unit Port Pads Calibration (MVNETA_EUPCR) */
+#define MVNETA_EUPCR_DRVN_MASK		0x0000001f
+#define MVNETA_EUPCR_TUNEEN		(1 << 16)
+#define MVNETA_EUPCR_LOCKN_MASK		0x003e0000
+#define MVNETA_EUPCR_OFFSET_MASK	0x1f000000	/* Reserved */
+#define MVNETA_EUPCR_WREN		(1U << 31)
+
+/* Ethernet Unit Control (MVNETA_EUC) */
+#define MVNETA_EUC_PORT0DPPAR 		(1 << 0)
+#define MVNETA_EUC_POLLING	 	(1 << 1)
+#define MVNETA_EUC_TOPDPPAR	 	(1 << 3)
+#define MVNETA_EUC_PORT0PW 		(1 << 16)
+#define MVNETA_EUC_PORTRESET	 	(1 << 24)
+#define MVNETA_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25)
+
+/* Base Address (MVNETA_BASEADDR) */
+#define MVNETA_BASEADDR_TARGET(target)	((target) & 0xf)
+#define MVNETA_BASEADDR_ATTR(attr)	(((attr) & 0xff) << 8)
+#define MVNETA_BASEADDR_BASE(base)	((base) & 0xffff0000)
+
+/* Size (MVNETA_S) */
+#define MVNETA_S_SIZE(size)		(((size) - 1) & 0xffff0000)
+
+/* Base Address Enable (MVNETA_BARE) */
+#define MVNETA_BARE_EN_MASK		((1 << MVNETA_NWINDOW) - 1)
+#define MVNETA_BARE_EN(win)		((1 << (win)) & MVNETA_BARE_EN_MASK)
+
+/* Ethernet Port Access Protect (MVNETA_EPAP) */
+#define MVNETA_EPAP_AC_NAC		0x0	/* No access allowed */
+#define MVNETA_EPAP_AC_RO		0x1	/* Read Only */
+#define MVNETA_EPAP_AC_FA		0x3	/* Full access (r/w) */
+#define MVNETA_EPAP_EPAR(win, ac)	((ac) << ((win) * 2))
+
+/* Port Configuration (MVNETA_PXC) */
+#define MVNETA_PXC_UPM			(1 << 0) /* Uni Promisc mode */
+#define MVNETA_PXC_RXQ(q)		((q) << 1)
+#define MVNETA_PXC_RXQ_MASK		MVNETA_PXC_RXQ(7)
+#define MVNETA_PXC_RXQARP(q)		((q) << 4)
+#define MVNETA_PXC_RXQARP_MASK		MVNETA_PXC_RXQARP(7)
+#define MVNETA_PXC_RB			(1 << 7) /* Rej mode of MAC */
+#define MVNETA_PXC_RBIP			(1 << 8)
+#define MVNETA_PXC_RBARP		(1 << 9)
+#define MVNETA_PXC_AMNOTXES		(1 << 12)
+#define MVNETA_PXC_RBARPF		(1 << 13)
+#define MVNETA_PXC_TCPCAPEN		(1 << 14)
+#define MVNETA_PXC_UDPCAPEN		(1 << 15)
+#define MVNETA_PXC_TCPQ(q)		((q) << 16)
+#define MVNETA_PXC_TCPQ_MASK		MVNETA_PXC_TCPQ(7)
+#define MVNETA_PXC_UDPQ(q)		((q) << 19)
+#define MVNETA_PXC_UDPQ_MASK		MVNETA_PXC_UDPQ(7)
+#define MVNETA_PXC_BPDUQ(q)		((q) << 22)
+#define MVNETA_PXC_BPDUQ_MASK		MVNETA_PXC_BPDUQ(7)
+#define MVNETA_PXC_RXCS			(1 << 25)
+
+/* Port Configuration Extend (MVNETA_PXCX) */
+#define MVNETA_PXCX_SPAN		(1 << 1)
+#define MVNETA_PXCX_TXCRCDIS		(1 << 3)
+
+/* MII Serial Parameters (MVNETA_MIISP) */
+#define MVNETA_MIISP_JAMLENGTH_12KBIT	0x00000000
+#define MVNETA_MIISP_JAMLENGTH_24KBIT	0x00000001
+#define MVNETA_MIISP_JAMLENGTH_32KBIT	0x00000002
+#define MVNETA_MIISP_JAMLENGTH_48KBIT	0x00000003
+#define MVNETA_MIISP_JAMIPG(x)		(((x) & 0x7c) << 0)
+#define MVNETA_MIISP_IPGJAMTODATA(x)	(((x) & 0x7c) << 5)
+#define MVNETA_MIISP_IPGDATA(x)		(((x) & 0x7c) << 10)
+#define MVNETA_MIISP_DATABLIND(x)	(((x) & 0x1f) << 17)
+
+/* GMII Serial Parameters (MVNETA_GMIISP) */
+#define MVNETA_GMIISP_IPGDATA(x)	(((x) >> 4) & 0x7)
+
+/* SDMA Configuration (MVNETA_SDC) */
+#define MVNETA_SDC_RIFB			(1 << 0)
+#define MVNETA_SDC_RXBSZ(x)		((x) << 1)
+#define MVNETA_SDC_RXBSZ_MASK		MVNETA_SDC_RXBSZ(7)
+#define MVNETA_SDC_RXBSZ_1_64BITWORDS	MVNETA_SDC_RXBSZ(0)
+#define MVNETA_SDC_RXBSZ_2_64BITWORDS	MVNETA_SDC_RXBSZ(1)
+#define MVNETA_SDC_RXBSZ_4_64BITWORDS	MVNETA_SDC_RXBSZ(2)
+#define MVNETA_SDC_RXBSZ_8_64BITWORDS	MVNETA_SDC_RXBSZ(3)
+#define MVNETA_SDC_RXBSZ_16_64BITWORDS	MVNETA_SDC_RXBSZ(4)
+#define MVNETA_SDC_BLMR			(1 << 4)
+#define MVNETA_SDC_BLMT			(1 << 5)
+#define MVNETA_SDC_SWAPMODE		(1 << 6)
+#define MVNETA_SDC_IPGINTRX_V1_MASK	__BITS(21, 8)
+#define MVNETA_SDC_IPGINTRX_V2_MASK	(__BIT(25) | __BITS(21, 7))
+#define MVNETA_SDC_IPGINTRX_V1(x)	(((x) << 4)			\
+						& MVNETA_SDC_IPGINTRX_V1_MASK)
+#define MVNETA_SDC_IPGINTRX_V2(x)	((((x) & 0x8000) << 10) 	\
+						| (((x) & 0x7fff) << 7))
+#define MVNETA_SDC_IPGINTRX_V1_MAX	0x3fff
+#define MVNETA_SDC_IPGINTRX_V2_MAX	0xffff
+#define MVNETA_SDC_TXBSZ(x)		((x) << 22)
+#define MVNETA_SDC_TXBSZ_MASK		MVNETA_SDC_TXBSZ(7)
+#define MVNETA_SDC_TXBSZ_1_64BITWORDS	MVNETA_SDC_TXBSZ(0)
+#define MVNETA_SDC_TXBSZ_2_64BITWORDS	MVNETA_SDC_TXBSZ(1)
+#define MVNETA_SDC_TXBSZ_4_64BITWORDS	MVNETA_SDC_TXBSZ(2)
+#define MVNETA_SDC_TXBSZ_8_64BITWORDS	MVNETA_SDC_TXBSZ(3)
+#define MVNETA_SDC_TXBSZ_16_64BITWORDS	MVNETA_SDC_TXBSZ(4)
+
+/* Port Serial Control (MVNETA_PSC) */
+#define MVNETA_PSC_PORTEN		(1 << 0)
+#define MVNETA_PSC_FLP			(1 << 1) /* Force_Link_Pass */
+#define MVNETA_PSC_ANDUPLEX		(1 << 2)	/* auto nego */
+#define MVNETA_PSC_ANFC			(1 << 3)
+#define MVNETA_PSC_PAUSEADV		(1 << 4)
+#define MVNETA_PSC_FFCMODE		(1 << 5)	/* Force FC */
+#define MVNETA_PSC_FBPMODE		(1 << 7)	/* Back pressure */
+#define MVNETA_PSC_RESERVED		(1 << 9)	/* Must be set to 1 */
+#define MVNETA_PSC_FLFAIL		(1 << 10)	/* Force Link Fail */
+#define MVNETA_PSC_ANSPEED		(1 << 13)
+#define MVNETA_PSC_DTEADVERT		(1 << 14)
+#define MVNETA_PSC_MRU(x)		((x) << 17)
+#define MVNETA_PSC_MRU_MASK		MVNETA_PSC_MRU(7)
+#define MVNETA_PSC_MRU_1518		0
+#define MVNETA_PSC_MRU_1522		1
+#define MVNETA_PSC_MRU_1552		2
+#define MVNETA_PSC_MRU_9022		3
+#define MVNETA_PSC_MRU_9192		4
+#define MVNETA_PSC_MRU_9700		5
+#define MVNETA_PSC_SETFULLDX		(1 << 21)
+#define MVNETA_PSC_SETFCEN		(1 << 22)
+#define MVNETA_PSC_SETGMIISPEED		(1 << 23)
+#define MVNETA_PSC_SETMIISPEED		(1 << 24)
+
+/* Ethernet Port Status (MVNETA_PS) */
+#define MVNETA_PS_LINKUP		(1 << 1)
+#define MVNETA_PS_FULLDX		(1 << 2)
+#define MVNETA_PS_ENFC			(1 << 3)
+#define MVNETA_PS_GMIISPEED		(1 << 4)
+#define MVNETA_PS_MIISPEED		(1 << 5)
+#define MVNETA_PS_TXINPROG		(1 << 7)
+#define MVNETA_PS_TXFIFOEMP		(1 << 10)	/* FIFO Empty */
+#define MVNETA_PS_RXFIFOEMPTY		(1 << 16)
+/* Armada XP */
+#define MVNETA_PS_TXINPROG_MASK		(0xff << 0)
+#define MVNETA_PS_TXINPROG_(q)		(1 << ((q) + 0))
+#define MVNETA_PS_TXFIFOEMP_MASK	(0xff << 8)
+#define MVNETA_PS_TXFIFOEMP_(q)		(1 << ((q) + 8))
+
+/* Transmit Queue Command (MVNETA_TQC) */
+#define MVNETA_TQC_ENQ(q)		(1 << ((q) + 0))/* Enable Q */
+#define MVNETA_TQC_DISQ(q)		(1 << ((q) + 8))/* Disable Q */
+
+/* Port Serial Control 1 (MVNETA_PSC1) */
+#define MVNETA_PSC1_PCSLB		(1 << 1)
+#define MVNETA_PSC1_RGMIIEN		(1 << 3)	/* RGMII */
+#define MVNETA_PSC1_PRST		(1 << 4)	/* Port Reset */
+
+/* Port Interrupt Cause (MVNETA_IC) */
+#define MVNETA_IC_RXBUF			(1 << 0)
+#define MVNETA_IC_EXTEND		(1 << 1)
+#define MVNETA_IC_RXBUFQ_MASK		(0xff << 2)
+#define MVNETA_IC_RXBUFQ(q)		(1 << ((q) + 2))
+#define MVNETA_IC_RXERROR		(1 << 10)
+#define MVNETA_IC_RXERRQ_MASK		(0xff << 11)
+#define MVNETA_IC_RXERRQ(q)		(1 << ((q) + 11))
+#define MVNETA_IC_TXEND(q)		(1 << ((q) + 19))
+#define MVNETA_IC_ETHERINTSUM		(1U << 31)
+
+/* Port Interrupt Cause Extend (MVNETA_ICE) */
+#define MVNETA_ICE_TXBUF_MASK		(0xff << + 0)
+#define MVNETA_ICE_TXBUF(q)		(1 << ((q) + 0))
+#define MVNETA_ICE_TXERR_MASK		(0xff << + 8)
+#define MVNETA_ICE_TXERR(q)		(1 << ((q) + 8))
+#define MVNETA_ICE_PHYSTC		(1 << 16)
+#define MVNETA_ICE_PTP			(1 << 17)
+#define MVNETA_ICE_RXOVR		(1 << 18)
+#define MVNETA_ICE_TXUDR		(1 << 19)
+#define MVNETA_ICE_LINKCHG		(1 << 20)
+#define MVNETA_ICE_SERDESREALIGN	(1 << 21)
+#define MVNETA_ICE_INTADDRERR		(1 << 23)
+#define MVNETA_ICE_SYNCCHANGED		(1 << 24)
+#define MVNETA_ICE_PRBSERROR		(1 << 25)
+#define MVNETA_ICE_ETHERINTSUM		(1U << 31)
+
+/* Port Tx FIFO Urgent Threshold (MVNETA_PTFUT) */
+#define MVNETA_PTFUT_IPGINTTX_V1_MASK	__BITS(17, 4)
+#define MVNETA_PTFUT_IPGINTTX_V2_MASK	__BITS(19, 4)
+#define MVNETA_PTFUT_IPGINTTX_V1(x)   __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V1_MASK)
+#define MVNETA_PTFUT_IPGINTTX_V2(x)   __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V2_MASK)
+#define MVNETA_PTFUT_IPGINTTX_V1_MAX	0x3fff
+#define MVNETA_PTFUT_IPGINTTX_V2_MAX	0xffff
+
+/* Port Rx Minimal Frame Size (MVNETA_PMFS) */
+#define MVNETA_PMFS_RXMFS(rxmfs)		(((rxmfs) - 40) & 0x7c)
+					/* RxMFS = 40,44,48,52,56,60,64 bytes */
+
+/* Transmit Queue Fixed Priority Configuration */
+#define MVNETA_TQFPC_EN(q)		(1 << (q))
+
+/* Receive Queue Command (MVNETA_RQC) */
+#define MVNETA_RQC_ENQ_MASK		(0xff << 0)	/* Enable Q */
+#define MVNETA_RQC_ENQ(n)		(1 << (0 + (n)))
+#define MVNETA_RQC_DISQ_MASK		(0xff << 8)	/* Disable Q */
+#define MVNETA_RQC_DISQ(n)		(1 << (8 + (n)))
+#define MVNETA_RQC_DISQ_DISABLE(q)	((q) << 8)
+
+/* Destination Address Filter Registers (MVNETA_DF{SM,OM,U}T) */
+#define MVNETA_DF(n, x)			((x) << (8 * (n)))
+#define MVNETA_DF_PASS			(1 << 0)
+#define MVNETA_DF_QUEUE(q)		((q) << 1)
+#define MVNETA_DF_QUEUE_MASK		((7) << 1)
+
+/* One mS Clock Divider (MVNETA_OMSCD) */
+#define MVNETA_OMSCD_1MS_CLOCK_ENABLE	(1U << 31)
+
+/* Port Acceleration Mode (MVNETA_PACC) */
+#define MVGVE_PACC_ACCELERATIONMODE_MASK	0x7
+#define MVGVE_PACC_ACCELERATIONMODE_BM		0x0	/* Basic Mode */
+#define MVGVE_PACC_ACCELERATIONMODE_EDM		0x1	/* Enhanced Desc Mode */
+#define MVGVE_PACC_ACCELERATIONMODE_EDMBM	0x2	/*   with BM */
+#define MVGVE_PACC_ACCELERATIONMODE_EDMPNC	0x3	/*   with PnC */
+#define MVGVE_PACC_ACCELERATIONMODE_EDMBPMNC	0x4	/*   with BM & PnC */
+
+/* Port BM Address (MVNETA_PBMADDR) */
+#define MVNETA_PBMADDR_BMADDRESS_MASK	0xfffff800
+
+/* Port Serdes Config (MVNETA_SERDESCFG) */
+#define MVNETA_SERDESCFG_SGMII_PROTO	0x0cc7
+#define MVNETA_SERDESCFG_QSGMII_PROTO	0x0667
+
+/* Ether Type Priority (MVNETA_ETP) */
+#define MVNETA_ETP_ETHERTYPEPRIEN	(1 << 0)	/* EtherType Prio Ena */
+#define MVNETA_ETP_ETHERTYPEPRIFRSTEN	(1 << 1)
+#define MVNETA_ETP_ETHERTYPEPRIQ		(0x7 << 2)	/*EtherType Prio Queue*/
+#define MVNETA_ETP_ETHERTYPEPRIVAL	(0xffff << 5)	/*EtherType Prio Value*/
+#define MVNETA_ETP_FORCEUNICSTHIT	(1 << 21)	/* Force Unicast hit */
+
+/* RX Hardware Forwarding (0_1, 2_3,..., 8_9) (MVNETA_RXHWFWD) */
+#define MVNETA_RXHWFWD_PORT_BASEADDRESS(p, x)	xxxxx
+
+/* RX Hardware Forwarding Pointer (MVNETA_RXHWFWDPTR) */
+#define MVNETA_RXHWFWDPTR_QUEUENO(q)	((q) << 8)	/* Queue Number */
+#define MVNETA_RXHWFWDPTR_PORTNO(p)	((p) << 11)	/* Port Number */
+
+/* RX Hardware Forwarding Threshold (MVNETA_RXHWFWDTH) */
+#define MVNETA_RXHWFWDTH_DROPRNDGENBITS(n)	(((n) & 0x3ff) << 0)
+#define MVNETA_RXHWFWDTH_DROPTHRESHOLD(n)	(((n) & 0xf) << 16)
+
+/* RX Control (MVNETA_RXCTRL) */
+#define MVNETA_RXCTRL_PACKETCOLORSRCSELECT(x)	(1 << 0)
+#define MVNETA_RXCTRL_GEMPORTIDSRCSEL(x)	((x) << 4)
+#define MVNETA_RXCTRL_TXHWFRWMQSRC(x)		(1 << 8)
+#define MVNETA_RXCTRL_RX_MH_SELECT(x)		((x) << 12)
+#define MVNETA_RXCTRL_RX_TX_SRC_SELECT		(1 << 16)
+#define MVNETA_RXCTRL_HWFRWDENB			(1 << 17)
+#define MVNETA_RXCTRL_HWFRWDSHORTPOOLID(id)	(((id) & 0x3) << 20)
+#define MVNETA_RXCTRL_HWFRWDLONGPOOLID(id)	(((id) & 0x3) << 22)
+
+/* Port RX queues Configuration (MVNETA_PRXC) */
+#define MVNETA_PRXC_POOLIDSHORT(i)	(((i) & 0x3) << 4)
+#define MVNETA_PRXC_POOLIDLONG(i)	(((i) & 0x3) << 6)
+#define MVNETA_PRXC_PACKETOFFSET(o)	(((o) & 0xf) << 8)
+#define MVNETA_PRXC_USERPREFETCHCMND0	(1 << 16)
+
+/* Port RX queues Snoop (MVNETA_PRXSNP) */
+#define MVNETA_PRXSNP_SNOOPNOOFBYTES(b)	(((b) & 0x3fff) << 0)
+#define MVNETA_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16)
+
+/* Port RX queues Snoop (MVNETA_PRXSNP) */
+#define MVNETA_PRXF01_PREFETCHCOMMAND0(c) (((c) & 0xffff) << 0) xxxx
+#define MVNETA_PRXF01_PREFETCHCOMMAND1(c) (((c) & 0xffff) << 16) xxxx
+
+/* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */
+#define MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x0003fff) << 0)
+#define MVNETA_PRXDQS_BUFFERSIZE(s)	(((s) & 0xfff80000) << 19)
+
+/* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */
+					/* Occupied Descriptors Threshold */
+#define MVNETA_PRXDQTH_ODT(x)		(((x) & 0x3fff) << 0)
+					/* Non Occupied Descriptors Threshold */
+#define MVNETA_PRXDQTH_NODT(x)		(((x) & 0x3fff) << 16)
+
+/* Port RX queues Status (MVNETA_PRXS) */
+					/* Occupied Descriptors Counter */
+#define MVNETA_PRXS_ODC(x)		(((x) >> 0) & 0x3fff)
+					/* Non Occupied Descriptors Counter */
+#define MVNETA_PRXS_NODC(x)		(((x) >> 16) & 0x3fff)
+
+/* Port RX queues Status Update (MVNETA_PRXSU) */
+#define MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0)
+#define MVNETA_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16)
+
+/* Port RX Flow Control (MVNETA_PRXFC) */
+#define MVNETA_PRXFC_PERPRIOFCGENCONTROL	(1 << 0)
+#define MVNETA_PRXFC_TXPAUSECONTROL		(1 << 1)
+
+/* Port RX_TX Pause (MVNETA_PRXTXP) */
+#define MVNETA_PRXTXP_TXPAUSE(x)		((x) & 0xff)
+
+/* Port RX Flow Control Generation (MVNETA_PRXFCG) */
+#define MVNETA_PRXFCG_PERPRIOFCGENDATA		(1 << 0)
+#define MVNETA_PRXFCG_PERPRIOFCGENQNO(x)	(((x) & 0x7) << 4)
+
+/* Port RX Initialization (MVNETA_PRXINIT) */
+#define MVNETA_PRXINIT_RXDMAINIT		(1 << 0)
+
+/* TX Number of New Bytes (MVNETA_TXNB) */
+#define MVNETA_TXNB_NOOFNEWBYTES(b)	(((b) & 0xffff) << 0)
+#define MVNETA_TXNB_PKTQNO(q)		(((q) & 0x7) << 28)
+#define MVNETA_TXNB_PKTCOLOR		(1U << 31)
+
+/* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */
+					/* Descriptors Queue Size */
+#define MVNETA_PTXDQS_DQS(x)		(((x) & 0x3fff) << 0)
+					/* Transmitted Buffer Threshold */
+#define MVNETA_PTXDQS_TBT(x)		(((x) & 0x3fff) << 16)
+
+/* Port TX queues Status (MVNETA_PTXS) */
+					/* Pending Descriptors Counter */
+#define MVNETA_PTXDQS_PDC(x)		(((x) >> 0) & 0x3fff)
+					/* Transmitted Buffer Counter */
+#define MVNETA_PTXS_TBC(x)		(((x) >> 16) & 0x3fff)
+
+/* Port TX queues Status Update (MVNETA_PTXSU) */
+					/* Number Of Written Descriptoes */
+#define MVNETA_PTXSU_NOWD(x)		(((x) & 0xff) << 0)
+					/* Number Of Released Buffers */
+#define MVNETA_PTXSU_NORB(x)		(((x) & 0xff) << 16)
+
+/* TX Transmitted Buffers Counter (MVNETA_TXTBC) */
+					/* Transmitted Buffers Counter */
+#define MVNETA_TXTBC_TBC(x)		(((x) & 0x3fff) << 16)
+
+/* Port TX Initialization (MVNETA_PTXINIT) */
+#define MVNETA_PTXINIT_TXDMAINIT	(1 << 0)
+
+/* Marvell Header (MVNETA_MH) */
+#define MVNETA_MH_MHEN			(1 << 0)
+#define MVNETA_MH_DAPREFIX		(0x3 << 1)
+#define MVNETA_MH_SPID			(0xf << 4)
+#define MVNETA_MH_MHMASK		(0x3 << 8)
+#define MVNETA_MH_MHMASK_8QUEUES	(0x0 << 8)
+#define MVNETA_MH_MHMASK_4QUEUES	(0x1 << 8)
+#define MVNETA_MH_MHMASK_2QUEUES	(0x3 << 8)
+#define MVNETA_MH_DSAEN_MASK		(0x3 << 10)
+#define MVNETA_MH_DSAEN_DISABLE		(0x0 << 10)
+#define MVNETA_MH_DSAEN_NONEXTENDED	(0x1 << 10)
+#define MVNETA_MH_DSAEN_EXTENDED		(0x2 << 10)
+
+/* Port Auto-Negotiation Configuration (MVNETA_PANC) */
+#define MVNETA_PANC_FORCELINKFAIL	(1 << 0)
+#define MVNETA_PANC_FORCELINKPASS	(1 << 1)
+#define MVNETA_PANC_INBANDANEN		(1 << 2)
+#define MVNETA_PANC_INBANDANBYPASSEN	(1 << 3)
+#define MVNETA_PANC_INBANDRESTARTAN	(1 << 4)
+#define MVNETA_PANC_SETMIISPEED		(1 << 5)
+#define MVNETA_PANC_SETGMIISPEED	(1 << 6)
+#define MVNETA_PANC_ANSPEEDEN		(1 << 7)
+#define MVNETA_PANC_SETFCEN		(1 << 8)
+#define MVNETA_PANC_PAUSEADV		(1 << 9)
+#define MVNETA_PANC_ANFCEN		(1 << 11)
+#define MVNETA_PANC_SETFULLDX		(1 << 12)
+#define MVNETA_PANC_ANDUPLEXEN		(1 << 13)
+#define MVNETA_PANC_RESERVED		(1 << 15)
+
+/* Port MAC Control 0 (MVNETA_PMACC0) */
+#define MVNETA_PMACC0_PORTEN		(1 << 0)
+#define MVNETA_PMACC0_PORTTYPE		(1 << 1)
+#define MVNETA_PMACC0_FRAMESIZELIMIT(x)	((((x) >> 1) & 0x7ffc) << 2)
+#define MVNETA_PMACC0_RESERVED		(1 << 15)
+
+/* Port MAC Control 1 (MVNETA_PMACC1) */
+#define MVNETA_PMACC1_PCSLB		(1 << 6)
+
+/* Port MAC Control 2 (MVNETA_PMACC2) */
+#define MVNETA_PMACC2_INBANDAN		(1 << 0)
+#define MVNETA_PMACC2_PCSEN		(1 << 3)
+#define MVNETA_PMACC2_RGMIIEN		(1 << 4)
+#define MVNETA_PMACC2_PADDINGDIS	(1 << 5)
+#define MVNETA_PMACC2_PORTMACRESET	(1 << 6)
+#define MVNETA_PMACC2_PRBSCHECKEN	(1 << 10)
+#define MVNETA_PMACC2_PRBSGENEN		(1 << 11)
+#define MVNETA_PMACC2_SDTT_MASK		(3 << 12)  /* Select Data To Transmit */
+#define MVNETA_PMACC2_SDTT_RM		(0 << 12)	/* Regular Mode */
+#define MVNETA_PMACC2_SDTT_PRBS		(1 << 12)	/* PRBS Mode */
+#define MVNETA_PMACC2_SDTT_ZC		(2 << 12)	/* Zero Constant */
+#define MVNETA_PMACC2_SDTT_OC		(3 << 12)	/* One Constant */
+#define MVNETA_PMACC2_RESERVED		(3 << 14)
+
+/* Port MAC Control 3 (MVNETA_PMACC3) */
+#define MVNETA_PMACC3_IPG_MASK		0x7f80
+
+/* Port Interrupt Cause/Mask (MVNETA_PIC_2/MVNETA_PIM_2) */
+#define MVNETA_PI_2_INTSUM		(1 << 0)
+#define MVNETA_PI_2_LSC			(1 << 1)   /* LinkStatus Change */
+#define MVNETA_PI_2_ACOP		(1 << 2)   /* AnCompleted OnPort */
+#define MVNETA_PI_2_AOOR		(1 << 5)   /* AddressOut Of Range */
+#define MVNETA_PI_2_SSC			(1 << 6)   /* SyncStatus Change */
+#define MVNETA_PI_2_PRBSEOP		(1 << 7)   /* QSGMII PRBS error */
+#define MVNETA_PI_2_MIBCWA		(1 << 15)  /* MIB counter wrap around */
+#define MVNETA_PI_2_QSGMIIPRBSE		(1 << 10)  /* QSGMII PRBS error */
+#define MVNETA_PI_2_PCSRXPRLPI		(1 << 11)  /* PCS Rx path received LPI*/
+#define MVNETA_PI_2_PCSTXPRLPI		(1 << 12)  /* PCS Tx path received LPI*/
+#define MVNETA_PI_2_MACRXPRLPI		(1 << 13)  /* MAC Rx path received LPI*/
+#define MVNETA_PI_2_MIBCCD		(1 << 14)  /* MIB counters copy done */
+
+/* LPI Control 0 (MVNETA_LPIC0) */
+#define MVNETA_LPIC0_LILIMIT(x)		(((x) & 0xff) << 0)
+#define MVNETA_LPIC0_TSLIMIT(x)		(((x) & 0xff) << 8)
+
+/* LPI Control 1 (MVNETA_LPIC1) */
+#define MVNETA_LPIC1_LPIRE		(1 << 0)	/* LPI request enable */
+#define MVNETA_LPIC1_LPIRF		(1 << 1)	/* LPI request force */
+#define MVNETA_LPIC1_LPIMM		(1 << 2)	/* LPI manual mode */
+#define MVNETA_LPIC1_TWLIMIT		(((x) & 0xfff) << 4)
+
+/* LPI Status (MVNETA_LPIS) */
+#define MVNETA_LPIS_PCSRXPLPIS		(1 << 0) /* PCS Rx path LPI status */
+#define MVNETA_LPIS_PCSTXPLPIS		(1 << 1) /* PCS Tx path LPI status */
+#define MVNETA_LPIS_MACRXPLPIS		(1 << 2)/* MAC Rx path LP idle status */
+#define MVNETA_LPIS_MACTXPLPWS		(1 << 3)/* MAC Tx path LP wait status */
+#define MVNETA_LPIS_MACTXPLPIS		(1 << 4)/* MAC Tx path LP idle status */
+
+/* Port PRBS Status (MVNETA_PPRBSS) */
+#define MVNETA_PPRBSS_PRBSCHECKLOCKED	(1 << 0)
+#define MVNETA_PPRBSS_PRBSCHECKRDY	(1 << 1)
+
+/* Port Status 0 (MVNETA_PS0) */
+#define MVNETA_PS0_LINKUP		(1 << 0)
+#define MVNETA_PS0_GMIISPEED		(1 << 1)
+#define MVNETA_PS0_MIISPEED		(1 << 2)
+#define MVNETA_PS0_FULLDX		(1 << 3)
+#define MVNETA_PS0_RXFCEN		(1 << 4)
+#define MVNETA_PS0_TXFCEN		(1 << 5)
+#define MVNETA_PS0_PRP			(1 << 6) /* Port Rx Pause */
+#define MVNETA_PS0_PTP			(1 << 7) /* Port Tx Pause */
+#define MVNETA_PS0_PDP			(1 << 8) /*Port is Doing Back-Pressure*/
+#define MVNETA_PS0_SYNCFAIL10MS		(1 << 10)
+#define MVNETA_PS0_ANDONE		(1 << 11)
+#define MVNETA_PS0_IBANBA		(1 << 12) /* InBand AutoNeg BypassAct */
+#define MVNETA_PS0_SYNCOK		(1 << 14)
+
+/* Port CPUn to Queue (MVNETA_PCP2Q) */
+#define MVNETA_PCP2Q_RXQAE_ALL		(0xff << 0)/*QueueAccessEnable*/
+#define MVNETA_PCP2Q_TXQAE_ALL		(0xff << 8)/*QueueAccessEnable*/
+
+/* Port RX_TX Threshold Interrupt Cause/Mask (MVNETA_PRXTXTIC/MVNETA_PRXTXTIM) */
+#define MVNETA_PRXTXTI_TBTCQ(q)		(1 << ((q) + 0))
+#define MVNETA_PRXTXTI_RBICTAPQ(q)	(1 << ((q) + 8))
+#define MVNETA_PRXTXTI_RDTAQ(q)		(1 << ((q) + 16))
+#define MVNETA_PRXTXTI_PRXTXICSUMMARY	(1 << 29)
+#define MVNETA_PRXTXTI_PTXERRORSUMMARY	(1 << 30)
+#define MVNETA_PRXTXTI_PMISCICSUMMARY	(1U << 31)
+
+/* Port RX_TX Interrupt Cause/Mask (MVNETA_PRXTXIC/MVNETA_PRXTXIM) */
+#define MVNETA_PRXTXI_TBRQ(q)		(1 << ((q) + 0))
+#define MVNETA_PRXTXI_RPQ(q)		(1 << ((q) + 8))
+#define MVNETA_PRXTXI_RREQ(q)		(1 << ((q) + 16))
+#define MVNETA_PRXTXI_PRXTXTHICSUMMARY	(1 << 29)
+#define MVNETA_PRXTXI_PTXERRORSUMMARY	(1 << 30)
+#define MVNETA_PRXTXI_PMISCICSUMMARY	(1U << 31)
+
+/* Port Misc Interrupt Cause/Mask (MVNETA_PMIC/MVNETA_PMIM) */
+#define MVNETA_PMI_PHYSTATUSCHNG	(1 << 0)
+#define MVNETA_PMI_LINKCHANGE		(1 << 1)
+#define MVNETA_PMI_PTP			(1 << 4)
+#define MVNETA_PMI_PME			(1 << 6) /* Packet Modification Error */
+#define MVNETA_PMI_IAE			(1 << 7) /* Internal Address Error */
+#define MVNETA_PMI_RXOVERRUN		(1 << 8)
+#define MVNETA_PMI_RXCRCERROR		(1 << 9)
+#define MVNETA_PMI_RXLARGEPACKET		(1 << 10)
+#define MVNETA_PMI_TXUNDRN		(1 << 11)
+#define MVNETA_PMI_PRBSERROR		(1 << 12)
+#define MVNETA_PMI_PSCSYNCCHNG		(1 << 13)
+#define MVNETA_PMI_SRSE			(1 << 14) /* SerdesRealignSyncError */
+#define MVNETA_PMI_RNBTP(q)		(1 << ((q) + 16)) /* RxNoBuffersToPool*/
+#define MVNETA_PMI_TREQ(q)		(1 << ((q) + 24)) /* TxResourceErrorQ */
+
+/* Port Interrupt Enable (MVNETA_PIE) */
+#define MVNETA_PIE_RXPKTINTRPTENB_ALL	(0xff << 24)
+#define MVNETA_PIE_TXPKTINTRPTENB_ALL	(0xff << 8)
+
+/* Power and PLL Control (MVNETA_PPLLC) */
+#define MVNETA_PPLLC_REF_FREF_SEL_MASK	(0xf << 0)
+#define MVNETA_PPLLC_PHY_MODE_MASK	(7 << 5)
+#define MVNETA_PPLLC_PHY_MODE_SATA	(0 << 5)
+#define MVNETA_PPLLC_PHY_MODE_SAS	(1 << 5)
+#define MVNETA_PPLLC_PLL_LOCK		(1 << 8)
+#define MVNETA_PPLLC_PU_DFE		(1 << 10)
+#define MVNETA_PPLLC_PU_TX_INTP		(1 << 11)
+#define MVNETA_PPLLC_PU_TX		(1 << 12)
+#define MVNETA_PPLLC_PU_RX		(1 << 13)
+#define MVNETA_PPLLC_PU_PLL		(1 << 14)
+
+/* Digital Loopback Enable (MVNETA_DLE) */
+#define MVNETA_DLE_LOCAL_SEL_BITS_MASK	(3 << 10)
+#define MVNETA_DLE_LOCAL_SEL_BITS_10BITS	(0 << 10)
+#define MVNETA_DLE_LOCAL_SEL_BITS_20BITS	(1 << 10)
+#define MVNETA_DLE_LOCAL_SEL_BITS_40BITS	(2 << 10)
+#define MVNETA_DLE_LOCAL_RXPHER_TO_TX_EN	(1 << 12)
+#define MVNETA_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13)
+#define MVNETA_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14)
+#define MVNETA_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15)
+
+/* Reference Clock Select (MVNETA_RCS) */
+#define MVNETA_RCS_REFCLK_SEL		(1 << 10)
+
+
+/*
+ * Set the chip's packet size limit to 9022.
+ * (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN)
+ */
+#define MVNETA_MRU		9022
+
+#define MVNETA_RXBUF_ALIGN	32	/* Cache line size */
+#define MVNETA_RXBUF_MASK	(MVNETA_RXBUF_ALIGN - 1)
+#define MVNETA_HWHEADER_SIZE	2
+
+
+/*
+ * DMA descriptors
+ *    Despite the documentation saying these descriptors only need to be
+ *    aligned to 16-byte bondaries, 32-byte alignment seems to be required
+ *    by the hardware.  We'll just pad them out to that to make it easier.
+ */
+struct mvneta_tx_desc {
+#if BYTE_ORDER == BIG_ENDIAN
+	uint16_t bytecnt;		/* Descriptor buffer byte count */
+	uint16_t l4ichk;		/* CPU provided TCP Checksum */
+	uint32_t cmdsts;		/* Descriptor command status */
+	uint32_t nextdescptr;		/* Next descriptor pointer */
+	uint32_t bufptr;		/* Descriptor buffer pointer */
+#else	/* LITTLE_ENDIAN */
+	uint32_t cmdsts;		/* Descriptor command status */
+	uint16_t l4ichk;		/* CPU provided TCP Checksum */
+	uint16_t bytecnt;		/* Descriptor buffer byte count */
+	uint32_t bufptr;		/* Descriptor buffer pointer */
+	uint32_t nextdescptr;		/* Next descriptor pointer */
+#endif
+	uint32_t _padding[4];
+} __packed;
+
+struct mvneta_rx_desc {
+#if BYTE_ORDER == BIG_ENDIAN
+	uint16_t bytecnt;		/* Descriptor buffer byte count */
+	uint16_t bufsize;		/* Buffer size */
+	uint32_t cmdsts;		/* Descriptor command status */
+	uint32_t nextdescptr;		/* Next descriptor pointer */
+	uint32_t bufptr;		/* Descriptor buffer pointer */
+#else	/* LITTLE_ENDIAN */
+	uint32_t cmdsts;		/* Descriptor command status */
+	uint16_t bufsize;		/* Buffer size */
+	uint16_t bytecnt;		/* Descriptor buffer byte count */
+	uint32_t bufptr;		/* Descriptor buffer pointer */
+	uint32_t nextdescptr;		/* Next descriptor pointer */
+#endif
+	uint32_t _padding[4];
+} __packed;
+
+#define MVNETA_ERROR_SUMMARY		(1 << 0)
+#define MVNETA_BUFFER_OWNED_MASK		(1U << 31)
+#define MVNETA_BUFFER_OWNED_BY_HOST	(0U << 31)
+#define MVNETA_BUFFER_OWNED_BY_DMA	(1U << 31)
+
+#define MVNETA_TX_ERROR_CODE_MASK	(3 << 1)
+#define MVNETA_TX_LATE_COLLISION_ERROR	(0 << 1)
+#define MVNETA_TX_UNDERRUN_ERROR	(1 << 1)
+#define MVNETA_TX_EXCESSIVE_COLLISION_ERRO (2 << 1)
+#define MVNETA_TX_LLC_SNAP_FORMAT	(1 << 9)
+#define MVNETA_TX_IP_NO_FRAG		(1 << 10)
+#define MVNETA_TX_IP_HEADER_LEN(len)	((len) << 11)
+#define MVNETA_TX_VLAN_TAGGED_FRAME	(1 << 15)
+#define MVNETA_TX_L4_TYPE_TCP		(0 << 16)
+#define MVNETA_TX_L4_TYPE_UDP		(1 << 16)
+#define MVNETA_TX_GENERATE_L4_CHKSUM	(1 << 17)
+#define MVNETA_TX_GENERATE_IP_CHKSUM	(1 << 18)
+#define MVNETA_TX_ZERO_PADDING		(1 << 19)
+#define MVNETA_TX_LAST_DESC		(1 << 20)
+#define MVNETA_TX_FIRST_DESC		(1 << 21)
+#define MVNETA_TX_GENERATE_CRC		(1 << 22)
+#define MVNETA_TX_ENABLE_INTERRUPT	(1 << 23)
+#define MVNETA_TX_L4_CSUM_FULL		(1 << 30)
+#define MVNETA_TX_L4_CSUM_NOT		(1U << 31)
+
+#define MVNETA_RX_ERROR_CODE_MASK	(3 << 1)
+#define MVNETA_RX_CRC_ERROR		(0 << 1)
+#define MVNETA_RX_OVERRUN_ERROR		(1 << 1)
+#define MVNETA_RX_MAX_FRAME_LEN_ERROR	(2 << 1)
+#define MVNETA_RX_RESOURCE_ERROR	(3 << 1)
+#define MVNETA_RX_L4_CHECKSUM_MASK	(0xffff << 3)
+#define MVNETA_RX_VLAN_TAGGED_FRAME	(1 << 19)
+#define MVNETA_RX_BPDU_FRAME		(1 << 20)
+#define MVNETA_RX_L4_TYPE_MASK		(3 << 21)
+#define MVNETA_RX_L4_TYPE_TCP		(0 << 21)
+#define MVNETA_RX_L4_TYPE_UDP		(1 << 21)
+#define MVNETA_RX_L4_TYPE_OTHER		(2 << 21)
+#define MVNETA_RX_NOT_LLC_SNAP_FORMAT	(1 << 23)
+#define MVNETA_RX_IP_FRAME_TYPE		(1 << 24)
+#define MVNETA_RX_IP_HEADER_OK		(1 << 25)
+#define MVNETA_RX_LAST_DESC		(1 << 26)
+#define MVNETA_RX_FIRST_DESC		(1 << 27)
+#define MVNETA_RX_UNKNOWN_DA		(1 << 28)
+#define MVNETA_RX_ENABLE_INTERRUPT	(1 << 29)
+#define MVNETA_RX_L4_CHECKSUM_OK	(1 << 30)
+
+#define MVNETA_RX_IP_FRAGMENT		(1 << 2)
+
+#endif	/* _MVGEREG_H_ */
diff --git a/sys/dev/fdt/mvmdio.c b/sys/dev/fdt/mvmdio.c
new file mode 100644
index 00000000000..ffcafda915e
--- /dev/null
+++ b/sys/dev/fdt/mvmdio.c
@@ -0,0 +1,177 @@
+/*	$OpenBSD: mvmdio.c,v 1.1 2017/08/25 20:09:34 patrick Exp $	*/
+/*	$NetBSD: if_mvneta.c,v 1.41 2015/04/15 10:15:40 hsuenaga Exp $	*/
+/*
+ * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_pinctrl.h>
+#include <dev/ofw/fdt.h>
+
+#include <dev/fdt/if_mvnetareg.h>
+
+#include <net/if.h>
+
+#define MVNETA_READ(sc, reg) \
+	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
+#define MVNETA_WRITE(sc, reg, val) \
+	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+
+struct mvmdio_softc {
+	struct device sc_dev;
+
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+
+	struct mutex sc_mtx;
+};
+
+struct mvmdio_softc *mvmdio_sc;
+
+static int mvmdio_match(struct device *, void *, void *);
+static void mvmdio_attach(struct device *, struct device *, void *);
+
+int mvmdio_miibus_readreg(struct device *, int, int);
+void mvmdio_miibus_writereg(struct device *, int, int, int);
+
+struct cfdriver mvmdio_cd = {
+	NULL, "mvmdio", DV_DULL
+};
+
+struct cfattach mvmdio_ca = {
+	sizeof (struct mvmdio_softc), mvmdio_match, mvmdio_attach,
+};
+
+static int
+mvmdio_match(struct device *parent, void *cfdata, void *aux)
+{
+	struct fdt_attach_args *faa = aux;
+
+	return OF_is_compatible(faa->fa_node, "marvell,orion-mdio");
+}
+
+static void
+mvmdio_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct mvmdio_softc *sc = (struct mvmdio_softc *) self;
+	struct fdt_attach_args *faa = aux;
+
+	printf("\n");
+
+	sc->sc_iot = faa->fa_iot;
+	if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
+	    faa->fa_reg[0].size, 0, &sc->sc_ioh))
+		panic("%s: cannot map registers", sc->sc_dev.dv_xname);
+
+	pinctrl_byname(faa->fa_node, "default");
+
+	mtx_init(&sc->sc_mtx, IPL_NET);
+
+	mvmdio_sc = sc;
+}
+
+int
+mvmdio_miibus_readreg(struct device *dev, int phy, int reg)
+{
+	struct mvmdio_softc *sc = (struct mvmdio_softc *) dev;
+	uint32_t smi, val;
+	int i;
+
+	mtx_enter(&sc->sc_mtx);
+
+	for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
+		DELAY(1);
+		if (!(MVNETA_READ(sc, 0) & MVNETA_SMI_BUSY))
+			break;
+	}
+	if (i == MVNETA_PHY_TIMEOUT) {
+		printf("%s: SMI busy timeout\n", sc->sc_dev.dv_xname);
+		mtx_leave(&sc->sc_mtx);
+		return -1;
+	}
+
+	smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg)
+	    | MVNETA_SMI_OPCODE_READ;
+	MVNETA_WRITE(sc, 0, smi);
+
+	for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
+		DELAY(1);
+		smi = MVNETA_READ(sc, 0);
+		if (smi & MVNETA_SMI_READVALID)
+			break;
+	}
+
+	mtx_leave(&sc->sc_mtx);
+
+	val = smi & MVNETA_SMI_DATA_MASK;
+
+	return val;
+}
+
+void
+mvmdio_miibus_writereg(struct device *dev, int phy, int reg, int val)
+{
+	struct mvmdio_softc *sc = (struct mvmdio_softc *) dev;
+	uint32_t smi;
+	int i;
+
+	mtx_enter(&sc->sc_mtx);
+
+	for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
+		DELAY(1);
+		if (!(MVNETA_READ(sc, 0) & MVNETA_SMI_BUSY))
+			break;
+	}
+	if (i == MVNETA_PHY_TIMEOUT) {
+		printf("%s: SMI busy timeout\n", sc->sc_dev.dv_xname);
+		mtx_leave(&sc->sc_mtx);
+		return;
+	}
+
+	smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) |
+	    MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK);
+	MVNETA_WRITE(sc, 0, smi);
+
+	for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
+		DELAY(1);
+		if (!(MVNETA_READ(sc, 0) & MVNETA_SMI_BUSY))
+			break;
+	}
+
+	mtx_leave(&sc->sc_mtx);
+
+	if (i == MVNETA_PHY_TIMEOUT)
+		printf("%s: phy write timed out\n", sc->sc_dev.dv_xname);
+}
diff --git a/sys/dev/fdt/mvmdiovar.h b/sys/dev/fdt/mvmdiovar.h
new file mode 100644
index 00000000000..920e007c78e
--- /dev/null
+++ b/sys/dev/fdt/mvmdiovar.h
@@ -0,0 +1,19 @@
+/*	$OpenBSD: mvmdiovar.h,v 1.1 2017/08/25 20:09:34 patrick Exp $	*/
+/*
+ * Copyright (c) 2015 Patrick Wildt <patrick@blueri.se>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int	 mvmdio_miibus_readreg(struct device *, int, int);
+void	 mvmdio_miibus_writereg(struct device *, int, int, int);