remove some unused includes

15 files changed, 0 insertions, 2189 deletions

diff --git a/sys/dev/ic/dc503reg.h b/sys/dev/ic/dc503reg.h
deleted file mode 100644
index 26ed195f50c..00000000000
--- a/sys/dev/ic/dc503reg.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*	$OpenBSD: dc503reg.h,v 1.1 2006/07/23 19:17:23 miod Exp $	*/
-/*	$NetBSD: pmreg.h,v 1.7 2005/12/11 12:18:36 christos Exp $	*/
-
-/*
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * Ralph Campbell.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)pmreg.h	8.1 (Berkeley) 6/10/93
- */
-
-/*
- * Layout of the programmable cursor chip (DC503) registers.
- * All registers are 16 bit wide.
- */
-
-#define	PCC_CMD		0x00	/* cursor command register */
-#define	PCCCMD_TEST	0x8000
-#define	PCCCMD_HSHI	0x4000
-#define	PCCCMD_VBHI	0x2000
-#define	PCCCMD_LODSA	0x1000
-#define	PCCCMD_FORG2	0x0800
-#define	PCCCMD_ENRG2	0x0400
-#define	PCCCMD_FORG1	0x0200
-#define	PCCCMD_ENRG1	0x0100
-#define	PCCCMD_XHWID	0x0080
-#define	PCCCMD_XHCL1	0x0040
-#define	PCCCMD_XHCLP	0x0020
-#define	PCCCMD_XHAIR	0x0010
-#define	PCCCMD_FOPB	0x0008
-#define	PCCCMD_ENPB	0x0004
-#define	PCCCMD_FOPA	0x0002
-#define	PCCCMD_ENPA	0x0001
-
-#define	PCC_XPOS	0x04	/* cursor X position */
-#define	PCC_YPOS	0x08	/* cursor Y position */
-#define	PCC_XMIN_1	0x0c	/* region 1 left edge */
-#define	PCC_XMAX_1	0x10	/* region 1 right edge */
-#define	PCC_YMIN_1	0x14	/* region 1 top edge */
-#define	PCC_YMAX_1	0x18	/* region 1 bottom edge */
-#define	PCC_XMIN_2	0x1c	/* region 2 left edge */
-#define	PCC_XMAX_2	0x20	/* region 2 right edge */
-#define	PCC_YMIN_2	0x24	/* region 2 top edge */
-#define	PCC_YMAX_2	0x28	/* region 2 bottom edge */
-#define	PCC_LOAD	0x2c	/* cursor pattern load */
-
-struct dc503reg {
-	volatile u_int16_t	cmdr;
-	int16_t	pad1;
-	volatile u_int16_t	xpos;
-	int16_t	pad2;
-	volatile u_int16_t	ypos;
-	int16_t	pad3;
-	volatile u_int16_t	xmin1;
-	int16_t	pad4;
-	volatile u_int16_t	xmax1;
-	int16_t	pad5;
-	volatile u_int16_t	ymin1;
-	int16_t	pad6;
-	volatile u_int16_t	ymax1;
-	int16_t	pad7[9];
-	volatile u_int16_t	xmin2;
-	int16_t	pad8;
-	volatile u_int16_t	xmax2;
-	int16_t	pad9;
-	volatile u_int16_t	ymin2;
-	int16_t	pad10;
-	volatile u_int16_t	ymax2;
-	int16_t	pad11;
-	volatile u_int16_t	load;
-};
-
-#define	PCC_CURSOR_SIZE	16
diff --git a/sys/dev/ic/espreg.h b/sys/dev/ic/espreg.h
deleted file mode 100644
index 618a60ea7b4..00000000000
--- a/sys/dev/ic/espreg.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*	$OpenBSD: espreg.h,v 1.2 1996/10/31 01:01:30 niklas Exp $	*/
-
-/*-
- * Copyright (c) 1995  Sean E. Fagin, John M Vinopal.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the author nor the names of contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _ESPREG_H_
-#define	_ESPREG_H_
-
-/*
- * Definitions for Hayes ESP serial cards.
- */
-
-/*
- * CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
- */
-#define	ESP_CMD1	4
-#define	ESP_CMD2	5
-
-/*
- * STAT1 and STAT2 are to get return values and status bytes
- */
-#define	ESP_STATUS1	ESP_CMD1
-#define	ESP_STATUS2	ESP_CMD2
-
-/*
- * Commands.  Commands are given by writing the command value to
- * ESP_CMD1 and then writing or reading some number of bytes from
- * ESP_CMD2 or ESP_STATUS2.
- */
-#define	ESP_GETTEST	0x01	/* self-test command (1 byte + extras) */
-#define	ESP_GETDIPS	0x02	/* get on-board DIP switches (1 byte) */
-#define	ESP_SETFLOWTYPE	0x08	/* set type of flow-control (2 bytes) */
-#define	ESP_SETRXFLOW	0x0a	/* set Rx FIFO flow control levels (4 bytes) */
-#define	ESP_SETMODE	0x10	/* set board mode (1 byte) */
-
-/* Mode bits (ESP_SETMODE). */
-#define	ESP_MODE_FIFO	0x02	/* act like a 16550 (compatibility mode) */
-#define	ESP_MODE_RTS	0x04	/* use RTS hardware flow control */
-#define	ESP_MODE_SCALE	0x80	/* scale FIFO trigger levels */
-
-/* Flow control type bits (ESP_SETFLOWTYPE). */
-#define	ESP_FLOW_RTS	0x04	/* cmd1: local Rx sends RTS flow control */
-#define	ESP_FLOW_CTS	0x10	/* cmd2: local transmitter responds to CTS */
-
-/* Used by ESP_SETRXFLOW. */
-#define	RXHIGHWATER	768
-#define	RXLOWWATER	512
-#define	HIBYTE(w)	(((w) >> 8) & 0xff)
-#define	LOBYTE(w)	((w) & 0xff)
-
-#endif /* !_ESPREG_H_ */
diff --git a/sys/dev/ic/hayespreg.h b/sys/dev/ic/hayespreg.h
deleted file mode 100644
index 118304fda97..00000000000
--- a/sys/dev/ic/hayespreg.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*	$OpenBSD: hayespreg.h,v 1.2 1996/10/31 01:01:30 niklas Exp $	*/
-/*	$NetBSD: hayespreg.h,v 1.1 1996/02/10 20:23:40 christos Exp $	*/
-
-/*-
- * Copyright (c) 1995  Sean E. Fagin, John M Vinopal.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the author nor the names of contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _HAYESPREG_H_
-#define	_HAYESPREG_H_
-
-/*
- * Definitions for Hayes ESP serial cards.
- */
-
-/*
- * CMD1 and CMD2 are the command ports, offsets from <hayesp_iobase>.
- */
-#define	HAYESP_CMD1	4
-#define	HAYESP_CMD2	5
-
-/*
- * STAT1 and STAT2 are to get return values and status bytes
- */
-#define	HAYESP_STATUS1	HAYESP_CMD1
-#define	HAYESP_STATUS2	HAYESP_CMD2
-
-/*
- * Commands.  Commands are given by writing the command value to
- * HAYESP_CMD1 and then writing or reading some number of bytes from
- * HAYESP_CMD2 or HAYESP_STATUS2.
- */
-#define	HAYESP_GETTEST		0x01	/* self-test command (1b+extras) */
-#define	HAYESP_GETDIPS		0x02	/* get on-board DIP switches (1b) */
-#define	HAYESP_SETFLOWTYPE	0x08	/* set type of flow-control (2b) */
-#define	HAYESP_SETRXFLOW	0x0a	/* set Rx FIFO " levels (4b) */
-#define	HAYESP_SETMODE		0x10	/* set board mode (1b) */
-
-/* Mode bits (HAYESP_SETMODE). */
-#define	HAYESP_MODE_FIFO	0x02	/* act like a 16550 (compat mode) */
-#define	HAYESP_MODE_RTS		0x04	/* use RTS hardware flow control */
-#define	HAYESP_MODE_SCALE	0x80	/* scale FIFO trigger levels */
-
-/* Flow control type bits (HAYESP_SETFLOWTYPE). */
-#define	HAYESP_FLOW_RTS	0x04	/* cmd1: local Rx sends RTS flow control */
-#define	HAYESP_FLOW_CTS	0x10	/* cmd2: local transmitter responds to CTS */
-
-/* Used by HAYESP_SETRXFLOW. */
-#define	HAYESP_RXHIWMARK	768
-#define	HAYESP_RXLOWMARK	512
-#define	HAYESP_HIBYTE(w)	(((w) >> 8) & 0xff)
-#define	HAYESP_LOBYTE(w)	((w) & 0xff)
-
-#endif /* !_HAYESPREG_H_ */
diff --git a/sys/dev/ic/i82595reg.h b/sys/dev/ic/i82595reg.h
deleted file mode 100644
index 2898af9bd76..00000000000
--- a/sys/dev/ic/i82595reg.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*	$OpenBSD: i82595reg.h,v 1.3 2003/10/21 18:58:49 jmc Exp $	*/
-/*	$NetBSD: i82595reg.h,v 1.1 1996/05/06 21:36:51 is Exp $	*/
-
-/*
- * Copyright (c) 1996, Ignatios Souvatzis.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Ignatios Souvatzis
- *	for the NetBSD project.
- * 4. The name of the author may not be used to endorse or promote products 
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Intel 82595 Ethernet chip register, bit, and structure definitions.
- *
- * Written by is with reference to Intel's i82595FX data sheet, with some 
- * clarification coming from looking at the Clarkson Packet Driver code for this
- * chip written by Russ Nelson and others;
- *
- * and
- *
- * configuration EEPROM layout. Written with reference to Intels
- * public "LAN595 Hardware and Software Specifications" document.
- */
-
-/* registers */
-
-/* bank0 */
-
-#define COMMAND_REG 0	/* available in any bank */
-
-#define		MC_SETUP_CMD	0x03
-#define		XMT_CMD		0x04
-#define		TDR_CMD		0x05
-#define		DUMP_CMD	0x06
-#define		DIAG_CMD	0x07
-#define		RCV_ENABLE_CMD	0x08
-#define		RCV_DISABLE_CMD	0x0a
-#define		RCV_STOP_CMD	0x0b
-#define		RESET_CMD	0x0e
-#define		TRISTATE_CMD	0x16
-#define		NO_TRISTATE_CMD	0x17
-#define		POWER_DOWN_CMD	0x18
-#define		SLEEP_MODE_CMD	0x19
-#define		NEGOTIATE_CMD	0x1a
-#define		RESUME_XMT_CMD	0x1c
-#define		SEL_RESET_CMD	0x1e
-#define		BANK_SEL(n)	(n<<6)	/* 0, 1, 2 */
-
-#define STATUS_REG 1
-
-#define		RX_STP_INT	0x01
-#define		RX_INT		0x02
-#define		TX_INT		0x04
-#define		EXEC_INT	0x08
-#define		EXEC_STATUS	0x30
-
-#define ID_REG 2
-
-#define		ID_REG_MASK	0x2c
-#define		ID_REG_SIG	0x24
-#define		R_ROBIN_BITS	0xc0
-#define		R_ROBIN_SHIFT	6
-#define		AUTO_ENABLE	0x10
-
-#define INT_MASK_REG 3
-
-#define		RX_STOP_BIT	0x01
-#define		RX_BIT		0x02
-#define		TX_BIT		0x04
-#define		EXEC_BIT	0x08
-#define		ALL_INTS	0x0f
-
-#define RCV_START_LOW 4
-#define RCV_START_HIGH 5
-
-#define RCV_STOP_LOW 6
-#define RCV_STOP_HIGH 7
-
-#define XMT_ADDR_REG 0x0a
-#define HOST_ADDR_REG 0x0c
-#define MEM_PORT_REG 0x0e
-
-/* -------------------- bank1 -------------------- */
-
-#define REG1 1
-
-#define		WORD_WIDTH	0x02
-#define		INT_ENABLE	0x80
-
-#define INT_NO_REG 2
-
-#define RCV_LOWER_LIMIT_REG 8
-#define RCV_UPPER_LIMIT_REG 9
-
-#define XMT_LOWER_LIMIT_REG 10
-#define XMT_UPPER_LIMIT_REG 11
-
-/* bank2 */
-
-/* reg1, apparently */
-
-#define		XMT_CHAIN_INT	0x20	/* interrupt at end of xmt chain */
-#define		XMT_CHAIN_ERRSTOP 0x40	/* int at end of chain even if err */
-#define		RCV_DISCARD_BAD	0x80	/* Throw bad frames away and continue */
-
-#define RECV_MODES_REG 2
-
-#define		PROMISC_MODE	0x01
-#define		NO_RX_CRC	0x04
-#define		NO_ADD_INS	0x10
-#define		MULTI_IA	0x20
-
-#define		MATCH_ID	(NO_ADD_INS | NO_RX_CRC | 0x02)
-#define		MATCH_ALL	(NO_ADD_INS | NO_RX_CRC | 0x01)
-#define		MATCH_BRDCST	(NO_ADD_INS | NO_RX_CRC)
-
-#define MEDIA_SELECT 3
-
-#define		TPE_BIT		0x04
-#define		BNC_BIT		0x20
-#define		TEST_MODE_MASK	0x3f
-
-#define I_ADD(n) (n+4)	/* 0..5 -> 4..9 */
-
-#define EEPROM_REG 10
-
-#define		EEDO 8
-#define		EEDI 4
-#define		EECS 2
-#define		EESK 1
-
-/*
- * EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
- * Software Specifications" document.
- */
-
-#define EEPPW0		0
-#define		EEPP_BusWidth	0x0004
-#define		EEPP_FlashAdrs	0x0038
-#define		EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
-					0xD4000, 0xD8000, 0xDC000}
-#define		EEPP_AutoIO	0x0040
-#define		EEPP_IOMapping	0xfc00
-
-#define EEPPW1		1
-#define		EEPP_Int	0x0007
-#define		EEPP_INTMAP	{3, 5, 9, 10, 11, -1, -1, -1}
-#define		EEPP_RINTMAP	{0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
-				 0xff, 0xff, 0x02, 0x03, 0x04 }
-
-#define		EEPP_LinkInteg	0x0008
-#define		EEPP_PolarCorr	0x0010
-#define		EEPP_AuiTpe	0x0020
-#define		EEPP_Jabber	0x0040
-#define		EEPP_AutoPort	0x0080
-#define		EEPP_SmOut	0x0100
-#define		EEPP_BootFls	0x0200
-#define		EEPP_DramSize	0x1000
-#define		EEPP_AltReady	0x2000
-
-#define EEPPEther2	2
-#define EEPPEther1	3
-#define EEPPEther0	4
-
-#define EEPPEther2a	0x3c
-#define EEPPEther1a	0x3d
-#define EEPPEther0a	0x3e
-
-#define EEPPW5		5
-#define		EEPP_BncTpe	0x0001
-#define		EEPP_RomSlct	0x0006	/* none, NetWare, NDIS, rsrvd. */
-#define		EEPP_NumConn	0x0008	/* 0=2, 1=3 */
-
-#define EEPW6		6
-#define EEPP_BoardRev	0x00FF
-
-#define EEPP_LENGTH 0x40
-#define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
-
-#define I595_XMT_HDRLEN	8
-
-#define CMD_MASK	0x001f
-#define TX_DONE		0x0080
-#define CHAIN		0x8000
-
-#define XMT_STATUS	0x02
-#define XMT_CHAIN	0x04
-#define XMT_COUNT	0x06
-
-#define I595_RCV_HDRLEN	8
-
-#define RCV_DONE	0x0008
-#define RX_OK		0x2000
-#define RX_ERR		0x0d81
-
-
diff --git a/sys/dev/ic/i82810reg.h b/sys/dev/ic/i82810reg.h
deleted file mode 100644
index 24e40362ad9..00000000000
--- a/sys/dev/ic/i82810reg.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*	$OpenBSD: i82810reg.h,v 1.4 2007/05/22 04:14:03 jsg Exp $	*/
-
-/*
- * Copyright (c) 2000 Michael Shalayeff
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* Intel i82810/810E memory and graphics controller */
-
-/* Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) */
-#define	I82810_SMRAM		0x70
-#define	I82810_SMRAM_GMS_DIS	0x00
-#define	I82810_SMRAM_GMS_RSRVD	0x40
-#define	I82810_SMRAM_GMS_512	0x80
-#define	I82810_SMRAM_GMS_1024	0xc0
-#define	I82810_SMRAM_USMM_DIS	0x00
-#define	I82810_SMRAM_USMM_TDHE	0x10
-#define	I82810_SMRAM_USMM_T5HE	0x20
-#define	I82810_SMRAM_USMM_T1HE	0x30
-#define	I82810_SMRAM_LSMM_DIS	0x00
-#define	I82810_SMRAM_LSMM_GSM	0x04
-#define	I82810_SMRAM_LSMM_CRSH	0x08
-#define	I82810_SMRAM_D_LCK	0x02
-#define	I82810_SMRAM_E_SMERR	0x01
-#define	I82810_MISCC		0x72
-#define	I82810_MISCC_GDCWS	0x0001
-#define	I82810_MISCC_P_LCK	0x0008
-#define	I82810_MISCC_WPTHC_NO	0x0000
-#define	I82810_MISCC_WPTHC_625	0x0010
-#define	I82810_MISCC_WPTHC_500	0x0020
-#define	I82810_MISCC_WPTHC_375	0x0030
-#define	I82810_MISCC_RPTHC_NO	0x0000
-#define	I82810_MISCC_RPTHC_625	0x0040
-#define	I82810_MISCC_RPTHC_500	0x0080
-#define	I82810_MISCC_RPTHC_375	0x00c0
-
-/* Graphics Device Registers (Device 1) */
-#define	I82810_GMADR		0x10
-#define	I82810_MMADR		0x14
-
-#define	I82810_DRT		0x3000
-#define	I82810_DRT_DP		0x01
-#define	I82810_DRAMCL		0x3001
-#define	I82810_DRAMCL_RPT	0x01
-#define	I82810_DRAMCL_RT	0x02
-#define	I82810_DRAMCL_CL	0x04
-#define	I82810_DRAMCL_RCO	0x08
-#define	I82810_DRAMCL_PMC	0x10
-#define	I82810_DRAMCH		0x3002
-#define	I82810_DRAMCH_SMS	0x07
-#define	I82810_DRAMCH_DRR	0x18
-#define	I82810_GTT		0x10000
-
-/*
- * Intel i82820 memory and graphics controller
- */
-
-/* Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) */
-#define	I82820_SMRAM		0x9c
-#define	I82820_SMRAM_SHIFT	8
-#define	I82820_SMRAM_G_SMRAME	(1 << 3)
-#define	I82820_SMRAM_D_LCK	(1 << 4)
-#define	I82820_SMRAM_D_CLS	(1 << 5)
-#define	I82820_SMRAM_D_OPEN	(1 << 6)
diff --git a/sys/dev/ic/ibm525reg.h b/sys/dev/ic/ibm525reg.h
deleted file mode 100644
index fca2fff436a..00000000000
--- a/sys/dev/ic/ibm525reg.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*	$OpenBSD: ibm525reg.h,v 1.2 2010/08/02 20:55:49 kettenis Exp $	*/
-/*
- * Copyright (c) 2005, Miodrag Vallat.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * IBM RGB525 Ramdac registers
- */
-
-#define	IBM525_REVISION		0x00
-#define	IBM525_ID		0x01
-
-/* Miscellaneous clock control */
-#define	IBM525_MISC_CLOCK	0x02
-#define	MC_B24P_PLL		0x00
-#define	MC_B24P_SCLK		0x20
-#define	MC_DDOT_DIV_1		0x00	/* (VRAM size / 1) bpp */
-#define	MC_DDOT_DIV_2		0x02	/* (VRAM size / 2) bpp */
-#define	MC_DDOT_DIV_4		0x04	/* (VRAM size / 4) bpp */
-#define	MC_DDOT_DIV_8		0x06	/* (VRAM size / 8) bpp */
-#define	MC_DDOT_DIV_16		0x08	/* (VRAM size / 16) bpp */
-#define	MC_DDOT_DIV_MASK	0x0e
-#define	MC_PLL_ENABLE		0x01
-
-/* Sync control */
-#define	IBM525_SYNC		0x03
-#define	S_CSYN_INVERT		0x40	/* Composite sync invert */
-#define	S_VSYN_INVERT		0x20	/* Vertical sync invert (positive) */
-#define	S_HSYN_INVERT		0x10	/* Horizontal sync invert (positive) */
-#define	S_VSYN_NORMAL		0x00
-#define	S_VSYN_HIGH		0x04
-#define	S_VSYN_LOW		0x08
-#define	S_VSYN_DISABLE		0x0c
-#define	S_VSYN_MASK		0x0c
-#define	S_HSYN_NORMAL		0x00
-#define	S_HSYN_HIGH		0x01
-#define	S_HSYN_LOW		0x02
-#define	S_HSYN_DISABLE		0x03
-#define	S_HSYN_MASK		0x03
-
-/* Horizontal sync position */
-#define	IBM525_HSYNC_POS	0x04
-
-/* Power management */
-#define	IBM525_POWER		0x05
-#define	P_SCLK_DISABLE		0x10
-#define	P_DDOT_DISABLE		0x08
-#define	P_SYNC_DISABLE		0x04
-#define	P_ICLK_DISABLE		0x02	/* Disable internal DAC clock */
-#define	P_DAC_PWR_DISABLE	0x01	/* Disable internal DAC power */
-
-/* DAC operation */
-#define	IBM525_DAC_OP		0x06
-#define	DO_SOG			0x08	/* Sync on Green */
-#define	DO_FAST_SLEW		0x02	/* fast (>= 20 MHz) pixel clock */
-#define	DO_BLANK_BR		0x04	/* blank blue and red channels */
-#define	DO_PEDESTAL		0x01
-
-/* Palette control */
-#define	IBM525_PALETTE		0x07
-
-/* System clock control */
-#define	IBM525_SYSCLK		0x08
-#define	SC_ENABLE		0x01
-
-/* Pixel format */
-#define	IBM525_PIXEL		0x0a
-#define	PIX_4BPP		0x02
-#define	PIX_8BPP		0x03
-#define	PIX_16BPP		0x04
-#define	PIX_24BPP		0x05
-#define	PIX_32BPP		0x06
-
-/* 8bpp pixel format */
-#define	IBM525_PF8		0x0b
-#define	PF8_INDIRECT		0x00
-#define	PF8_DIRECT		0x01
-
-/* 16bpp pixel format */
-#define	IBM525_PF16		0x0c
-#define	PF16_INDIRECT		0x00
-#define	PF16_DIRECT		0xc0
-#define	PF16_LINEAR		0x04
-#define	PF16_555		0x00	/* 5:5:5 15bpp */
-#define	PF16_565		0x02	/* 5:6:5 15bpp */
-
-/* 24bpp pixel format */
-#define	IBM525_PF24		0x0d
-#define	PF24_INDIRECT		0x00
-#define	PF24_DIRECT		0x01
-
-/* 32bpp pixel format */
-#define	IBM525_PF32		0x0e
-#define	PF32_INDIRECT		0x00
-#define	PF32_DIRECT		0x03
-#define	PF32_BYPASS		0x00
-#define	PF32_LOOKUP		0x04
-
-/* Pixel PLL control #1 */
-#define	IBM525_PLL1		0x10
-#define	P1_CLK_REF		0x00
-#define	P1_CLK_EXT		0x10
-#define	P1_SRC_EXT_F		0x00	/* Use F registers for timing */
-#define	P1_SRC_EXT_MN		0x01	/* Use M:N registers for timing */
-#define	P1_SRC_DIRECT_F		0x02	/* Use F registers for timing */
-#define	P1_SRC_DIRECT_MN	0x03	/* Use M:N registers for timing */
-
-/* Pixel PLL control #2 */
-#define	IBM525_PLL2		0x11
-
-/* Fixed PLL reference */
-#define	IBM525_PLL_FIXED_REF	0x14
-
-/* PLL reference divider */
-#define	IBM525_PLL_REF_DIV	0x15
-
-/* PLL VCO divider */
-#define	IBM525_PLL_VCO_DIV	0x16
-
-/* N0-N15 */
-#define	IBM525_F(n)		(0x20 + (n))
-
-/* Miscellaneous control #1 */
-#define	IBM525_MISC1		0x70
-#define	M1_VRAM_32		0x00
-#define	M1_VRAM_64		0x01
-#define	M1_VRAM_SIZE_MASK	0x01
-#define	M1_SENSE_DISABLE	0x10
-
-/* Miscellaneous control #2 */
-#define	IBM525_MISC2		0x71
-#define	M2_PCLK_LOCAL		0x00
-#define	M2_PCLK_PLL		0x40
-#define	M2_PCLK_EXT		0x80
-#define	M2_PCLK_MASK		0xc0
-#define	M2_PALETTE_6		0x00	/* VGA compatible 6bit palette */
-#define	M2_PALETTE_8		0x04	/* 8bit palette */
-#define	M2_PALETTE_MASK		0x04
-#define	M2_MODE_VRAM		0x01
-#define	M2_MODE_VGA		0x00
-#define	M2_MODE_MASK		0x01
-
-/* Miscellaneous control #3 */
-#define	IBM525_MISC3		0x72
-#define	M3_SWAP_BR		0x80	/* swap blue and red */
-#define	M3_SWAP_WORDS		0x10
-#define	M3_SWAP_NIBBLES		0x02
-
-/* Miscellaneous control #4 */
-#define	IBM525_MISC4		0x73
-#define	M4_INVERT_DCLK		0x10
-#define	M4_FAST			0x20	/* Fast (>= 50 MHz) pixel clock */
-
-/*
- * Pixel clock encoding
- */
-#define	MHZ_TO_PLL(m) \
-	((m) < 32 ? 0x00 | (4 * (m) - 65) : \
-	   (m) < 64 ? 0x40 | (2 * (m) - 65) : \
-	     (m) < 128 ? 0x80 | ((m) - 65) : \
-	       0xc0 | ((m) / 2 - 65))
diff --git a/sys/dev/ic/intersil7170.h b/sys/dev/ic/intersil7170.h
deleted file mode 100644
index 065ee6f87f1..00000000000
--- a/sys/dev/ic/intersil7170.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*	$OpenBSD: intersil7170.h,v 1.2 2008/06/26 05:42:15 ray Exp $	*/
-/*	$NetBSD: intersil7170.h,v 1.1 1997/05/02 06:15:28 jeremy Exp $	*/
-
-/*-
- * Copyright (c) 1996 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Adam Glass.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef	_INTERSIL7170_H
-#define	_INTERSIL7170_H
-
-/*
- * Driver support for the intersil7170 used in sun[34]s to provide
- * real time clock and time-of-day support.
- *
- * Derived from: datasheet "ICM7170 a uP-Compatible Real-Time Clock"
- *                          document #301680-005, Dec 85
- */
-
-struct intersil_dt {		       /* from p. 7 of 10 */
-    u_int8_t dt_csec;
-    u_int8_t dt_hour;
-    u_int8_t dt_min;
-    u_int8_t dt_sec;
-    u_int8_t dt_month;
-    u_int8_t dt_day;
-    u_int8_t dt_year;
-    u_int8_t dt_dow;
-};
-
-struct intersil7170 {
-    struct intersil_dt counters;
-    struct intersil_dt clk_ram;	/* should be ok as both are word aligned */
-    u_int8_t clk_intr_reg;
-    u_int8_t clk_cmd_reg;
-};
-
-/*  bit assignments for command register, p. 6 of 10, write-only */
-#define INTERSIL_CMD_FREQ_32K    0x0
-#define INTERSIL_CMD_FREQ_1M     0x1
-#define INTERSIL_CMD_FREQ_2M     0x2
-#define INTERSIL_CMD_FREQ_4M     0x3
-
-#define INTERSIL_CMD_12HR_MODE   0x0
-#define INTERSIL_CMD_24HR_MODE   0x4
-
-#define INTERSIL_CMD_STOP        0x0
-#define INTERSIL_CMD_RUN         0x8
-
-#define INTERSIL_CMD_IDISABLE   0x0
-#define INTERSIL_CMD_IENABLE   0x10
-
-#define INTERSIL_CMD_TEST_MODE      0x20
-#define INTERSIL_CMD_NORMAL_MODE    0x0
-
-/* bit assignments for interrupt register r/w, p 7 of 10*/
-
-#define INTERSIL_INTER_ALARM       0x1 /* r/w */
-#define INTERSIL_INTER_CSECONDS    0x2 /* r/w */
-#define INTERSIL_INTER_DSECONDS    0x4 /* r/w */
-#define INTERSIL_INTER_SECONDS     0x8 /* r/w */
-#define INTERSIL_INTER_MINUTES    0x10 /* r/w */
-#define INTERSIL_INTER_HOURS      0x20 /* r/w */
-#define INTERSIL_INTER_DAYS       0x40 /* r/w */
-#define INTERSIL_INTER_PENDING    0x80 /* read-only */
-
-#define INTERSIL_INTER_BITS "\20\10PENDING\7DAYS\6HRS\5MIN\4SCDS\3DSEC\2CSEC\1ALARM"
-
-#endif	/* _INTERSIL7170_H */
diff --git a/sys/dev/isa/madreg.h b/sys/dev/isa/madreg.h
deleted file mode 100644
index 5e6e114aaec..00000000000
--- a/sys/dev/isa/madreg.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*	$OpenBSD: madreg.h,v 1.1 1998/04/26 21:02:37 provos Exp $	*/
-/*	$NetBSD: madreg.h,v 1.4 1998/01/19 22:18:27 augustss Exp $	*/
-/*
- * Copyright (c) 1996 Lennart Augustsson
- * Copyright (c) 1995 Hannu Savolainen
- * Copyright (c) 1991-1993 Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the Computer Systems
- *	Engineering Group at Lawrence Berkeley Laboratory.
- * 4. Neither the name of the University nor of the Laboratory may be used
- *    to endorse or promote products derived from this software without
- *    specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-
-/*
- * Variations of the suppored chips.
- */
-
-#define MAD_NONE	0
-#define MAD_82C928	1		/* OPTi 82C928     MAD16 */
-#define MAD_OTI601D	2		/* OAK OTI-601D    Mozart */
-#define MAD_82C929	3		/* OPTi 82C929     MAD16 Pro */
-#define MAD_82C931	4		/* OPTi 82C831     */
-
-/*
- *    Registers
- *
- *      The MAD16 occupies I/O ports 0xf8d to 0xf93 (fixed locations).
- *      All ports are inactive by default. They can be activated by
- *      writing 0xE2 or 0xE3 to the password register. The password is valid
- *      only until the next I/O read or write.
- */
-
-#define MAD_BASE	0xf8d
-#define MAD_NPORT	7
-
-#define MC1_PORT	0	/* SB address, CDROM interface type, joystick */
-#define MC2_PORT	1	/* CDROM address, IRQ, DMA, plus OPL4 bit */
-#define MC3_PORT	2
-#define MC_PASSWD_REG	MC3_PORT
-#define MC4_PORT	3
-#define MC5_PORT	4
-#define MC6_PORT	5
-#define MC7_PORT	6
-
-#define MC1_NOCD	0x00
-#define MC1_JOYDISABLE	0x01
-#define MC1_SONY	0x02
-#define MC1_MITSUMI	0x04
-#define MC1_PANASONIC	0x06
-#define MC1_SECIDE	0x08
-#define MC1_PRIMIDE	0x0a
-
-#define MC2_CDDISABLE	0x03
-#define MC2_OPL4	0x20
-
-/* Possible WSS emulation ports */
-#define M_WSS_PORT0 0x530
-#define M_WSS_PORT1 0xe80
-#define M_WSS_PORT2 0xf40
-#define M_WSS_PORT3 0x604
-#define M_WSS_NPORTS 4
-
-/* Port 1 */
-#define M_WSS_PORT_SELECT(i) (0x80 | ((i) << 4))
-
-#define M_PASSWD_928	0xe2
-#define M_PASSWD_929	0xe3
-#define M_PASSWD_931	0xe4
-
-/* Regions of I/O space that the MAD occupies besides
-   WSS emulation and MAD_BASE.  Talk about waste. */
-#define MAD_REG1 0x220
-#define MAD_LEN1 16
-#define MAD_REG2 0x380
-#define MAD_LEN2 2
-#define MAD_REG3 0x388
-#define MAD_LEN3 4
diff --git a/sys/dev/isa/rtreg.h b/sys/dev/isa/rtreg.h
deleted file mode 100644
index 3171d1e2406..00000000000
--- a/sys/dev/isa/rtreg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* $OpenBSD: rtreg.h,v 1.1 2002/08/28 21:20:48 mickey Exp $ */
-
-/*
- * Copyright (c) 2001, 2002 Maxim Tsyplakov <tm@oganer.net>,
- *			    Vladimir Popov <jumbo@narod.ru>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* AIMS Lab Radiotrack FM Radio Card device driver */
-
-#ifndef _RTREG_H_
-#define _RTREG_H_
-
-#include <dev/isa/rtvar.h>
-
-#define RF_25K			25
-#define RF_50K			50
-#define RF_100K			100
-
-#define MAX_VOL			5	/* XXX Find real value */
-#define VOLUME_RATIO(x)		(255 * x / MAX_VOL)
-
-#define RT_BASE_VALID(x)	((x == 0x20C) || (x == 0x30C))
-
-#define CARD_RADIOTRACK		0
-#define CARD_SF16FMI		1
-#define CARD_UNKNOWN		-1
-
-#define RTRACK_CAPABILITIES	RADIO_CAPS_DETECT_STEREO | 		\
-				RADIO_CAPS_DETECT_SIGNAL | 		\
-				RADIO_CAPS_SET_MONO | 			\
-				RADIO_CAPS_REFERENCE_FREQ
-
-#define SF16FMI_CAPABILITIES	RADIO_CAPS_REFERENCE_FREQ
-
-#define	RT_WREN_ON		(1 << 0)
-#define	RT_WREN_OFF		(0 << 0)
-#define RT_CLCK_ON		(1 << 1)
-#define RT_CLCK_OFF		(0 << 1)
-#define RT_DATA_ON		(1 << 2)
-#define RT_DATA_OFF		(0 << 2)
-#define RT_CARD_ON		(1 << 3)
-#define RT_CARD_OFF		(0 << 3)
-#define RT_SIGNAL_METER		(1 << 4)
-#define RT_VOLUME_DOWN		(1 << 6)
-#define RT_VOLUME_UP		(2 << 6)
-#define RT_VOLUME_STEADY	(3 << 6)
-
-#define RT_SIGNAL_METER_DELAY	150000
-#define RT_VOLUME_DELAY		100000
-
-#endif /* _RTREG_H_ */
diff --git a/sys/dev/isa/rtvar.h b/sys/dev/isa/rtvar.h
deleted file mode 100644
index b481caa3454..00000000000
--- a/sys/dev/isa/rtvar.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* $OpenBSD: rtvar.h,v 1.1 2002/08/28 21:20:48 mickey Exp $ */
-
-/*
- * Copyright (c) 2001, 2002 Maxim Tsyplakov <tm@oganer.net>,
- *			    Vladimir Popov <jumbo@narod.ru>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* AIMS Lab Radiotrack FM Radio Card device driver */
-
-/*
- * Sanyo LM7000 Direct PLL Frequency Synthesizer
- */
-
-#ifndef _RTVAR_H_
-#define _RTVAR_H_
-
-struct rt_softc {
-	struct device	sc_dev;
-
-	int		sc_ct;	/* card type */
-	int		sc_mute;
-	u_int8_t	sc_vol;
-	u_int32_t	sc_freq;
-	u_int32_t	sc_rf;
-	u_int32_t	sc_stereo;
-
-	struct lm700x_t	lm;
-};
-
-void	rtattach(struct rt_softc *);
-
-#endif /* _RTVAR_H_ */
diff --git a/sys/dev/microcode/ises/ises_fw.h b/sys/dev/microcode/ises/ises_fw.h
deleted file mode 100644
index 875a6fae37f..00000000000
--- a/sys/dev/microcode/ises/ises_fw.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*	$OpenBSD: ises_fw.h,v 1.1 2001/07/02 09:18:14 ho Exp $	*/
-
-/* 
- * ------------------------------------------
- * PCC-ISES Basic Functionality firmware v2.0 
- * ------------------------------------------
- */
-
-/* 
- * To regenerate this file from the *.pcc or *.emb file supplied by the
- * vendor, do the following:
- *  - In the *.pcc or *.emb file, pick out the BCMD_IDPLEN and BCMD_IPDCRC
- *    values and put them in ISES_BF_IDPLEN / ISES_BF_IDPCRC respectively.
- *  - Remove everything from the file except the "firmware data", and feed
- *    the result through this filter:
- *       sed -e 's/$//' -e 's/ /, 0x/g' -e 's/./0x&/' -e 's/.$/,/' | \
- *           xargs -n4 | sed 's/./<TAB>&/'
- */
-
-/*
- * Copyright (C) 1999, 2000 Pijnenburg Custom Chips B.V.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted provided
- * that the following conditions are met:
- * 1. Redistribution of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistribution in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define ISES_BF_IDPLEN		0x00000403	/* Total length, 32bit words */
-#define ISES_BF_IDPCRC		0x59DE7DEF	/* Firmware CRC */
-
-static const u_int32_t ises_bf_fw[] = {
-	0xEA000006, 0xE1A00000, 0xE1A00000, 0xE1A00000,
-	0xE1A00000, 0xE1A00000, 0xEA000013, 0xEA000026,
-	0xE59FD0C4, 0xE3A000D2, 0xE121F000, 0xE59FD0BC,
-	0xE3A000D1, 0xE121F000, 0xE59FD0B0, 0xE3A000D3,
-	0xE121F000, 0xEB00029B, 0xEAFFFFFE, 0xE10F1000,
-	0xE1811000, 0xE121F001, 0xE12FFF1E, 0xE10F1000,
-	0xE1C11000, 0xE121F001, 0xE12FFF1E, 0xE92D0003,
-	0xE59F107C, 0xE5910004, 0xE5810000, 0xE3100902,
-	0x0A00000B, 0xE59F106C, 0xE5910000, 0xE3500000,
-	0x1A000003, 0xE59F1060, 0xE3A00001, 0xE5810000,
-	0xEA000003, 0xE3500001, 0x1A000001, 0xE59F1038,
-	0xE5810000, 0xE8BD0003, 0xE25EF004, 0xE25EF004,
-	0xE3A000D3, 0xE121F000, 0xE59FE030, 0xE3A00000,
-	0xE3A01032, 0xE48E0004, 0xE2511001, 0x1AFFFFFC,
-	0xE91E3FFE, 0xE3A0E000, 0xE3A0F000, 0x000017B4,
-	0x000017DC, 0xFFFFEA00, 0xFFFFE60C, 0xFFFFF000,
-	0x00001714, 0xE3A01001, 0xE3A00AFE, 0xE2400601,
-	0xE5A01624, 0xE1A0F00E, 0xE3A00AFE, 0xE2400601,
-	0xE5901620, 0xE3510000, 0x0AFFFFFC, 0xE5900610,
-	0xE1A0F00E, 0xE3A02000, 0xE3510000, 0x91A0F00E,
-	0xE3A03AFE, 0xE2433601, 0xE593C620, 0xE35C0000,
-	0x0AFFFFFC, 0xE593C610, 0xE2822001, 0xE1520001,
-	0xE480C004, 0x3AFFFFF7, 0xE1A0F00E, 0xE3A01000,
-	0xE3A00AFE, 0xE2400601, 0xE5A01618, 0xE1A0F00E,
-	0xE3A01002, 0xE3A00AFE, 0xE2400601, 0xE5A01624,
-	0xE1A0F00E, 0xE3A01AFE, 0xE2411601, 0xE591261C,
-	0xE3520000, 0x1A000006, 0xE3A02506, 0xE5812600,
-	0xE591261C, 0xE3520000, 0x0AFFFFFC, 0xE3A02401,
-	0xE5812600, 0xE5A10610, 0xE1A0F00E, 0xE3A03000,
-	0xE3510000, 0x91A0F00E, 0xE92D4010, 0xE3A0E506,
-	0xE3A0C401, 0xE3A02AFE, 0xE2422601, 0xE592461C,
-	0xE3540000, 0x1A000004, 0xE582E600, 0xE592461C,
-	0xE3540000, 0x0AFFFFFC, 0xE582C600, 0xE4904004,
-	0xE5824610, 0xE2833001, 0xE1530001, 0x3AFFFFF2,
-	0xE8BD8010, 0xE3A01000, 0xE3A00AFE, 0xE2400601,
-	0xE5A01614, 0xE3A00CE6, 0xE2400801, 0xE5901000,
-	0xE3811302, 0xE5801000, 0xE5901000, 0xE3C11302,
-	0xE5801000, 0xE1A0F00E, 0xE59F2038, 0xE59F0038,
-	0xE5901000, 0xE0821181, 0xE5D11006, 0xE20120F0,
-	0xE3A03BC2, 0xE2433701, 0xE0832402, 0xE5802008,
-	0xE2822004, 0xE580200C, 0xE2432B02, 0xE0821401,
-	0xE5A01010, 0xE1A0F00E, 0x00000E00, 0x00001000,
-	0xE92D4000, 0xEBFFFFB0, 0xE3A01002, 0xE59F0028,
-	0xE5801000, 0xE3A01AFE, 0xE2411601, 0xE5912204,
-	0xE5802004, 0xE5911208, 0xE5801008, 0xE3A01003,
-	0xEB000264, 0xE3A00000, 0xE8BD8000, 0x00001014,
-	0xE92D4000, 0xEBFFFFDB, 0xEBFFFF9F, 0xE51F005C,
-	0xE51F205C, 0xE5921000, 0xE0800181, 0xE5D01007,
-	0xE3510011, 0x1A000004, 0xE51F0074, 0xE5900008,
-	0xE5903000, 0xE3130008, 0x0AFFFFFC, 0xE5B2000C,
-	0xE5801000, 0xE3A00000, 0xEB000247, 0xE3A00000,
-	0xE8BD8000, 0xE92D4000, 0xEBFFFFC6, 0xEBFFFF8A,
-	0xE51F10AC, 0xE5910008, 0xE5902000, 0xE3120008,
-	0x0AFFFFFC, 0xE5900000, 0xE3100002, 0x0A000002,
-	0xE3A00003, 0xEB000238, 0xEA000002, 0xE5B10010,
-	0xE3A01040, 0xEB00023B, 0xE3A00000, 0xE8BD8000,
-	0xE92D4010, 0xEBFFFFB3, 0xE51F40F4, 0xE5940008,
-	0xE5901000, 0xE3110008, 0x0AFFFFFC, 0xE5900000,
-	0xE3100002, 0x0A000005, 0xE5B41004, 0xE51F00D8,
-	0xEBFFFF5F, 0xEBFFFF6C, 0xE3A00003, 0xEA00000B,
-	0xE5940010, 0xE5941004, 0xEBFFFF59, 0xEBFFFF66,
-	0xE51F0140, 0xE5941000, 0xE0800181, 0xE5D02007,
-	0xE5B41004, 0xE594000C, 0xEB00024E, 0xE3A00000,
-	0xEB000215, 0xE3A00000, 0xE8BD8010, 0xE92D4010,
-	0xEBFFFF94, 0xEBFFFF58, 0xE51F0174, 0xE5901008,
-	0xE5912000, 0xE3120008, 0x0AFFFFFC, 0xE5911000,
-	0xE3110002, 0xE3A04000, 0x13A00003, 0x1A00000F,
-	0xE51F11A0, 0xE5902000, 0xE0812182, 0xE5D22007,
-	0xE3520034, 0x1A000003, 0xE5902010, 0xE5224088,
-	0xE5902010, 0xE5224084, 0xE5902000, 0xE0811182,
-	0xE5D11007, 0xE590000C, 0xE5801000, 0xE3A00000,
-	0xEB0001F5, 0xE1A00004, 0xE8BD8010, 0xE92D4010,
-	0xEBFFFF39, 0xE3A04000, 0xE3A00AFE, 0xE2400601,
-	0xE5A04400, 0xE3A00000, 0xEB0001EB, 0xE1A00004,
-	0xE8BD8010, 0xE92D4010, 0xE51F01D4, 0xE1A04000,
-	0xE3A01002, 0xEBFFFF1E, 0xEBFFFF2B, 0xE3A00AFE,
-	0xE2400601, 0xE5901474, 0xE3110002, 0x1A00000F,
-	0xE5901424, 0xE3110402, 0x13A00005, 0x1A00000E,
-	0xE3A01003, 0xE5801470, 0xE5901474, 0xE3110020,
-	0x0AFFFFFC, 0xE5941000, 0xE5801478, 0xE5B41004,
-	0xE5801478, 0xE5900474, 0xE3100002, 0x0A000001,
-	0xE3A00004, 0xEA000000, 0xE3A00000, 0xEB0001CA,
-	0xE3A00000, 0xE8BD8010, 0xE92D4000, 0xEBFFFF0E,
-	0xE3A00AFE, 0xE2400601, 0xE5901474, 0xE3110002,
-	0xE51F126C, 0x1A00000D, 0xE5902424, 0xE3120402,
-	0x13A00005, 0x1A00000C, 0xE5902474, 0xE3120040,
-	0x0AFFFFFC, 0xE5902478, 0xE5812000, 0xE5902478,
-	0xE5812004, 0xE5900474, 0xE3100002, 0x0A000001,
-	0xE3A00004, 0xEA000000, 0xE3A00000, 0xE3500000,
-	0x1A000003, 0xE1A00001, 0xE3A01002, 0xEB0001B1,
-	0xEA000000, 0xEB0001A8, 0xE3A00000, 0xE8BD8000,
-	0xE92D40F0, 0xE51F6320, 0xE5961004, 0xE51F02E8,
-	0xE1A04000, 0xEBFFFEDA, 0xEBFFFEE7, 0xE3A05AFE,
-	0xE2455601, 0xE3A07000, 0xE5960000, 0xE3500023,
-	0x1A000004, 0xE5941000, 0xE3110004, 0x13A00004,
-	0x15A50470, 0x1A000018, 0xE3500023, 0x13500031,
-	0x0A000002, 0xE5951474, 0xE3110001, 0x1AFFFFFC,
-	0xE3500025, 0x1A000003, 0xE5940000, 0xE3C0033F,
-	0xE5840000, 0xE5857470, 0xE5960004, 0xE1A02100,
-	0xE51F03A0, 0xE5961000, 0xE0800181, 0xE5D00006,
-	0xE2400B07, 0xE1A01004, 0xEB0001D0, 0xE5B50474,
-	0xE3100002, 0x13A00004, 0x1A000000, 0xE3A00000,
-	0xEB000179, 0xE1A00007, 0xE8BD80F0, 0xE92D40F0,
-	0xEBFFFEBD, 0xE3A06AFE, 0xE2466601, 0xE5960474,
-	0xE3100002, 0xE51F73B0, 0xE51F43F4, 0x15940000,
-	0x13500020, 0x1A000014, 0xE5940000, 0xE350002E,
-	0x13500030, 0x13500034, 0x1A000002, 0xE5961474,
-	0xE3110001, 0x1AFFFFFC, 0xE51F1428, 0xE0810180,
-	0xE5D05007, 0xE1A02105, 0xE5D00006, 0xE2401B07,
-	0xE1A00007, 0xEB0001AD, 0xE5B60474, 0xE3100002,
-	0x15940000, 0x13500020, 0x0A000001, 0xE3A00004,
-	0xEA000000, 0xE3A00000, 0xE3500000, 0x1A000003,
-	0xE1A01005, 0xE1A00007, 0xEB000156, 0xEA000000,
-	0xEB00014D, 0xE3A00000, 0xE8BD80F0, 0xE92D41F0,
-	0xE3A04000, 0xE3A00003, 0xE3A08AFE, 0xE2488601,
-	0xE5880470, 0xE5980474, 0xE3100002, 0xE51F54A8,
-	0x13A04004, 0x1A000006, 0xE5950004, 0xE3100001,
-	0x13A04006, 0x1A000002, 0xE5980424, 0xE3100402,
-	0x13A04005, 0xE51F7490, 0xE3540000, 0x0A000004,
-	0xE1A00007, 0xE5951004, 0xEBFFFE6D, 0xEBFFFE7A,
-	0xEA00001D, 0xE3A06000, 0xE5950004, 0xE3500000,
-	0xDA000015, 0xE5980474, 0xE3100020, 0x0AFFFFFC,
-	0xEBFFFE5C, 0xE5880478, 0xEBFFFE5A, 0xE5880478,
-	0xE5980474, 0xE3100004, 0x1A000007, 0xE5980474,
-	0xE3100040, 0x0AFFFFFC, 0xE5980478, 0xE7870106,
-	0xE5980478, 0xE0871106, 0xE5A10004, 0xE2866002,
-	0xE5950004, 0xE1560000, 0xBAFFFFE9, 0xEBFFFE5E,
-	0xE5980474, 0xE3100002, 0x13A04004, 0xE3540000,
-	0x05B80474, 0x03100004, 0x1A000003, 0xE1A00007,
-	0xE5B51004, 0xEB000113, 0xEA000001, 0xE1A00004,
-	0xEB000109, 0xE3A00000, 0xE8BD81F0, 0xE92D4010,
-	0xEBFFFE4D, 0xE3A00AFE, 0xE2400601, 0xE5901474,
-	0xE3110002, 0xE3A04000, 0x1A000013, 0xE5901424,
-	0xE3110402, 0x0A000003, 0xE5901474, 0xE3110C02,
-	0x0AFFFFFC, 0xEA000002, 0xE5901474, 0xE3110020,
-	0x0AFFFFFC, 0xE5901470, 0xE3C11001, 0xE5801470,
-	0xE5901474, 0xE3110001, 0x1AFFFFFC, 0xE5804470,
-	0xE5900474, 0xE3100002, 0x0A000001, 0xE3A00004,
-	0xEA000000, 0xE3A00000, 0xEB0000E7, 0xE1A00004,
-	0xE8BD8010, 0xE92D4070, 0xE3A00AFE, 0xE2400601,
-	0xE5901474, 0xE3110002, 0xE51F55F4, 0xE3A06000,
-	0x0A000005, 0xE3A04004, 0xE1A00005, 0xE3A01012,
-	0xEBFFFE13, 0xEBFFFE20, 0xEA000027, 0xE5901424,
-	0xE3110402, 0x0A000003, 0xE5901474, 0xE3110C02,
-	0x0AFFFFFC, 0xEA000002, 0xE5901474, 0xE3110020,
-	0x0AFFFFFC, 0xE5901470, 0xE3C11001, 0xE5801470,
-	0xE5901474, 0xE3110001, 0x1AFFFFFC, 0xE1A04000,
-	0xE5806470, 0xE1A00005, 0xE3A02048, 0xE3A0100C,
-	0xE2411B07, 0xEB000111, 0xE3A01006, 0xE3A0000C,
-	0xE2400B07, 0xEBFFFDF6, 0xEBFFFDEE, 0xE3C0033F,
-	0xE5840424, 0xE3A0100B, 0xE3A00028, 0xE2400B07,
-	0xEBFFFDEF, 0xEBFFFDFC, 0xE3A00003, 0xE5840470,
-	0xE5B40474, 0xE2104002, 0x13A04004, 0xE3540000,
-	0x1A000003, 0xE1A00005, 0xE3A01012, 0xEB0000B1,
-	0xEA000001, 0xE1A00004, 0xEB0000A7, 0xE1A00006,
-	0xE8BD8070, 0xE92D4000, 0xEBFFFDEB, 0xE51F172C,
-	0xE51F072C, 0xE5900000, 0xE0810180, 0xE5D00007,
-	0xE3A01AFE, 0xE2411601, 0xE5A10C00, 0xE3A00000,
-	0xEB000099, 0xE3A00000, 0xE8BD8000, 0xE92D4000,
-	0xEBFFFDC8, 0xE3A01AFE, 0xE2411601, 0xE5A10C04,
-	0xEBFFFDD9, 0xE3A00000, 0xEB00008F, 0xE3A00000,
-	0xE8BD8000, 0xE92D41F0, 0xEBFFFDBE, 0xE1A04000,
-	0xEBFFFDD1, 0xE3A06000, 0xE35400FF, 0x9A000002,
-	0xE3A00007, 0xEB000084, 0xEA00001C, 0xE3A00000,
-	0xE51F376C, 0xE3540000, 0x9A000015, 0xE3A07064,
-	0xE3A0C080, 0xE3A02AFE, 0xE2422601, 0xE3A0E001,
-	0xE3A01000, 0xE5827800, 0xE582C808, 0xE5928A00,
-	0xE3180001, 0x0AFFFFFC, 0xE582EA00, 0xE5928C04,
-	0xE20880FF, 0xE0885405, 0xE2811001, 0xE3510004,
-	0x3AFFFFF3, 0xE7835100, 0xE2800001, 0xE1500004,
-	0x3AFFFFEE, 0xE1A01004, 0xE1A00003, 0xEB00006D,
-	0xE1A00006, 0xE8BD81F0, 0xE92D47F0, 0xEB0000A1,
-	0xE3A09004, 0xE3A08AFE, 0xE2488601, 0xE3A07010,
-	0xE1A06088, 0xE2485A01, 0xE3500000, 0x0A000001,
-	0xEB000084, 0xEA000015, 0xEB000082, 0xE5889470,
-	0xE3A0A000, 0xE59F4040, 0xEBFFFD81, 0xEBFFFD9F,
-	0xE3A00001, 0xEB000014, 0xEB000019, 0xE3500002,
-	0x0A00000A, 0xE5867804, 0xE5857804, 0xE5889470,
-	0xE3A00002, 0xEB00000C, 0xE584A000, 0xE5940000,
-	0xE3500000, 0x0AFFFFFC, 0xEAFFFFEE, 0x000017B4,
-	0xE5A67804, 0xE5A57804, 0xE5A89470, 0xE3A00003,
-	0xEB000001, 0xEAFFFFFF, 0xEAFFFFFE, 0xE1A00C00,
-	0xE3A01AFE, 0xE2411601, 0xE5A10600, 0xE1A0F00E,
-	0xE1A0F00E, 0xE92D43F0, 0xE3A07001, 0xE3A09AFE,
-	0xE2499601, 0xE3A080FF, 0xE59F6030, 0xE59F5030,
-	0xE59F4030, 0xE5990618, 0xE3500C01, 0x0A000005,
-	0xE5990618, 0xE3500000, 0x9A000007, 0xE5990620,
-	0xE3500000, 0x1A000004, 0xE3A00002, 0xEA000019,
-	0x00001004, 0x00001000, 0x00000E00, 0xE5990618,
-	0xE3500000, 0x0AFFFFFC, 0xEBFFFD4E, 0xE20010FF,
-	0xE0082420, 0xE5851000, 0xE1A03800, 0xE1A03823,
-	0xE1530820, 0xE5862000, 0x1A000007, 0xE351003E,
-	0xD0843181, 0xD5D3C004, 0xD15C0002, 0xCA000002,
-	0xE5D33005, 0xE1530002, 0xAA000006, 0xE1A00820,
-	0xE1A00800, 0xE3800001, 0xEBFFFD59, 0xEBFFFD7C,
-	0xE1A00007, 0xE8BD83F0, 0xE1A0E00F, 0xE794F181,
-	0xE3500000, 0x0AFFFFD2, 0xE8BD83F0, 0xE92D4000,
-	0xE51F1094, 0xE5911000, 0xE1800801, 0xEBFFFD4C,
-	0xE8BD4000, 0xEAFFFD6E, 0xE92D4030, 0xE1A05000,
-	0xE1A04001, 0xE1A00C01, 0xE51F10BC, 0xE5911000,
-	0xE1800801, 0xEBFFFD42, 0xE1A01004, 0xE1A00005,
-	0xEBFFFD4D, 0xE8BD4030, 0xEAFFFD61, 0xE59F1020,
-	0xE5910000, 0xE59F201C, 0xE1500002, 0x21A0F00E,
-	0xE5922000, 0xE5802000, 0xE3E00000, 0xE5810000,
-	0xE1A0F00E, 0x000017FC, 0x000017F8, 0xE92D4010,
-	0xE1A04000, 0xEB000010, 0xE3540018, 0x03A00080,
-	0x0A000002, 0xE354001C, 0x18BD8010, 0xE3A00040,
-	0xE8BD4010, 0xEAFFFCD8, 0xE92D4000, 0xE3A01001,
-	0xE3A00018, 0xEBFFFFF0, 0xE3A01902, 0xE3A00AFE,
-	0xE2400601, 0xE5A01A08, 0xE8BD8000, 0xE3A000C0,
-	0xEAFFFCC9, 0xE1A0F00E, 0xE3A03000, 0xE1510002,
-	0x21A0F00E, 0xE7803101, 0xE2811001, 0xE1510002,
-	0x3AFFFFFB, 0xE1A0F00E, 0xE3A00000, 0xE1A0F00E,
-	0xE3A00001, 0xE1A0F00E, 0xE3A00002, 0xE1A0F00E,
-	0xE92D4000, 0xE59F001C, 0xE5901000, 0xE59F0018,
-	0xEBFFFCEF, 0xEBFFFCFC, 0xE3A00011, 0xEBFFFFB2,
-	0xE3A00000, 0xE8BD8000, 0x00001004, 0x00001014,
-	0xE1803001, 0xE1833002, 0xE3130003, 0x1A00000B,
-	0xE1A0C122, 0xE1A03000, 0xE24C2001, 0xE35C0000,
-	0x91A0F00E, 0xE491C004, 0xE483C004, 0xE1A0C002,
-	0xE2422001, 0xE35C0000, 0x8AFFFFF9, 0xE1A0F00E,
-	0xE1A03000, 0xE1A0C002, 0xE2422001, 0xE35C0000,
-	0x91A0F00E, 0xE4D1C001, 0xE4C3C001, 0xE1A0C002,
-	0xE2422001, 0xE35C0000, 0x8AFFFFF9, 0xE1A0F00E,
-	0x000002A0, 0x00000000, 0x000002E0, 0x10C80000,
-	0x000002E0, 0x11C80000, 0x00000334, 0x00C00000,
-	0x00000380, 0x40C04000, 0x00000380, 0x40C14000,
-	0x00000380, 0x40C24000, 0x00000380, 0x20C52000,
-	0x00000380, 0x20C72000, 0x00000380, 0x22C42200,
-	0x00000380, 0x22C62200, 0x00000380, 0x22C32200,
-	0x000003FC, 0x34C80000, 0x000003FC, 0x35C80000,
-	0x000003FC, 0x36C80000, 0x000003FC, 0x37C80000,
-	0x000002E0, 0x10D80000, 0x000002E0, 0x11D80000,
-	0x00000334, 0x00D00000, 0x00000380, 0x40D04000,
-	0x00000380, 0x40D14000, 0x00000380, 0x40D24000,
-	0x00000380, 0x20D52000, 0x00000380, 0x20D72000,
-	0x00000380, 0x22D42200, 0x00000380, 0x22D62200,
-	0x00000380, 0x22D32200, 0x000003FC, 0x34D80000,
-	0x000003FC, 0x35D80000, 0x000003FC, 0x36D80000,
-	0x000003FC, 0x37D80000, 0x0000047C, 0x00000000,
-	0x0000066C, 0x01000000, 0x000004A4, 0x00000202,
-	0x00000528, 0x00000000, 0x000005B0, 0x01700101,
-	0x0000066C, 0x01700000, 0x000005B0, 0x01240101,
-	0x0000066C, 0x01240000, 0x000005B0, 0x021C0202,
-	0x0000066C, 0x021C0000, 0x000005B0, 0x02140202,
-	0x0000066C, 0x02140000, 0x000005B0, 0x020C0202,
-	0x0000066C, 0x020C0000, 0x000005B0, 0x02280202,
-	0x0000066C, 0x02280000, 0x000005B0, 0x02440202,
-	0x0000066C, 0x02440000, 0x000005B0, 0x024C0202,
-	0x0000066C, 0x024C0000, 0x000005B0, 0x05300505,
-	0x0000066C, 0x05300000, 0x0000071C, 0x0000FF00,
-	0x0000082C, 0x00000000, 0x000008B4, 0x00001212,
-	0x000009B4, 0x01000000, 0x000009B4, 0x00000000,
-	0x000009EC, 0x00000101, 0x00000A14, 0x00000101,
-	0x00000D58, 0x00004040, 0x00000D60, 0x00002020,
-	0x00000D60, 0x0000FF00, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000
-};
diff --git a/sys/dev/mii/mtdphyreg.h b/sys/dev/mii/mtdphyreg.h
deleted file mode 100644
index 42303aa4b3f..00000000000
--- a/sys/dev/mii/mtdphyreg.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*	$OpenBSD: mtdphyreg.h,v 1.3 2003/06/02 19:08:58 jason Exp $	*/
-
-/*
- * Copyright (c) 1998 Jason L. Wright (jason@thought.net)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _DEV_MII_MTDPHYREG_H_
-#define	_DEV_MII_MTDPHYREG_H_
-
-/*
- * Myson MTD972 registers.
- */
-
-#define	MII_MTDPHY_ANNPTR	0x07	/* Auto-Neg Next Page Tx Register */
-#define	ANNPTR_NEXT		0x8000	/* Next Page */
-#define	ANNPTR_ACK		0x4000	/* Acknowledge */
-#define	ANNPTR_MPG		0x2000	/* Message Page */
-#define	ANNPTR_ACK2		0x1000	/* Acknowledge 2 */
-#define	ANNPTR_TOGGLE		0x0800	/* Toggle */
-#define	ANNPTR_DAT		0x0400	/* Data */
-
-#define	MII_MTDPHY_DCR		0x12	/* Disconnect Register */
-	/* count of the number of partitions */
-
-#define	MII_MTDPHY_FCSCR	0x13	/* False Carrier Sense Counter Reg */
-	/* count of the number of false carrier senses */
-
-#define	MII_MTDPHY_RECR		0x15	/* Receive Error Condition Register */
-	/* count of the number of receive errors */
-
-#define	MII_MTDPHY_RR		0x16	/* Revision Register */
-	/* revision of the MTD972 */
-
-#define	MII_MTDPHY_PCR		0x17	/* PHY Configuration Register */
-#define	PCR_NRZIEN		0x8000	/* NRZI Encode/Decode Enable */
-#define	PCR_TOCEL		0x4000	/* Descrambler Time Out Select */
-#define	PCR_TODIS		0x2000	/* Descrambler Time Out Disable */
-#define	PCR_RPTR		0x1000	/* Enable Repeater mode */
-#define	PCR_ENCSEL		0x0800	/* PMD ENCSEL pin control */
-#define	PCR_20MENB		0x0100	/* 20MHz output enable */
-#define	PCR_25MDIS		0x0080	/* 25MHz output disable */
-#define	PCR_FGLNKTX		0x0040	/* Force link status good */
-#define	PCR_FCONNT		0x0020	/* Bypass disconnect function */
-#define	PCR_TXOFF		0x0010	/* Turn off TX */
-#define	PCR_LEDTSL		0x0002	/* LED T display select */
-#define	PCR_LEDPSL		0x0001	/* LED P display select */
-
-#define	MII_MTDPHY_LBCR		0x18	/* Loopback and Bypass Control Reg */
-#define	LBCR_BP4B5B		0x4000	/* Bypass */
-#define	LBCR_BPSCRM		0x2000	/* Bypass */
-#define	LBCR_BPALGN		0x1000	/* Bypass symbol alignment */
-#define	LBCR_LBK10		0x0800	/* Loopback control for 10BT */
-#define	LBCR_LBK1		0x0200	/* Loopback control 1 for PMD */
-#define	LBCR_LBK0		0x0100	/* Loopback control 0 for PMD */
-#define	LBCR_FDCRS		0x0040	/* Full duplex CRS function */
-#define	LBCR_CERR		0x0010	/* Code Error */
-#define	LBCR_PERR		0x0008	/* Premature Error */
-#define	LBCR_LERR		0x0004	/* Link Error */
-#define	LBCR_FERR		0x0002	/* Frame Error */
-
-#define	MII_MTDPHY_PAR		0x19	/* PHY Address Register */
-#define	PAR_ANS			0x0400	/* State of autonegotiation */
-#define	PAR_FEFE		0x0100	/* Far End Fault Enable */
-#define	PAR_DPLX		0x0080	/* Duplex status */
-#define	PAR_SPD			0x0040	/* Speed status */
-#define	PAR_CONN		0x0020	/* Connection status */
-#define	PAR_PHYADDR_MASK	0x001f	/* PHY address mask */
-
-#define	MII_MTDPHY_10SR		0x1b	/* 10baseT Status Register */
-#define	TENSR_10BTSER		0x0200	/* Serial mode for 10BaseT interface */
-#define	TENSR_POLST		0x0001	/* Polarity state */
-
-#define	MII_MTDPHY_10CR		0x1c	/* 10baseT Control Register */
-#define	TENCR_LOE		0x0020	/* Link Pulse Ouput Enable */
-#define	TENCR_HBE		0x0010	/* HeartBeat Enable */
-#define	TENCR_UTPV		0x0008	/* TPOV=1, TPOI=0 */
-#define	TENCR_LSS		0x0004	/* Low Squelch Select */
-#define	TENCR_PENB		0x0002	/* Parity Enable */
-#define	TENCR_JEN		0x0001	/* Jabber Enable */
-
-#endif /* _DEV_MII_MTDPHYREG_H_ */
diff --git a/sys/dev/mii/txphyreg.h b/sys/dev/mii/txphyreg.h
deleted file mode 100644
index cdb9ffcff08..00000000000
--- a/sys/dev/mii/txphyreg.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*	$OpenBSD: txphyreg.h,v 1.3 2003/10/22 09:39:29 jmc Exp $	*/
-
-/*
- * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _DEV_MII_TXPHYREG_H_
-#define	_DEV_MII_TXPHYREG_H_
-
-/*
- * Texas Instruments TNETE2101 registers.
- */
-#define	MII_TXPHY_ID		0x10	/* PHY identifier */
-
-#define	MII_TXPHY_CTL		0x11	/* PHY control */
-#define	TXCTL_IGLINK		0x8000	/* ignore link */
-#define	TXCTL_SWAPOL		0x4000	/* swap polarity */
-#define	TXCTL_MANCONF		0x2000	/* manual configuration */
-#define	TXCTL_SQEEN		0x1000	/* SQE enable */
-#define	TXCTL_MTEST		0x0800	/* manufacturing test */
-#define	TXCTL_FIBER		0x0400	/* 100BaseFX mode */
-#define	TXCTL_FEFEN		0x0200	/* far-end fault indication enable */
-#define	TXCTL_NOENDEC		0x0100	/* no encode/decode */
-#define	TXCTL_NOALIGN		0x0080	/* no symbol alignment */
-#define	TXCTL_DUPONLY		0x0040	/* duplex LED only */
-#define	TXCTL_REPEATER		0x0020	/* repeater mode enable */
-#define	TXCTL_RXRESET		0x0010	/* 100baseTX rx reset */
-#define	TXCTL_NOLINKP		0x0008	/* disable link pulse tx */
-#define	TXCTL_NFEW		0x0004	/* no far end wrap */
-#define	TXCTL_INTEN		0x0002	/* interrupt enable */
-#define	TXCTL_TINT		0x0001	/* test interrupt */
-
-#define	MII_TXPHY_STS		0x12	/* PHY status */
-#define	TXSTS_MINT		0x8000	/* mii interrupt */
-#define	TXSTS_PHOK		0x4000	/* power high ok */
-#define	TXSTS_PLOK		0x2000	/* polarity ok */
-#define	TXSTS_TPENERGY		0x1000	/* TP energy detect */
-#define	TXSTS_SYNCLOSS		0x0800	/* 100btx rx descrambler sync loss */
-#define	TXSTS_FEFI		0x0400	/* Far-end fault indication */
-
-#endif /* _DEV_MII_MTDPHYREG_H_ */
diff --git a/sys/dev/pci/bt8370reg.h b/sys/dev/pci/bt8370reg.h
deleted file mode 100644
index 3414c79ca33..00000000000
--- a/sys/dev/pci/bt8370reg.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*	$OpenBSD: bt8370reg.h,v 1.3 2005/12/19 15:53:15 claudio Exp $ */
-
-/*
- * Copyright (c) 2004,2005  Internet Business Solutions AG, Zurich, Switzerland
- * Written by: Andre Oppermann <oppermann@accoom.net>
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-/* Bt8370 Register definitions */
-/* Globals */
-#define	Bt8370_DID	0x000		/* Device Identification */
-#define	Bt8370_CR0	0x001		/* Primary control register */
-#define		CR0_RESET	0x80		/* Reset Framer */
-#define		CR0_E1_FAS	0x00		/* E1 FAS only */
-#define		CR0_E1_FAS_CRC	0x08		/* E1 FAS+CRC4 */
-#define		CR0_T1_SF	0x09		/* T1 SF */
-#define		CR0_T1_ESF	0x1B		/* T1 ESF+ForceCRC */
-#define	Bt8370_JAT_CR	0x002		/* Jitter attenuator conf */
-#define		JAT_CR_JEN	0x80		/* Jitter anntenuator enable */
-#define		JAT_CR_JFREE	0x40		/* Free running JCLK and CLADO */
-#define		JAT_CR_JDIR_TX	0x00		/* JAT in TX direction */
-#define		JAT_CR_JDIR_RX	0x20		/* JAT in RC direction */
-#define		JAT_CR_JAUTO	0x10		/* JCLK Acceleration */
-#define		JAT_CR_CENTER	0x80		/* Force JAT to center */
-#define		JAT_CR_JSIZE8	0x00		/* Elastic store size 8 bits */
-#define		JAT_CR_JSIZE16	0x01		/* Elastic store size 16 bits */
-#define		JAT_CR_JSIZE32	0x02		/* Elastic store size 32 bits */
-#define		JAT_CR_JSIZE64	0x03		/* Elastic store size 64 bits */
-#define		JAT_CR_JSIZE128	0x04		/* Elastic store size 128 bits */
-#define	Bt8370_IRR	0x003		/* Interrupt request register */
-/* Interrupt Status */
-#define	Bt8370_ISR7	0x004		/* Alarm 1 Interrupt Status */
-#define	Bt8370_ISR6	0x005		/* Alarm 2 Interrupt Status */
-#define	Bt8370_ISR5	0x006		/* Error Interrupt Status */
-#define	Bt8370_ISR4	0x007		/* Counter Overflow Interrupt Status */
-#define	Bt8370_ISR3	0x008		/* Timer Interrupt Status */
-#define	Bt8370_ISR2	0x009		/* Data Link 1 Interrupt Status */
-#define	Bt8370_ISR1	0x00A		/* Data Link 2 Interrupt Status */
-#define	Bt8370_ISR0	0x00B		/* Pattern Interrupt Status */
-/* Interrupt Enable */
-#define	Bt8370_IER7	0x00C		/* Alarm 1 Interrupt Enable register */
-#define	Bt8370_IER6	0x00D		/* Alarm 2 Interrupt Enable register */
-#define	Bt8370_IER5	0x00E		/* Error Interrupt Enable register */
-#define	Bt8370_IER4	0x00F		/* Count Overflow Interrupt Enable register */
-#define	Bt8370_IER3	0x010		/* Timer Interrupt Enable register */
-#define	Bt8370_IER2	0x011		/* Data Link 1 Interrupt Enable register */
-#define	Bt8370_IER1	0x012		/* Date Link 2 Interrupt Enable register */
-#define	Bt8370_IER0	0x013		/* Pattern Interrupt Enable register */
-/* Primary */
-#define	Bt8370_LOOP	0x014		/* Loopback Configuration register */
-#define		LOOP_PLOOP	0x08		/* Remote Payload Loopback */
-#define		LOOP_LLOOP	0x04		/* Remote Line Loopback */
-#define		LOOP_FLOOP	0x02		/* Local Framer Loopback */
-#define		LOOP_ALOOP	0x01		/* Local Analog Loopback */
-#define	Bt8370_DL3_TS	0x015		/* External Data Link Channel */
-#define	Bt8370_DL3_BIT	0x016		/* External Data Link Bit */
-#define	Bt8370_FSTAT	0x017		/* Offline Framer Status */
-#define		FSTAT_INVALID	0x10		/* No candidate */
-#define		FSTAT_FOUND	0x08		/* Frame Search Successful */
-#define		FSTAT_TIMEOUT	0x04		/* Framer Search Timeout */
-#define		FSTAT_ACTIVE	0x02		/* Framer Active */
-#define		FSTAT_RXTXN	0x01		/* RX/TX Reframe Operation */
-#define	Bt8370_PIO	0x018		/* Programmable Input/Output */
-#define		PIO_ONESEC_IO	0x80		/*  */
-#define		PIO_RDL_IO	0x40		/*  */
-#define		PIO_TDL_IO	0x20		/*  */
-#define		PIO_INDY_IO	0x10		/*  */
-#define		PIO_RFSYNC_IO	0x08		/*  */
-#define		PIO_RMSYNC_IO	0x04		/*  */
-#define		PIO_TFSYNC_IO	0x02		/*  */
-#define		PIO_TMSYNC_IO	0x01		/*  */
-#define	Bt8370_POE	0x019		/* Programmable Output Enable */
-#define		POE_TDL_OE	0x20		/*  */
-#define		POE_RDL_OE	0x10		/*  */
-#define		POE_INDY_OE	0x08		/*  */
-#define		POE_TCKO_OE	0x04		/*  */
-#define		POE_CLADO_OE	0x02		/*  */
-#define		POE_RCKO_OE	0x01		/*  */
-#define	Bt8370_CMUX	0x01A		/* Clock Input Mux */
-#define		CMUX_RSBCKI_RSBCKI	0x00	/*  */
-#define		CMUX_RSBCKI_TSBCKI	0x40	/*  */
-#define		CMUX_RSBCKI_CLADI	0x80	/*  */
-#define		CMUX_RSBCKI_CLADO	0xC0	/*  */
-#define		CMUX_TSBCKI_TSBCKI	0x00	/*  */
-#define		CMUX_TSBCKI_RSBCKI	0x10	/*  */
-#define		CMUX_TSBCKI_CLADI	0x20	/*  */
-#define		CMUX_TSBCKI_CLADO	0x30	/*  */
-#define		CMUX_CLADI_CLADI	0x00	/*  */
-#define		CMUX_CLADI_RCKO		0x04	/*  */
-#define		CMUX_CLADI_TSBCKI	0x08	/*  */
-#define		CMUX_CLADI_TCKI		0x0C	/*  */
-#define		CMUX_TCKI_TCKI		0x00	/*  */
-#define		CMUX_TCKI_RCKO		0x01	/*  */
-#define		CMUX_TCKI_RSBCKI	0x02	/*  */
-#define		CMUX_TCKI_CLADO		0x03	/*  */
-#define	Bt8370_TMUX	0x01B		/* Test Mux Configuration */
-#define	Bt8370_TEST	0x01C		/* Test Configuration */
-/* Receive LIU (RLIU) */
-#define	Bt8370_LIU_CR	0x020		/* LIU Configuration */
-#define		LIU_CR_RST_LIU	0x80		/* Reset RLIU */
-#define		LIU_CR_SQUELCH	0x40		/* Enable Squelch */
-#define		LIU_CR_FORCE_VGA 0x20		/* Internal Variable Gain Amp */
-#define		LIU_CR_RDIGI	0x10		/* Enable Receive Digital Inputs */
-#define		LIU_CR_ATTN0	0x00		/* Bridge Attenuation 0db */
-#define		LIU_CR_ATTN10	0x04		/* Bridge Attenuation -10db */
-#define		LIU_CR_ATTN20	0x08		/* Bridge Attenuation -20db */
-#define		LIU_CR_ATTN30	0x0C		/* Bridge Attenuation -30db */
-#define		LIU_CR_MAGIC	0x01		/* This one must be enabled */
-#define	Bt8370_RSTAT	0x021		/* Receive LIU Status */
-#define		RSTAT_CPDERR	0x80		/* CLAD Phase detector lost lock */
-#define		RSTAT_JMPTY	0x40		/* JAT Empty/Full */
-#define		RSTAT_ZCSUB	0x20		/* ZCS detected */
-#define		RSTAT_EXZ	0x10		/* Excessive Zeros */
-#define		RSTAT_BPV	0x08		/* Bipolar Violations */
-#define		RSTAT_EYEOPEN	0x02		/* Equalization State */
-#define		RSTAT_PRE_EQ	0x01		/* Pre-Equalizer Status */
-#define	Bt8370_RLIU_CR	0x022		/* Receive LIU Configuration */
-#define		RLIU_CR_FRZ_SHORT 0x80		/* Freeze Equalizer for short lines */
-#define		RLIU_CR_HI_CLICE  0x40		/* High Clock Slicer Threshold */
-#define		RLIU_CR_AGC32	0x00		/* AGC Observation Window 32bit */
-#define		RLIU_CR_AGC128	0x10		/* AGC Observation Window 128bit */
-#define		RLIU_CR_AGC512	0x20		/* AGC Observation Window 512bit */
-#define		RLIU_CR_AGC2048	0x30		/* AGC Observation Window 2048bit */
-#define		RLIU_CR_EQ_FRZ	0x08		/* Freeze EQ Coefficients */
-#define		RLIU_CR_OOR_BLOCK 0x04		/* Disable automatic RLBO */
-#define		RLIU_CR_RLBO	0x02		/* Receiver Line Build Out */
-#define		RLIU_CR_LONG_EYE  0x01		/* Eye Open Timeout 8192bit */
-#define	Bt8370_LPF	0x023		/* RPLL Low Pass Filter */
-#define	Bt8370_VGA_MAX	0x024		/* Variable Gain Amplifier Maximum */
-#define	Bt8370_EQ_DAT	0x025		/* Equalizer Coefficient Data register */
-#define	Bt8370_EQ_PTR	0x026		/* Equalizer Coefficient Table Pointer */
-#define	Bt8370_DSLICE	0x027		/* Data Slicer Threshold */
-#define	Bt8370_EQ_OUT	0x028		/* Equalizer Output Levels */
-#define	Bt8370_VGA	0x029		/* Variable Gain Amplifier Status */
-#define	Bt8370_PRE_EQ	0x02A		/* Pre-Equalizer */
-#define	Bt8370_COEFF	0x030 /* -037 *//* LMS Adjusted Equalizer Coefficient Status */
-#define	Bt8370_GAIN	0x038 /* -03C *//* Equalizer Gain Thresholds */
-/* Digital Reveiver (RCVR) */
-#define	Bt8370_RCR0	0x040		/* Receiver Configuration */
-#define		RCR0_HDB3	0x00		/* */
-#define		RCR0_B8ZS	0x00		/* */
-#define		RCR0_AMI	0x80		/* */
-#define		RCR0_RABORT	0x40		/* */
-#define		RCR0_RFORCE	0x20		/* */
-#define		RCR0_LFA_FAS	0x18		/* 3 consecutive FAS Errors */
-#define		RCR0_LFA_FASCRC	0x08		/* 3 consecutive FAS or 915 CRC Errors */
-#define		RCR0_LFA_26F	0x08		/* 2 out of 6 F bit Errors */
-#define		RCR0_RZCS_BPV	0x00		/* */
-#define		RCR0_RZCS_NBPV	0x01		/* */
-#define	Bt8370_RPATT	0x041		/* Receive Test Pattern Configuration */
-#define	Bt8370_RLB	0x042		/* Receive Loopback Code Detector Configuration */
-#define	Bt8370_LBA	0x043		/* Loopback Activate Code Pattern */
-#define	Bt8370_LBD	0x044		/* Loopback Deactivate Code Pattern */
-#define	Bt8370_RALM	0x045		/* Receive Alarm Signal Configuration */
-#define		RALM_FSNFAS	0x20		/* Include FS/NFAS in FERR and FRED */
-#define	Bt8370_LATCH	0x046		/* Alarm/Error/Counter Latch Configuration */
-#define		LATCH_STOPCNT	0x08		/* Stop Error Counter during RLOF,RLOS,RAIS */
-#define	Bt8370_ALM1	0x047		/* Alarm 1 Status */
-#define		ALM1_RMYEL	0x80		/* Receive Multifram Yellow Alarm */
-#define		ALM1_RYEL	0x40		/* Receive Yellow Alarm */
-#define		ALM1_RAIS	0x10		/* Reveive Alarm Indication Signal */
-#define		ALM1_RALOS	0x09		/* Receive Analog Loss of Signal */
-#define		ALM1_RLOS	0x04		/* Receive Loss of Signal */
-#define		ALM1_RLOF	0x02		/* Receive Loss of Frame Alignment */
-#define		ALM1_SIGFRZ	0x01		/* Signalling Freeze */
-#define	Bt8370_ALM2	0x048		/* Alarm 2 Status */
-#define		ALM2_LOOPDN	0x80		/*  */
-#define		ALM2_LOOPUP	0x40		/*  */
-#define		ALM2_TSHORT	0x10		/* Transmit Short Circuit */
-#define		ALM2_TLOC	0x08		/* Transmit Loss of clock */
-#define		ALM2_TLOF	0x02		/* Transmit Loss of Frame alignment */
-#define	Bt8370_ALM3	0x049		/* Alarm 3 Status */
-#define		ALM3_RMAIS	0x40		/* Receive TS16 Alarm Indication */
-#define		ALM3_SEF	0x20		/* Severely Errored Frame */
-#define		ALM3_SRED	0x10		/* Loss of CAS Alignment */
-#define		ALM3_MRED	0x08		/* Loss of MFAS Alignment */
-#define		ALM3_FRED	0x04		/* Loss of T1/FAS Alignment */
-#define		ALM3_LOF1	0x02		/* Reason for Loss of Frame Alignment */
-#define		ALM3_LOF0	0x01		/* Reason for Loss of Frame Alignment */
-/* Error/Alarm Counters */
-#define	Bt8370_FERR_LSB	0x050		/* Framing Bit Error Counter LSB */
-#define	Bt8370_FERR_MSB	0x051		/* ditto MSB */
-#define	Bt8370_CERR_LSB	0x052		/* CRC Error Counter LSB */
-#define	Bt8370_CERR_MSB	0x053		/* ditto MSB */
-#define	Bt8370_LCV_LSB	0x054		/* Line Code Violation Counter LSB*/
-#define	Bt8370_LCV_MSB	0x055		/* ditto MSB */
-#define	Bt8370_FEBE_LSB	0x056		/* Far End Block Error Counter LSB*/
-#define	Bt8370_FEBE_MSB	0x057		/* ditto MSB */
-#define	Bt8370_BERR_LSB	0x058		/* PRBS Bit Error Counter LSB */
-#define	Bt8370_BERR_MSB	0x059		/* ditto MSB */
-/* Receive Sa-Byte */
-#define	Bt8370_RSA4	0x05B		/* Receive Sa4 Byte Buffer */
-#define	Bt8370_RSA5	0x05C		/* ditto Sa5 */
-#define	Bt8370_RSA6	0x05D		/* ditto Sa6 */
-#define	Bt8370_RSA7	0x05E		/* ditto Sa7 */
-#define	Bt8370_RSA8	0x05F		/* ditto Sa8 */
-/* Transmit LIU (TLIU) */
-#define	Bt8370_SHAPE	0x060 /* -067 *//* Transmit Pulse Shape Configuration */
-#define	Bt8370_TLIU_CR	0x068		/* Transmit LIU Configuration */
-#define		TLIU_CR_120	0x4C		/* 120 Ohms, external term */
-#define		TLIU_CR_100	0x40		/* 100 Ohms, external term */
-/* Digital Transmitter (XMTR) */
-#define	Bt8370_TCR0	0x070		/* Transmit Framer Configuration */
-#define		TCR0_FAS	0x00		/* FAS Only */
-#define		TCR0_MFAS	0x04		/* FAS + MFAS*/
-#define		TCR0_SF		0x04		/* SF Only */
-#define		TCR0_ESF	0x01		/* ESF Only */
-#define		TCR0_ESFCRC	0x0D		/* ESF + Force CRC */
-#define	Bt8370_TCR1	0x071		/* Transmitter Configuration */
-#define		TCR1_TABORT	0x40		/* Disable TX Offline Framer */
-#define		TCR1_TFORCE	0x20		/* Force TX Reframe */
-#define		TCR1_HDB3	0x01		/* Line code HDB3 */
-#define		TCR1_B8ZS	0x01		/* Line code B8ZS */
-#define		TCR1_AMI	0x00		/* Line code AMI */
-#define		TCR1_3FAS	0x10		/* 3 consecutive FAS Errors */
-#define		TCR1_26F	0x10		/* 2 out of 6 Frame Bit Errors */
-#define	Bt8370_TFRM	0x072		/* Transmit Frame Format */
-#define		TFRM_MYEL	0x20		/* Insert MultiFrame Yellow Alarm */
-#define		TFRM_YEL	0x10		/* Insert Yellow Alarm */
-#define		TFRM_MF		0x08		/* Insert MultiFrame Alignment */
-#define		TFRM_FE		0x04		/* Insert FEBE */
-#define		TFRM_CRC	0x02		/* Insert CRC4 */
-#define		TFRM_FBIT	0x01		/* Insert F bit or FAS/NAS alignment */
-#define	Bt8370_TERROR	0x073		/* Transmit Error Insert */
-#define	Bt8370_TMAN	0x074		/* Transmit Manual Sa-Byte/FEBE Configuration */
-#define		TMAN_MALL	0xF8		/* All Sa Bytes Manual */
-#define	Bt8370_TALM	0x075		/* Transmit Alarm Signal Configuration */
-#define		TALM_AMYEL	0x20		/* Automatic MultiFrame Yellow Alarm transmit */
-#define		TALM_AYEL	0x10		/* Automatic Yellow Alarm transmit */
-#define		TALM_AAIS	0x08		/* Automatic AIS Alarm transmit */
-#define	Bt8370_TPATT	0x076		/* Transmit Test Pattern Configuration */
-#define	Bt8370_TLB	0x077		/* Transmit Inband Loopback Code Configuration */
-#define	Bt8370_LBP	0x078		/* Transmit Inband Loopback Code Pattern */
-/* Transmit Sa-Byte */
-#define	Bt8370_TSA4	0x07B		/* Transmit Sa4 Byte Buffer */
-#define	Bt8370_TSA5	0x07C		/* ditto Sa5 */
-#define	Bt8370_TSA6	0x07D		/* ditto Sa6 */
-#define	Bt8370_TSA7	0x07E		/* ditto Sa7 */
-#define	Bt8370_TSA8	0x07F		/* ditto Sa8 */
-/* Clock Rate Adapter (CLAD) */
-#define	Bt8370_CLAD_CR	0x090		/* Clock Rate Adapter Configuration */
-#define		CLAD_CR_CEN	0x80		/* Enable CLAD phase detector */
-#define		CLAD_CR_XSEL_1X	0x00		/* Line rate multiplier 1X */
-#define		CLAD_CR_XSEL_2X	0x10		/* Line rate multiplier 2X */
-#define		CLAD_CR_XSEL_4X	0x20		/* Line rate multiplier 4X */
-#define		CLAD_CR_XSEL_8X	0x30		/* Line rate multiplier 8X */
-#define		CLAD_CR_LFGAIN	0x05		/* Loop filter gain */
-#define	Bt8370_CSEL	0x091		/* CLAD Frequency Select */
-#define		CSEL_VSEL_1536	0x60		/* 1536kHz */
-#define		CSEL_VSEL_1544	0x50		/* 1544kHz */
-#define		CSEL_VSEL_2048	0x10		/* 2048kHz */
-#define		CSEL_VSEL_4096	0x20		/* 4096kHz */
-#define		CSEL_VSEL_8192	0x30		/* 8192kHz */
-#define		CSEL_OSEL_1536	0x06		/* 1536kHz */
-#define		CSEL_OSEL_1544	0x05		/* 1544kHz */
-#define		CSEL_OSEL_2048	0x01		/* 2048kHz */
-#define		CSEL_OSEL_4096	0x02		/* 4096kHz */
-#define		CSEL_OSEL_8192	0x03		/* 8192kHz */
-#define	Bt8370_CPHASE	0x092		/* CLAD Phase Detector Scale Factor */
-#define	Bt8370_CTEST	0x093		/* CLAD Test */
-/* Bit Oriented Protocol Transceiver (BOP) */
-#define	Bt8370_BOP	0x0A0		/* Bit Oriented Protocol Transceiver */
-#define	Bt8370_TBOP	0x0A1		/* Transmit BOP Code Word */
-#define	Bt8370_RBOP	0x0A2		/* Receive BOP Code Word */
-#define	Bt8370_BOP_STAT	0x0A3		/* BOP Status */
-/* Data Link #1 */
-#define	Bt8370_DL1_TS	0x0A4		/* DL1 Time Slot Enable */
-#define	Bt8370_DL1_BIT	0x0A5		/* DL1 Bit Enable */
-#define	Bt8370_DL1_CTL	0x0A6		/* DL1 Control */
-#define	Bt8370_RDL1_FFC	0x0A7		/* RDL #1 FIFO Fill Control */
-#define	Bt8370_RDL1	0x0A8		/* Receive Data Link FIFO #1 */
-#define	Bt8370_RDL1_STAT 0x0A9		/* RDL #1 Status */
-#define	Bt8370_PRM1	0x0AA		/* Performance Report Message */
-#define	Bt8370_TDL1_FEC	0x0AB		/* TDL #1 FIFO Empty Control */
-#define	Bt8370_TDL1_EOM	0x0AC		/* TDL #1 End of Message Control */
-#define	Bt8370_TDL1	0x0AD		/* Transmit Data Link FIFO #1*/
-#define	Bt8370_TDL1_STAT 0x0AE		/* TDL #1 Status */
-/* Data Link #2 */
-#define	Bt8370_DL2_TS	0x0AF		/* DL2 Time Slot Enable */
-#define	Bt8370_DL2_BIT	0x0B0		/* DL2 Bit Enable */
-#define	Bt8370_DL2_CTL	0x0B1		/* DL2 Control */
-#define	Bt8370_RDL2_FFC	0x0B2		/* RDL #2 FIFO Fill Control */
-#define	Bt8370_RDL2	0x0B3		/* Receive Data Link FIFO #2 */
-#define	Bt8370_RDL2_STAT 0x0B4		/* RDL #2 Status */
-#define	Bt8370_TDL2_FEC	0x0B6		/* TDL #2 FIFO Empty Control */
-#define	Bt8370_TDL2_EOM	0x0B7		/* TDL #2 End of Message Control */
-#define	Bt8370_TDL2	0x0B8		/* Transmit Data Link FIFO #2*/
-#define	Bt8370_TDL2_STAT 0x0B9		/* TDL #2 Status */
-/* Test */
-#define	Bt8370_TEST1	0x0BA		/* DLINK Test Configuration */
-#define	Bt8370_TEST2	0x0BB		/* DLINK Test Status */
-#define	Bt8370_TEST3	0x0BC		/* DLINK Test Status */
-#define	Bt8370_TEST4	0x0BD		/* DLINK Test Control #1 or Configuration #2 */
-#define	Bt8370_TEST5	0x0BE		/* DLINK Test Control #2 or Configuration #2 */
-/* System Bus Interface (SBI) */
-#define	Bt8370_SBI_CR	0x0D0		/* System Bus Interface Configuration */
-#define		SBI_CR_X2CLK	0x80		/* Times 2 clock */
-#define		SBI_CR_SBI_OE	0x40		/* Enable SBI */
-#define		SBI_CR_1536	0x08		/* 1536, 24TS*/
-#define		SBI_CR_1544	0x07		/* 1544, 24TS + F bit */
-#define		SBI_CR_2048	0x06		/* 2048, 32TS */
-#define		SBI_CR_4096_A	0x04		/* 4096 Group A */
-#define		SBI_CR_4096_B	0x05		/* 4096 Group B */
-#define		SBI_CR_8192_A	0x00		/* 8192 Group A */
-#define		SBI_CR_8192_B	0x01		/* 8192 Group B */
-#define		SBI_CR_8192_C	0x02		/* 8192 Group C */
-#define		SBI_CR_8192_D	0x03		/* 8192 Group D */
-#define	Bt8370_RSB_CR	0x0D1		/* Receive System Bus Configuration */
-#define		RSB_CR_BUS_RSB	0x80		/* Multiple devices on bus */
-#define		RSB_CR_SIG_OFF	0x40		/* Inhibit RPCMO Signal reinsertion */
-#define		RSB_CR_RPCM_NEG	0x20		/* RSB falling edge */
-#define		RSB_CR_RSYN_NEG	0x10		/* RFSYNC falling edge */
-#define		RSB_CR_BUS_FRZ	0x08		/* Multiple devices on bus */
-#define		RSB_CR_RSB_CTR	0x04		/* Force RSLIP Center */
-#define		RSB_CR_RSBI_NORMAL	0x00	/* Normal Slip Buffer Mode */
-#define		RSB_CR_RSBI_ELASTIC	0x02	/* Receive Slip Buffer Elastic Mode */
-#define		RSB_CR_RSBI_BYPASS	0x03	/* Bypass Slip Buffer */
-#define	Bt8370_RSYNC_BIT 0x0D2		/* Receive System Bus Sync Bit Offset */
-#define	Bt8370_RSYNC_TS	0x0D3		/* Receive System Bus Sync Time Slot Offset */
-#define	Bt8370_TSB_CR	0x0D4		/* Transmit System Bus Configuration */
-#define		TSB_CR_BUS_TSB	0x80		/* Bused TSB output */
-#define		TSB_CR_TPCM_NEG	0x20		/* TINDO falling edge */
-#define		TSB_CR_TSYN_NEG	0x10		/* TFSYNC falling edge */
-#define		TSB_CR_TSB_CTR	0x04		/* Force TSLIP Center */
-#define		TSB_CR_TSB_NORMAL	0x00	/* Normal Slip Buffer Mode */
-#define		TSB_CR_TSB_ELASTIC	0x02	/* Send Slip Buffer Elastic Mode */
-#define		TSB_CR_TSB_BYPASS	0x03	/* Bypass Slip Buffer */
-#define	Bt8370_TSYNC_BIT 0x0D5		/* Transmit System Bus Sync Bit Offset */
-#define	Bt8370_TSYNC_TS	0x0D6		/* Transmit System Bus Sync Time Slot Offset */
-#define	Bt8370_RSIG_CR	0x0D7		/* Receive Signaling Configuration */
-#define		RSIG_CR_FRZ_OFF	0x04		/* Manual Signaling Update FRZ */
-#define		RSIG_CR_THRU	0x01		/* Transparent Robbed Bit Signaling */
-#define	Bt8370_RSYNC_FRM 0x0D8		/* Signaling Reinsertion Frame Offset */
-#define	Bt8370_SSTAT	0x0D9		/* Slip Buffer Status */
-#define		SSTAT_TSDIR	0x80		/* Transmit Slip Direction */
-#define		SSTAT_TFSLIP	0x40		/* Controlled Slip Event */
-#define		SSTAT_TUSLIP	0x20		/* Uncontrolled Slip Event */
-#define		SSTAT_RSDIR	0x08		/* Receive Slip Direction */
-#define		SSTAT_RFSLIP	0x04		/* Controlled Slip Event */
-#define		SSTAT_RUSLIP	0x02		/* Uncontrolled Slip Event */
-#define	Bt8370_STACK	0x0DA		/* Receive Signaling Stack */
-#define	Bt8370_RPHASE	0x0DB		/* RSLIP Phase Status */
-#define	Bt8370_TPHASE	0x0DC		/* TSLIP Phase Status */
-#define	Bt8370_PERR	0x0DD		/* RAM Parity Status */
-#define	Bt8370_SBCn	0x0E0 /* -0FF *//* System Bus Per-Channel Control */
-#define		SBCn_INSERT	0x40		/* Insert RX Signaling on RPCMO */
-#define		SBCn_SIG_LP	0x20		/* Local Signaling Loopback */
-#define		SBCn_RLOOP	0x10		/* Local Loopback */
-#define		SBCn_RINDO	0x08		/* Activate RINDO time slot indicator */
-#define		SBCn_TINDO	0x04		/* Activate TINDO time slot indicator */
-#define		SBCn_TSIG_AB	0x02		/* AB Signaling */
-#define		SBCn_ASSIGN	0x01		/* Enable System Bus Time Slot */
-/* Buffer Memory */
-#define	Bt8370_TPCn	0x100		/* Transmit Per-Channel Control */
-#define		TPCn_CLEAR	0x00		/* Clear Channel Mode */
-#define		TPCn_EMFBIT	0x80		/* TB7ZS/EMFBIT */
-#define		TPCn_TLOOP	0x40		/* Remote DS0 Channel Loopback */
-#define		TPCn_TIDLE	0x20		/* Transmit Idle */
-#define		TPCn_TLOCAL	0x10		/* Transmit Local Signaling */
-#define		TPCn_TSIGA	0x08		/* ABCD signaling value */
-#define		TPCn_TSIGB	0x04		/* ABCD signaling value */
-#define		TPCn_TSIGC	0x02		/* ABCD signaling value */
-#define		TPCn_TSIGD	0x01		/* ABCD signaling value */
-#define		TPCn_TSIGO	TPCn_TSIGA	/* Transmit Signaling Output */
-#define		TPCn_RSIGO	TPCn_TSIGB	/* Receive Signaling Output */
-#define	Bt8370_TSIGn	0x120		/* Transmit Signaling Buffer */
-#define	Bt8370_TSLIP_LOn 0x140		/* Transmit PCM Slip Buffer */
-#define	Bt8370_TSLIP_HIn 0x160		/* Transmit PCM Slip Buffer */
-#define	Bt8370_RPCn	0x180		/* Receive Per-Channel Control */
-#define		RPCn_CLEAR	0x00		/* Clear Channel Mode */
-#define		RPCn_RSIG_AB	0x80		/* AB Signaling */
-#define		RPCn_RIDLE	0x40		/* Time Slot Idle */
-#define		RPCn_SIG_STK	0x20		/* Receive Signal Stack */
-#define		RPCn_RLOCAL	0x10		/* Enable Local Signaling Output */
-#define		RPCn_RSIGA	0x08		/* Local Receive Signaling */
-#define		RPCn_RSIGB	0x04		/* Local Receive Signaling */
-#define		RPCn_RSIGC	0x02		/* Local Receive Signaling */
-#define		RPCn_RSIGD	0x01		/* Local Receive Signaling */
-#define	Bt8370_RSIGn	0x1A0		/* Receive Signaling Buffer */
-#define	Bt8370_RSLIP_LOn 0x1C0		/* Receive PCM Slip Buffer */
-#define	Bt8370_RSLIP_HIn 0x1E0		/* Receive PCM Slip Buffer */
diff --git a/sys/dev/pci/pciide_i31244_reg.h b/sys/dev/pci/pciide_i31244_reg.h
deleted file mode 100644
index bf7ea9415f0..00000000000
--- a/sys/dev/pci/pciide_i31244_reg.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/*	$OpenBSD: pciide_i31244_reg.h,v 1.2 2006/11/19 20:09:59 brad Exp $	*/
-/*	$NetBSD: pciide_i31244_reg.h,v 1.2 2005/02/11 21:12:32 rearnsha Exp $	*/
-
-/*
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _DEV_PCI_PCIIDE_I31244_REG_H_
-#define	_DEV_PCI_PCIIDE_I31244_REG_H_
-
-/*
- * Register definitions for the Intel i31244 Serial ATA Controller.
- */
-
-/*
- * In DPA mode, the i31244 has a single 64-bit BAR.
- */
-#define	ARTISEA_PCI_DPA_BASE	PCI_MAPREG_START
-
-/*
- * Extended Control and Status Register 0
- */
-#define	ARTISEA_PCI_SUECSR0	0x98
-#define	SUECSR0_LED0_ONLY	(1U << 28)	/* activity on LED0 only */
-#define	SUECSR0_SFSS		(1U << 16)	/* Superset Features
-						   Secondary Select */
-
-#define ARTISEA_PCI_SUDCSCR	0xa0
-#define SUDCSCR_DMA_WCAE	0x02		/* Write cache align enable */
-#define SUDCSCR_DMA_RCAE	0x01		/* Read cache align enable */
-
-/*
- * DPA mode shared registers.
- */
-#define	ARTISEA_SUPDIPR		0x00	/* DPA interrupt pending register */
-#define	SUPDIPR_PORTSHIFT(x)	((x) * 8)
-#define	SUPDIPR_PHY_CS		(1U << 0)	/* PHY change state */
-#define	SUPDIPR_PHY_RDY		(1U << 1)	/* PHY ready */
-#define	SUPDIPR_FIFO_ERR	(1U << 2)	/* FIFO error */
-#define	SUPDIPR_ERR_RCVD	(1U << 3)	/* ERR received */
-#define	SUPDIPR_U_FIS_R		(1U << 4)	/* unrecog. FIS reception */
-#define	SUPDIPR_DATA_I		(1U << 5)	/* data integrity */
-#define	SUPDIPR_CRC_ED		(1U << 6)	/* CRC error detected */
-#define	SUPDIPR_IDE		(1U << 7)	/* IDE interrupt */
-
-#define	ARTISEA_SUPDIMR		0x04	/* DPA interrupt mask register */
-	/* See SUPDIPR bits. */
-
-/*
- * DPA mode offset to per-port registers.
- */
-#define	ARTISEA_DPA_PORT_BASE(x) (((x) + 1) * 0x200)
-
-/*
- * DPA mode per-port registers.
- */
-#define	ARTISEA_SUPDDR		0x00	/* DPA data port register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDER		0x04	/* DPA error register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDFR		0x06	/* DPA features register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCSR		0x08	/* DPA sector count register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDSNR		0x0c	/* DPA sector number register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCLR		0x10	/* DPA cylinder low register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCHR		0x14	/* DPA cylinder high register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDDHR		0x18	/* DPA device/head register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDSR		0x1c	/* DPA status register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCR		0x1d	/* DPA command register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDASR		0x28	/* DPA alt. status register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDDCTLR	0x29	/* DPA device control register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDUDDTPR	0x64	/* DPA upper DMA desc. table pointer */
-
-#define	ARTISEA_SUPDUDDPR	0x6c	/* DPA upper DMA data buffer pointer */
-
-#define	ARTISEA_SUPDDCMDR	0x70	/* DPA DMA command register */
-	/* Almost compatible with PCI IDE, but not quite. */
-#define	SUPDDCMDR_START		(1U << 0)	/* start DMA transfer (c) */
-#define	SUPDDCMDR_WRITE		(1U << 3)	/* write *to memory* (c) */
-#define	SUPDDCMDR_DP_DMA_ACT	(1U << 8)	/* first party DMA active */
-#define	SUPDDCMDR_FP_DMA_DIR	(1U << 9)	/* 1 = host->device */
-
-#define	ARTISEA_SUPDDSR		0x72	/* DPA DMA status register */
-	/* PCI IDE compatible */
-
-#define	ARTISEA_SUPDDDTPR	0x74	/* DPA DMA desc. table pointer */
-
-#define	ARTISEA_SUPERSET_DPA_OFF 0x100	/* offset to Superset regs: DPA mode */
-
-#define	ARTISEA_SUPDSSSR	0x000	/* DPA SATA SStatus register */
-#define	SUPDSSSR_IPM_NP		(0 << 8)	/* device not present */
-#define	SUPDSSSR_IPM_ACT	(1U << 8)	/* active state */
-#define	SUPDSSSR_IPM_PARTIAL	(2U << 8)	/* partial power mgmt */
-#define	SUPDSSSR_IPM_SLUMBER	(6U << 8)	/* slumber power mgmt */
-#define	SUPDSSSR_SPD_NP		(0 << 4)	/* device not present */
-#define	SUPDSSSR_SPD_G1		(1U << 4)	/* Generation 1 speed */
-#define	SUPDSSSR_DET_NP		(0 << 0)	/* device not present */
-#define	SUPDSSSR_DET_PHY_CNE	(1U << 0)	/* PHY comm. not established */
-#define	SUPDSSSR_DET_PHY_CE	(3U << 0)	/* PHY comm. established */
-#define	SUPDSSSR_DET_PHY_LOOP	(4U << 0)	/* loopback mode */
-
-#define	ARTISEA_SUPDSSER	0x004	/* DPA SATA SError register */
-#define	SUPDSSER_DIAG_F		(1U << 25)	/* invalid FIS type */
-#define	SUPDSSER_DIAG_T		(1U << 24)	/* not implemented */
-#define	SUPDSSER_DIAG_S		(1U << 23)	/* not implemented */
-#define	SUPDSSER_DIAG_H		(1U << 22)	/* handshake error */
-#define	SUPDSSER_DIAG_C		(1U << 21)	/* CRC error */
-#define	SUPDSSER_DIAG_D		(1U << 20)	/* disparity error */
-#define	SUPDSSER_DIAG_B		(1U << 19)	/* not implemented */
-#define	SUPDSSER_DIAG_W		(1U << 18)	/* comm wake */
-#define	SUPDSSER_DIAG_I		(1U << 17)	/* not implemented */
-#define	SUPDSSER_DIAG_N		(1U << 16)	/* PHY RDY state change */
-#define	SUPDSSER_ERR_E		(1U << 11)	/* internal error */
-#define	SUPDSSER_ERR_P		(1U << 10)	/* protocol error */
-#define	SUPDSSER_ERR_C		(1U << 9)	/* non-recovered comm. */
-#define	SUPDSSER_ERR_T		(1U << 8)	/* non-recovered TDIE */
-#define	SUPDSSER_ERR_M		(1U << 1)	/* recovered comm. */
-#define	SUPDSSER_ERR_I		(1U << 0)	/* not implemented */
-
-#define	ARTISEA_SUPDSSCR	0x008	/* DPA SATA SControl register */
-#define	SUPDSSCR_IPM_ANY	(0 << 8)	/* no IPM mode restrictions */
-#define	SUPDSSCR_IPM_NO_PARTIAL	(1U << 8)	/* no PARTIAL mode */
-#define	SUPDSSCR_IPM_NO_SLUMBER	(2U << 8)	/* no SLUMBER mode */
-#define	SUPDSSCR_IPM_NONE	(3U << 8)	/* no PM allowed */
-#define	SUPDSSCR_SPD_ANY	(0 << 4)	/* no speed restrictions */
-#define	SUPDSSCR_SPD_G1		(1U << 4)	/* <= Generation 1 */
-#define	SUPDSSCR_DET_NORM	(0 << 0)	/* normal operation */
-#define	SUPDSSCR_DET_INIT	(1U << 0)	/* comm. init */
-#define	SUPDSSCR_DET_DISABLE	(4U << 0)	/* disable interface */
-
-#define	ARTISEA_SUPDSDBR	0x00c	/* DPA Set Device Bits register */
-
-#define	ARTISEA_SUPDPFR		0x040	/* DPA PHY feature register */
-#define	SUPDPFR_SSCEN		(1U << 16)	/* SSC enable */
-#define	SUPDPFR_FVS		(1U << 14)	/* full voltage swing */
-
-#define	ARTISEA_SUPDBFCSR	0x044	/* DPA BIST FIS ctrl/stat register */
-#define	SUPDBFCSR_PAT_D21_5	(0 << 30)	/* D21.5s */
-#define	SUPDBFCSR_PAT_D24_3	(1U << 30)	/* D24.3s */
-#define	SUPDBFCSR_PAT_D10_2	(2U << 30)	/* D10.2 / K28.5 */
-#define	SUPDBFCSR_PAT_COUNT	(3U << 30)	/* counting */
-#define	SUPDBFCSR_CS_D21_5	(0 << 28)
-#define	SUPDBFCSR_CS_D24_3	(1U << 28)
-#define	SUPDBFCSR_CS_D10_2	(2U << 28)
-#define	SUPDBFCSR_CS_COUNT	(3U << 30)
-#define	SUPDBFCSR_CLEAR_ERRS	(1U << 25)	/* clear errors/frames */
-#define	SUPDBFCSR_CE		(1U << 24)	/* BIST check enable */
-#define	SUPDBFCSR_PE		(1U << 23)	/* BIST pattern enable */
-#define	SUPDBFCSR_K28_5		((1U << 16) |				\
-				 (1U << 8)	/* send K28.5s */
-#define	SUPDBFCSR_BIST_ACT_RX	(1U << 15)	/* BIST Act. FIS was rx'd */
-#define	SUPDBFCSR_BIST_ACT_RX_TO (1U << 14)	/* ...with transmit-only */
-#define	SUPDBFCSR_BIST_ACT_RX_AB (1U << 13)	/* ...with align-bypass */
-#define	SUPDBFCSR_BIST_ACT_RX_SB (1U << 12)	/* ...with scrambling-bypass */
-#define	SUPDBFCSR_BIST_ACT_RX_RT (1U << 11)	/* ...with retimed */
-#define	SUPDBFCSR_BIST_ACT_RX_P  (1U << 10)	/* ...with primitive */
-#define	SUPDBFCSR_BIST_ACT_RX_AFEL (1U << 9)	/* ...with AFE loopback */
-#define	SUPDBFCSR_BIST_ACT_TX	(1U << 7)	/* send BIST Act. FIS */
-#define	SUPDBFCSR_BIST_ACT_TX_TO (1U << 6)	/* ...with transmit-only */
-#define	SUPDBFCSR_BIST_ACT_TX_AB (1U << 5)	/* ...with align-bypass */
-#define	SUPDBFCSR_BIST_ACT_TX_SB (1U << 4)	/* ...with scrambling-bypass */
-#define	SUPDBFCSR_BIST_ACT_TX_RT (1U << 3)	/* ...with retimed */
-#define	SUPDBFCSR_BIST_ACT_TX_P  (1U << 2)	/* ...with primitive */
-#define	SUPDBFCSR_BIST_ACT_TX_AFEL (1U << 1)	/* ...with AFE loopback */
-#define	SUPDBFCSR_INIT_NE_TO	(1U << 0)	/* init. near-end tx-only */
-
-#define	ARTISEA_SUPDBER		0x048	/* DPA BIST errors register */
-
-#define	ARTISEA_SUPDBFR		0x04c	/* DPA BIST frames register */
-
-#define	ARTISEA_SUPDHBDLR	0x050	/* DPA Host BIST data low register */
-
-#define	ARTISEA_SUPDHBDHR	0x054	/* DPA Host BIST data high register */
-
-#define	ARTISEA_SUPDDBDLR	0x058	/* DPA Device BIST data low */
-
-#define	ARTISEA_SUPDDBDHR	0x05c	/* DPA Device BIST data high */
-
-#define	ARTISEA_SUPDDSFCSR	0x068	/* DPA DMA setup FIS ctrl/stat */
-#define	SUPDDSFCSR_DIR		(1U << 31)	/* First Party setup FIS
-						   word 0 direction bit
-						   (1 == tx -> rx) */
-#define	SUPDDSFCSR_INTR		(1U << 30)	/* rcvd's First Party setup
-						   FIS with I bit set */
-#define	SUPDDSFCSR_START_SETUP	(1U << 28)	/* send DMA setup FIS */
-#define	SUPDDSFCSR_EN_FP_AP	(1U << 27)	/* enab. FP DMA auto-process */
-#define	SUPDDSFCSR_ABORT_TSM	(1U << 24)	/* abort xport/link SMs */
-
-#define	ARTISEA_SUPDHDBILR	0x06c	/* DPA Host DMA Buff. Id low */
-
-#define	ARTISEA_SUPDHDBIHR	0x070	/* DPA Host DMA Buff. Id high */
-
-#define	ARTISEA_SUPDHRDR0	0x074	/* DPA Host Resvd. DWORD 0 */
-
-#define	ARTISEA_SUPDHDBOR	0x078	/* DPA Host DMA Buff. offset */
-
-#define	ARTISEA_SUPDHDTCR	0x07c	/* DPA Host DMA xfer count */
-
-#define	ARTISEA_SUPDHRDR1	0x080	/* DPA Host Resvd. DWORD 1 */
-
-#define	ARTISEA_SUPDDDBILR	0x084	/* DPA Device DMA Buff. Id low */
-
-#define	ARTISEA_SUPDDDBIHR	0x088	/* DPA Device DMA Buff. Id high */
-
-#define	ARTISEA_SUPDDRDR0	0x08c	/* DPA Device Resvd. DWORD 0 */
-
-#define	ARTISEA_SUPDDDBOR	0x090	/* DPA Device DMA Buff. offset */
-
-#define	ARTISEA_SUPDDTCR	0x094	/* DPA Device DMA xfer count */
-
-#define	ARTISEA_SUPDDRDR1	0x09c	/* DPA Device Resvd. DWORD 1 */
-
-#endif /* _DEV_PCI_PCIIDE_I31244_REG_H_ */