diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2022-06-22 22:49:11 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2022-06-22 22:49:11 +0000 |
| commit | a20552fa25eef069b6a3cc82f17856da7ad398dd (patch) | |
| tree | 53d5ec014bc22dc67e4e4e19f8cdf9e5698f9de8 /sys/dev | |
| parent | 1d2b2629ce565f49b9444b0c2892589fdd78012c (diff) | |
drm/amd/display: Read Golden Settings Table from VBIOS
From Sherry Wang
a2010538c9d25bafb35ebaff4d9eb9d0390b402b in linux 5.15.y/5.15.49
4b81dd2cc6f4f4e8cea0ed6ee8d5193a8ae14a72 in mainline linux
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c index b47830ce1bf..67a1094a0fd 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c @@ -168,9 +168,7 @@ void enc31_hw_init(struct link_encoder *enc) AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 */ - AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); - - AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); + // dmub will read AUX_DPHY_RX_CONTROL0/AUX_DPHY_TX_CONTROL from vbios table in dp_aux_init //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk |