diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2013-09-01 10:36:32 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2013-09-01 10:36:32 +0000 |
| commit | b55a7b600eec1f5498504d6c531a7419a2da048c (patch) | |
| tree | dc7719ee595440d29e8c5a43e45f5fcce0b50418 /sys/dev | |
| parent | c94aa3f427adcbae65fedc590152af09a788f1b9 (diff) | |
drm/radeon: update line buffer allocation for dce4.1/5
We need to allocate line buffer to each display when
setting up the watermarks. Failure to do so can lead
to a blank screen. This fixes blank screen problems
on dce4.1/5 asics.
from a proposed Linux patch by Alex Deucher of AMD.
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/pci/drm/radeon/evergreen.c | 27 | ||||
| -rw-r--r-- | sys/dev/pci/drm/radeon/evergreend.h | 6 |
2 files changed, 27 insertions, 6 deletions
diff --git a/sys/dev/pci/drm/radeon/evergreen.c b/sys/dev/pci/drm/radeon/evergreen.c index f0cda01f800..12d91ba0986 100644 --- a/sys/dev/pci/drm/radeon/evergreen.c +++ b/sys/dev/pci/drm/radeon/evergreen.c @@ -1,4 +1,4 @@ -/* $OpenBSD: evergreen.c,v 1.3 2013/08/26 05:15:21 jsg Exp $ */ +/* $OpenBSD: evergreen.c,v 1.4 2013/09/01 10:36:31 jsg Exp $ */ /* * Copyright 2010 Advanced Micro Devices, Inc. * @@ -731,7 +731,8 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, struct drm_display_mode *mode, struct drm_display_mode *other_mode) { - u32 tmp; + u32 tmp, buffer_alloc, i; + u32 pipe_offset = radeon_crtc->crtc_id * 0x20; /* * Line Buffer Setup * There are 3 line buffers, each one shared by 2 display controllers. @@ -754,18 +755,34 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, * non-linked crtcs for maximum line buffer allocation. */ if (radeon_crtc->base.enabled && mode) { - if (other_mode) + if (other_mode) { tmp = 0; /* 1/2 */ - else + buffer_alloc = 1; + } else { tmp = 2; /* whole */ - } else + buffer_alloc = 2; + } + } else { tmp = 0; + buffer_alloc = 0; + } /* second controller of the pair uses second half of the lb */ if (radeon_crtc->crtc_id % 2) tmp += 4; WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); + if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { + WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, + DMIF_BUFFERS_ALLOCATED(buffer_alloc)); + for (i = 0; i < rdev->usec_timeout; i++) { + if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & + DMIF_BUFFERS_ALLOCATED_COMPLETED) + break; + udelay(1); + } + } + if (radeon_crtc->base.enabled && mode) { switch (tmp) { case 0: diff --git a/sys/dev/pci/drm/radeon/evergreend.h b/sys/dev/pci/drm/radeon/evergreend.h index c12a290225b..659f36ca5a4 100644 --- a/sys/dev/pci/drm/radeon/evergreend.h +++ b/sys/dev/pci/drm/radeon/evergreend.h @@ -1,4 +1,4 @@ -/* $OpenBSD: evergreend.h,v 1.1 2013/08/12 04:11:53 jsg Exp $ */ +/* $OpenBSD: evergreend.h,v 1.2 2013/09/01 10:36:31 jsg Exp $ */ /* * Copyright 2010 Advanced Micro Devices, Inc. * @@ -761,6 +761,10 @@ # define LATENCY_LOW_WATERMARK(x) ((x) << 0) # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) +#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 +# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) +# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) + #define IH_RB_CNTL 0x3e00 # define IH_RB_ENABLE (1 << 0) # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |