macros describing necessary bits on newer chips.

just extra cruft, it doesnt change anything that already exists so it cant
(and empirically doesnt) change existing chip support.

1 files changed, 95 insertions, 2 deletions

diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index e5146f89915..f01ec1eeb75 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_bgereg.h,v 1.104 2011/02/15 19:49:47 robert Exp $	*/
+/*	$OpenBSD: if_bgereg.h,v 1.105 2013/01/10 00:47:39 dlg Exp $	*/
 
 /*
  * Copyright (c) 2001 Wind River Systems
@@ -92,6 +92,7 @@
 #define BGE_UNMAPPED_END		0x00001FFF
 #define BGE_DMA_DESCRIPTORS		0x00002000
 #define BGE_DMA_DESCRIPTORS_END		0x00003FFF
+#define BGE_SEND_RING_5717		0x00004000
 #define BGE_SEND_RING_1_TO_4		0x00004000
 #define BGE_SEND_RING_1_TO_4_END	0x00005FFF
 
@@ -106,6 +107,8 @@
 #define BGE_BUFFPOOL_2_END		0x00017FFF
 #define BGE_BUFFPOOL_3			0x00018000 /* or expansion ROM */
 #define BGE_BUFFPOOL_3_END		0x0001FFFF
+#define BGE_STD_RX_RINGS_5717		0x00040000
+#define BGE_JUMBO_RX_RINGS_5717		0x00044400
 
 /* Mappings for external SSRAM configurations */
 #define BGE_SEND_RING_5_TO_6		0x00006000
@@ -306,6 +309,12 @@
 #define BGE_CHIPID_BCM5906_A2		0xc002
 #define BGE_CHIPID_BCM57780_A0		0x57780000
 #define BGE_CHIPID_BCM57780_A1		0x57780001
+#define BGE_CHIPID_BCM5717_A0		0x05717000
+#define BGE_CHIPID_BCM5717_B0		0x05717100
+#define BGE_CHIPID_BCM5719_A0		0x05719000
+#define BGE_CHIPID_BCM5720_A0		0x05720000
+#define BGE_CHIPID_BCM57765_A0		0x57785000
+#define BGE_CHIPID_BCM57765_B0		0x57785100
 
 /* shorthand one */
 #define BGE_ASICREV(x)			((x) >> 12)
@@ -328,6 +337,8 @@
 #define BGE_ASICREV_BCM5785		0x5785
 #define BGE_ASICREV_BCM57780		0x57780
 #define BGE_ASICREV_BCM5717		0x5717
+#define BGE_ASICREV_BCM5719		0x5719
+#define BGE_ASICREV_BCM5720		0x5720
 #define BGE_ASICREV_BCM57765		0x57785
 
 /* chip revisions */
@@ -346,6 +357,7 @@
 
 /* PCI DMA Read/Write Control register */
 #define BGE_PCIDMARWCTL_MINDMA		0x000000FF
+#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT	0x00000001
 #define BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
 #define BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x0000C000
@@ -363,6 +375,9 @@
 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x)	((x) << 24)
 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x)	((x) << 28)
 
+#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA	0x00000080
+#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK	0x00000380
+
 #define BGE_PCI_READ_BNDRY_DISABLE	0x00000000
 #define BGE_PCI_READ_BNDRY_16BYTES	0x00000100
 #define BGE_PCI_READ_BNDRY_32BYTES	0x00000200
@@ -718,6 +733,9 @@
 #define BGE_TXMODE_FLOWCTL_ENABLE	0x00000010
 #define BGE_TXMODE_BIGBACKOFF_ENABLE	0x00000020
 #define BGE_TXMODE_LONGPAUSE_ENABLE	0x00000040
+#define BGE_TXMODE_MBUF_LOCKUP_FIX	0x00000100
+#define BGE_TXMODE_JMB_FRM_LEN		0x00400000
+#define BGE_TXMODE_CNT_DN_MODE		0x00800000
 
 /* Transmit MAC status register */
 #define BGE_TXSTAT_RX_XOFFED		0x00000001
@@ -731,6 +749,8 @@
 #define BGE_TXLEN_SLOTTIME		0x000000FF
 #define BGE_TXLEN_IPG			0x00000F00
 #define BGE_TXLEN_CRS			0x00003000
+#define BGE_TXLEN_JMB_FRM_LEN_MSK	0x00FF0000
+#define BGE_TXLEN_CNT_DN_VAL_MSK	0xFF000000
 
 /* Receive MAC mode register */
 #define BGE_RXMODE_RESET		0x00000001
@@ -907,9 +927,10 @@
 #define BGE_SGDIGCFG_AUTO		0x80000000
 
 /* SGDIG status (not documented) */
+#define BGE_SGDIGSTS_DONE		0x00000002
+#define BGE_SGDIGSTS_IS_SERDES		0x00000100
 #define BGE_SGDIGSTS_PAUSE_CAP		0x00080000
 #define BGE_SGDIGSTS_ASYM_PAUSE		0x00100000
-#define BGE_SGDIGSTS_DONE		0x00000002
 
 /* MI communication register */
 #define BGE_MICOMM_DATA			0x0000FFFF
@@ -1291,6 +1312,55 @@
 /* Receive List Selector Status register */
 #define BGE_RXLSSTAT_ERROR		0x00000004
 
+#define BGE_CPMU_CTRL			0x3600
+#define BGE_CPMU_LSPD_10MB_CLK		0x3604
+#define BGE_CPMU_LSPD_1000MB_CLK	0x360C
+#define BGE_CPMU_LNK_AWARE_PWRMD	0x3610
+#define BGE_CPMU_HST_ACC		0x361C
+#define BGE_CPMU_CLCK_ORIDE		0x3624
+#define BGE_CPMU_CLCK_STAT		0x3630
+#define BGE_CPMU_MUTEX_REQ		0x365C
+#define BGE_CPMU_MUTEX_GNT		0x3660
+#define BGE_CPMU_PHY_STRAP		0x3664
+
+/* Central Power Management Unit (CPMU) register */
+#define BGE_CPMU_CTRL_LINK_IDLE_MODE	0x00000200
+#define BGE_CPMU_CTRL_LINK_AWARE_MODE	0x00000400
+#define BGE_CPMU_CTRL_LINK_SPEED_MODE	0x00004000
+#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY	0x00010000
+
+/* Link Speed 10MB/No Link Power Mode Clock Policy register */
+#define BGE_CPMU_LSPD_10MB_MACCLK_MASK	0x001F0000
+#define BGE_CPMU_LSPD_10MB_MACCLK_6_25	0x00130000
+
+/* Link Speed 1000MB Power Mode Clock Policy register */
+#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5	0x00000000
+#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5	0x00110000
+#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK	0x001F0000
+
+/* Link Aware Power Mode Clock Policy register */
+#define BGE_CPMU_LNK_AWARE_MACCLK_MASK	0x001F0000
+#define BGE_CPMU_LNK_AWARE_MACCLK_6_25	0x00130000
+
+#define BGE_CPMU_HST_ACC_MACCLK_MASK	0x001F0000
+#define BGE_CPMU_HST_ACC_MACCLK_6_25	0x00130000
+
+/* Clock Speed Override Policy register */
+#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
+
+/* CPMU Clock Status register */
+#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK	0x001F0000
+#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5	0x00000000
+#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5	0x00110000
+#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25	0x00130000
+
+/* CPMU Mutex Request register */
+#define BGE_CPMU_MUTEX_REQ_DRIVER	0x00001000
+#define BGE_CPMU_MUTEX_GNT_DRIVER	0x00001000
+
+/* CPMU GPHY Strap register */
+#define BGE_CPMU_PHY_STRAP_IS_SERDES	0x00000020
+
 /*
  * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
  */
@@ -1490,6 +1560,7 @@
 #define BGE_BMANMODE_ATTN		0x00000004
 #define BGE_BMANMODE_TESTMODE		0x00000008
 #define BGE_BMANMODE_LOMBUF_ATTN	0x00000010
+#define BGE_BMANMODE_NO_TX_UNDERRUN	0x80000000
 
 /* Buffer manager status register */
 #define BGE_BMANSTAT_ERRO		0x00000004
@@ -1501,6 +1572,8 @@
  */
 #define BGE_RDMA_MODE			0x4800
 #define BGE_RDMA_STATUS			0x4804
+#define BGE_RDMA_RSRVCTRL		0x4900
+#define BGE_RDMA_LSO_CRPTEN_CTRL	0x4910
 
 /* Read DMA mode register */
 #define BGE_RDMAMODE_RESET		0x00000001
@@ -1520,6 +1593,9 @@
 #define BGE_RDMAMODE_FIFO_SIZE_128	0x00020000
 #define BGE_RDMAMODE_FIFO_LONG_BURST	0x00030000
 #define BGE_RDMAMODE_MULT_DMA_RD_DIS	0x01000000
+#define BGE_RDMAMODE_TSO4_ENABLE	0x08000000
+#define BGE_RDMAMODE_TSO6_ENABLE	0x10000000
+#define BGE_RDMAMODE_H2BNC_VLAN_DET	0x20000000
 
 /* Read DMA status register */
 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
@@ -1531,6 +1607,19 @@
 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_RDMASTAT_LOCWRITE_TOOBIG	0x00000200
 
+/* Read DMA Reserved Control register */
+#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX	0x00000004
+#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K	0x00000C00
+#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K	0x000C0000
+#define BGE_RDMA_RSRVCTRL_TXMRGN_320B	0x28000000
+#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK	0x00000FF0
+#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK	0x000FF000
+#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK	0xFFE00000
+
+#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512	0x00020000
+#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K	0x00030000
+#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K	0x000C0000
+
 /*
  * Write DMA control registers
  */
@@ -1939,14 +2028,18 @@
 #define BGE_MODECTL_WORDSWAP_NONFRAME	0x00000004
 #define BGE_MODECTL_BYTESWAP_DATA	0x00000010
 #define BGE_MODECTL_WORDSWAP_DATA	0x00000020
+#define BGE_MODECTL_BYTESWAP_B2HRX_DATA	0x00000040
+#define BGE_MODECTL_WORDSWAP_B2HRX_DATA	0x00000080
 #define BGE_MODECTL_NO_FRAME_CRACKING	0x00000200
 #define BGE_MODECTL_NO_RX_CRC		0x00000400
 #define BGE_MODECTL_RX_BADFRAMES	0x00000800
 #define BGE_MODECTL_NO_TX_INTR		0x00002000
 #define BGE_MODECTL_NO_RX_INTR		0x00004000
 #define BGE_MODECTL_FORCE_PCI32		0x00008000
+#define BGE_MODECTL_B2HRX_ENABLE	0x00008000
 #define BGE_MODECTL_STACKUP		0x00010000
 #define BGE_MODECTL_HOST_SEND_BDS	0x00020000
+#define BGE_MODECTL_HTX2B_ENABLE	0x00040000
 #define BGE_MODECTL_TX_NO_PHDR_CSUM	0x00100000
 #define BGE_MODECTL_RX_NO_PHDR_CSUM	0x00800000
 #define BGE_MODECTL_TX_ATTN_INTR	0x01000000