Add support for i.MX8M PWM clocks.

2 files changed, 74 insertions, 1 deletions

diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index 47e057783d9..0074ea58061 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.13 2019/03/13 09:41:12 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.14 2019/03/13 09:49:46 patrick Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -228,6 +228,7 @@ uint32_t imxccm_get_uartclk(struct imxccm_softc *);
 uint32_t imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t);
+uint32_t imxccm_imx8mq_pwm(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_uart(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_usdhc(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_usb(struct imxccm_softc *sc, uint32_t);
@@ -661,6 +662,33 @@ imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t idx)
 }
 
 uint32_t
+imxccm_imx8mq_pwm(struct imxccm_softc *sc, uint32_t idx)
+{
+	uint32_t mux;
+
+	if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+		return 0;
+
+	mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+	mux >>= sc->sc_muxs[idx].shift;
+	mux &= sc->sc_muxs[idx].mask;
+
+	switch (mux) {
+	case 0:
+		return clock_get_frequency(sc->sc_node, "osc_25m");
+	case 1:
+		return 100 * 1000 * 1000; /* sys1_pll_100m */
+	case 2:
+		return 160 * 1000 * 1000; /* sys1_pll_160m */
+	case 3:
+		return 40 * 1000 * 1000; /* sys1_pll_40m */
+	default:
+		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+		return 0;
+	}
+}
+
+uint32_t
 imxccm_imx8mq_uart(struct imxccm_softc *sc, uint32_t idx)
 {
 	uint32_t mux;
@@ -1064,6 +1092,11 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 		case IMX8MQ_CLK_ECSPI2_SRC:
 		case IMX8MQ_CLK_ECSPI3_SRC:
 			return imxccm_imx8mq_ecspi(sc, idx);
+		case IMX8MQ_CLK_PWM1_SRC:
+		case IMX8MQ_CLK_PWM2_SRC:
+		case IMX8MQ_CLK_PWM3_SRC:
+		case IMX8MQ_CLK_PWM4_SRC:
+			return imxccm_imx8mq_pwm(sc, idx);
 		}
 	} else if (sc->sc_gates == imx7d_gates) {
 		switch (idx) {
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index 145189e1707..ea865f6bd96 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -391,6 +391,22 @@ struct imxccm_mux imx7d_muxs[] = {
 #define IMX8MQ_CLK_ECSPI2_CG		0x134
 #define IMX8MQ_CLK_ECSPI2_PRE_DIV	0x135
 #define IMX8MQ_CLK_ECSPI2_DIV		0x136
+#define IMX8MQ_CLK_PWM1_SRC		0x137
+#define IMX8MQ_CLK_PWM1_CG		0x138
+#define IMX8MQ_CLK_PWM1_PRE_DIV		0x139
+#define IMX8MQ_CLK_PWM1_DIV		0x13a
+#define IMX8MQ_CLK_PWM2_SRC		0x13b
+#define IMX8MQ_CLK_PWM2_CG		0x13c
+#define IMX8MQ_CLK_PWM2_PRE_DIV		0x13d
+#define IMX8MQ_CLK_PWM2_DIV		0x13e
+#define IMX8MQ_CLK_PWM3_SRC		0x13f
+#define IMX8MQ_CLK_PWM3_CG		0x140
+#define IMX8MQ_CLK_PWM3_PRE_DIV		0x141
+#define IMX8MQ_CLK_PWM3_DIV		0x142
+#define IMX8MQ_CLK_PWM4_SRC		0x143
+#define IMX8MQ_CLK_PWM4_CG		0x144
+#define IMX8MQ_CLK_PWM4_PRE_DIV		0x145
+#define IMX8MQ_CLK_PWM4_DIV		0x146
 #define IMX8MQ_CLK_PCIE2_CTRL_SRC	0x17b
 #define IMX8MQ_CLK_PCIE2_CTRL_CG	0x17c
 #define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV	0x17d
@@ -417,6 +433,10 @@ struct imxccm_mux imx7d_muxs[] = {
 #define IMX8MQ_CLK_I2C4_ROOT		0x195
 #define IMX8MQ_CLK_PCIE1_ROOT		0x197
 #define IMX8MQ_CLK_PCIE2_ROOT		0x198
+#define IMX8MQ_CLK_PWM1_ROOT		0x199
+#define IMX8MQ_CLK_PWM2_ROOT		0x19a
+#define IMX8MQ_CLK_PWM3_ROOT		0x19b
+#define IMX8MQ_CLK_PWM4_ROOT		0x19c
 #define IMX8MQ_CLK_UART1_ROOT		0x1a4
 #define IMX8MQ_CLK_UART2_ROOT		0x1a5
 #define IMX8MQ_CLK_UART3_ROOT		0x1a6
@@ -452,6 +472,10 @@ struct imxccm_gate imx8mq_gates[] = {
 	[IMX8MQ_CLK_USB_PHY_REF_CG] = { 0xb180, 14, IMX8MQ_CLK_USB_PHY_REF_SRC },
 	[IMX8MQ_CLK_ECSPI1_CG] = { 0xb280, 14, IMX8MQ_CLK_ECSPI1_SRC },
 	[IMX8MQ_CLK_ECSPI2_CG] = { 0xb300, 14, IMX8MQ_CLK_ECSPI2_SRC },
+	[IMX8MQ_CLK_PWM1_CG] = { 0xb380, 14, IMX8MQ_CLK_PWM1_SRC },
+	[IMX8MQ_CLK_PWM2_CG] = { 0xb400, 14, IMX8MQ_CLK_PWM2_SRC },
+	[IMX8MQ_CLK_PWM3_CG] = { 0xb480, 14, IMX8MQ_CLK_PWM3_SRC },
+	[IMX8MQ_CLK_PWM4_CG] = { 0xb500, 14, IMX8MQ_CLK_PWM4_SRC },
 	[IMX8MQ_CLK_PCIE2_CTRL_CG] = { 0xc000, 14, IMX8MQ_CLK_PCIE2_CTRL_SRC },
 	[IMX8MQ_CLK_PCIE2_PHY_CG] = { 0xc080, 14, IMX8MQ_CLK_PCIE2_PHY_SRC },
 	[IMX8MQ_CLK_PCIE2_AUX_CG] = { 0xc100, 14, IMX8MQ_CLK_PCIE2_AUX_SRC },
@@ -466,6 +490,10 @@ struct imxccm_gate imx8mq_gates[] = {
 	[IMX8MQ_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MQ_CLK_I2C4_DIV },
 	[IMX8MQ_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MQ_CLK_PCIE1_CTRL_DIV },
 	[IMX8MQ_CLK_PCIE2_ROOT] = { 0x4640, 0, IMX8MQ_CLK_PCIE2_CTRL_DIV },
+	[IMX8MQ_CLK_PWM1_ROOT] = { 0x4280, 0, IMX8MQ_CLK_PWM1_DIV },
+	[IMX8MQ_CLK_PWM2_ROOT] = { 0x4290, 0, IMX8MQ_CLK_PWM2_DIV },
+	[IMX8MQ_CLK_PWM3_ROOT] = { 0x42a0, 0, IMX8MQ_CLK_PWM3_DIV },
+	[IMX8MQ_CLK_PWM4_ROOT] = { 0x42b0, 0, IMX8MQ_CLK_PWM4_DIV },
 	[IMX8MQ_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MQ_CLK_UART1_DIV },
 	[IMX8MQ_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MQ_CLK_UART2_DIV },
 	[IMX8MQ_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MQ_CLK_UART3_DIV },
@@ -524,6 +552,14 @@ struct imxccm_divider imx8mq_divs[] = {
 	[IMX8MQ_CLK_ECSPI1_DIV] = { 0xb280, 0, 0x3f, IMX8MQ_CLK_ECSPI1_PRE_DIV },
 	[IMX8MQ_CLK_ECSPI2_PRE_DIV] = { 0xb300, 16, 0x7, IMX8MQ_CLK_ECSPI2_CG },
 	[IMX8MQ_CLK_ECSPI2_DIV] = { 0xb300, 0, 0x3f, IMX8MQ_CLK_ECSPI2_PRE_DIV },
+	[IMX8MQ_CLK_PWM1_PRE_DIV] = { 0xb380, 16, 0x7, IMX8MQ_CLK_PWM1_CG },
+	[IMX8MQ_CLK_PWM1_DIV] = { 0xb380, 0, 0x3f, IMX8MQ_CLK_PWM1_PRE_DIV },
+	[IMX8MQ_CLK_PWM2_PRE_DIV] = { 0xb400, 16, 0x7, IMX8MQ_CLK_PWM2_CG },
+	[IMX8MQ_CLK_PWM2_DIV] = { 0xb400, 0, 0x3f, IMX8MQ_CLK_PWM2_PRE_DIV },
+	[IMX8MQ_CLK_PWM3_PRE_DIV] = { 0xb480, 16, 0x7, IMX8MQ_CLK_PWM3_CG },
+	[IMX8MQ_CLK_PWM3_DIV] = { 0xb480, 0, 0x3f, IMX8MQ_CLK_PWM3_PRE_DIV },
+	[IMX8MQ_CLK_PWM4_PRE_DIV] = { 0xb500, 16, 0x7, IMX8MQ_CLK_PWM4_CG },
+	[IMX8MQ_CLK_PWM4_DIV] = { 0xb500, 0, 0x3f, IMX8MQ_CLK_PWM4_PRE_DIV },
 	[IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = { 0xc000, 16, 0x7, IMX8MQ_CLK_PCIE2_CTRL_CG },
 	[IMX8MQ_CLK_PCIE2_CTRL_DIV] = { 0xc000, 0, 0x3f, IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV },
 	[IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = { 0xc080, 16, 0x7, IMX8MQ_CLK_PCIE2_PHY_CG },
@@ -558,6 +594,10 @@ struct imxccm_mux imx8mq_muxs[] = {
 	[IMX8MQ_CLK_USB_PHY_REF_SRC] = { 0xb180, 24, 0x7 },
 	[IMX8MQ_CLK_ECSPI1_SRC] = { 0xb280, 24, 0x7 },
 	[IMX8MQ_CLK_ECSPI2_SRC] = { 0xb300, 24, 0x7 },
+	[IMX8MQ_CLK_PWM1_SRC] = { 0xb380, 24, 0x7 },
+	[IMX8MQ_CLK_PWM2_SRC] = { 0xb400, 24, 0x7 },
+	[IMX8MQ_CLK_PWM3_SRC] = { 0xb480, 24, 0x7 },
+	[IMX8MQ_CLK_PWM4_SRC] = { 0xb500, 24, 0x7 },
 	[IMX8MQ_CLK_PCIE2_CTRL_SRC] = { 0xc000, 24, 0x7 },
 	[IMX8MQ_CLK_PCIE2_PHY_SRC] = { 0xc080, 24, 0x7 },
 	[IMX8MQ_CLK_PCIE2_AUX_SRC] = { 0xc100, 24, 0x7 },