add support for the 82562E[MT] phys (These are essentially 82555's will

all support for T4 gone).  There are some register definition conflicts
(SCR), but that is qualified by the presence of T4 support.

2 files changed, 43 insertions, 9 deletions

diff --git a/sys/dev/mii/inphy.c b/sys/dev/mii/inphy.c
index 2d6b5c9b614..1f736bde779 100644
--- a/sys/dev/mii/inphy.c
+++ b/sys/dev/mii/inphy.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: inphy.c,v 1.6 2000/08/26 20:04:17 nate Exp $	*/
+/*	$OpenBSD: inphy.c,v 1.7 2001/04/17 01:19:21 jason Exp $	*/
 /*	$NetBSD: inphy.c,v 1.18 2000/02/02 23:34:56 thorpej Exp $	*/
 
 /*-
@@ -112,9 +112,14 @@ inphymatch(parent, match, aux)
 {
 	struct mii_attach_args *ma = aux;
 
-	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_INTEL &&
-	    MII_MODEL(ma->mii_id2) == MII_MODEL_INTEL_I82555)
-		return (10);
+	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_INTEL) {
+		switch (MII_MODEL(ma->mii_id2)) {
+		case MII_MODEL_INTEL_I82555:
+		case MII_MODEL_INTEL_I82562EM:
+		case MII_MODEL_INTEL_I82562ET:
+			return (10);
+		}
+	}
 
 	return (0);
 }
@@ -127,9 +132,23 @@ inphyattach(parent, self, aux)
 	struct mii_softc *sc = (struct mii_softc *)self;
 	struct mii_attach_args *ma = aux;
 	struct mii_data *mii = ma->mii_data;
+	char *mstr;
 
-	printf(": %s, rev. %d\n", MII_STR_INTEL_I82555,
-	    MII_REV(ma->mii_id2));
+	switch (MII_MODEL(ma->mii_id2)) {
+	case MII_MODEL_INTEL_I82555:
+		mstr = MII_STR_INTEL_I82555;
+		break;
+	case MII_MODEL_INTEL_I82562EM:
+		mstr = MII_STR_INTEL_I82562EM;
+		break;
+	case MII_MODEL_INTEL_I82562ET:
+		mstr = MII_STR_INTEL_I82562ET;
+		break;
+	default:
+		mstr = "unknown inphy";
+		break;
+	}
+	printf(": %s, rev. %d\n", mstr, MII_REV(ma->mii_id2));
 
 	sc->mii_inst = mii->mii_instance;
 	sc->mii_phy = ma->mii_phyno;
@@ -244,7 +263,7 @@ inphy_status(sc)
 			return;
 		}
 		scr = PHY_READ(sc, MII_INPHY_SCR);
-		if (scr & SCR_T4)
+		if ((bmsr & BMSR_100T4) && (scr & SCR_T4))
 			mii->mii_media_active |= IFM_100_T4;
 		else if (scr & SCR_S100)
 			mii->mii_media_active |= IFM_100_TX;
diff --git a/sys/dev/mii/inphyreg.h b/sys/dev/mii/inphyreg.h
index 14ba829e51f..96a428130ba 100644
--- a/sys/dev/mii/inphyreg.h
+++ b/sys/dev/mii/inphyreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: inphyreg.h,v 1.2 1999/06/22 16:12:05 jason Exp $	*/
+/*	$OpenBSD: inphyreg.h,v 1.3 2001/04/17 01:19:22 jason Exp $	*/
 /*	$NetBSD: inphyreg.h,v 1.1 1998/08/11 00:00:28 thorpej Exp $	*/
 
 /*-
@@ -42,7 +42,10 @@
 #define	_DEV_MII_INPHYREG_H_
 
 /*
- * Intel 82555 registers.
+ * Intel 82555, 82562EM, and 82562ET registers.
+ * Note that the 82562 chips are basically 82555 with a few extra registers
+ * and all of the 100baseT4 support removed.  Bits in the SCR register do
+ * overlap however.
  */
 
 #define	MII_INPHY_SCR		0x10	/* Status and Control */
@@ -56,6 +59,9 @@
 #define	SCR_T4			0x0004	/* autoneg resulted in 100baseT4 */
 #define	SCR_S100		0x0002	/* autoneg resulted in 100baseTX */
 #define	SCR_FDX			0x0001	/* autoneg resulted in full-duplex */
+/* 82562E[MT] only */
+#define	SCR_PHYADDR_M		0x007c	/* phy address mask */
+#define	SCR_PHYADDR_S		2	/* shift to normalize */
 
 #define	MII_INPHY_SCTRL		0x11	/* Special Control Bit */
 #define	SCTRL_SCRBYPASS		0x8000	/* scrambler bypass */
@@ -73,6 +79,15 @@
 #define	SCTRL_EXTSQUELCH	0x0004	/* extended sequelch enable */
 #define	SCTRL_LINKINTDIS	0x0002	/* link integrity disable */
 #define	SCTRL_JABBERDIS		0x0001	/* jabber disabled */
+/* 82562E[MT] only */
+#define	SCTRL_SRE		0x0400	/* symbol error enable */
+#define SCTRL_FORCEPOL		0x0020	/* force polarity, 0 = normal */
+
+/* 82562E[MT] only */
+#define	MII_INPHY_PHYADDR	0x12	/* phy address register, 82562 only */
+
+/* 82562E[MT] only */
+#define	MII_INPHY_100TXFCC	0x13	/* false carrier counter */
 
 #define	MII_INPHY_100TXRDC	0x14	/* 100baseTX Receive Disconnect Cntr */