diff options
author | Marcus Glocker <mglocker@cvs.openbsd.org> | 2006-11-17 20:49:28 +0000 |
---|---|---|
committer | Marcus Glocker <mglocker@cvs.openbsd.org> | 2006-11-17 20:49:28 +0000 |
commit | 1ac6e4041663e723ed2afc95b726d3e8ce340bca (patch) | |
tree | e19f848d55db35d0e810f9b3acf4382e14aca7a0 /sys/dev | |
parent | f0c2715c84dc19de756de1273dc0fb2a101e943f (diff) |
Minor cleanup.
Diffstat (limited to 'sys/dev')
-rw-r--r-- | sys/dev/ic/bcwreg.h | 48 | ||||
-rw-r--r-- | sys/dev/ic/bcwvar.h | 43 |
2 files changed, 43 insertions, 48 deletions
diff --git a/sys/dev/ic/bcwreg.h b/sys/dev/ic/bcwreg.h index 279ecc25ff2..ba385b91e01 100644 --- a/sys/dev/ic/bcwreg.h +++ b/sys/dev/ic/bcwreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bcwreg.h,v 1.1 2006/11/17 18:58:31 mglocker Exp $ */ +/* $OpenBSD: bcwreg.h,v 1.2 2006/11/17 20:49:27 mglocker Exp $ */ /* * Copyright (c) 2006 Jon Simola <jsimola@gmail.com> @@ -78,10 +78,9 @@ #define SBIV_ENET0 0x02 /* enable for enet 0 */ #define SBIV_ENET1 0x40 /* enable for enet 1 */ - /* Host Interface Registers */ -#define BCW_DEVCTL 0x0000 /* device control */ +#define BCW_DEVCTL 0x0000 /* device control */ /* device control bits */ #define BCW_DC_IP 0x00000400 /* internal phy present */ #define BCW_DC_ER 0x00008000 /* ephy reset */ @@ -128,13 +127,13 @@ #define RS_ERROR 0xf0000 /* had an error */ /* Ethernet MAC control registers */ -#define BCW_RX_CTL 0x0400 /* receive config */ +#define BCW_RX_CTL 0x0400 /* receive config */ /* config bits */ #define ERC_DB 0x00000001 /* disable broadcast */ #define ERC_AM 0x00000002 /* rx all multicast */ #define ERC_PE 0x00000008 /* promiscuous enable */ -#define BCW_RX_MAX 0x0404 /* max packet length */ +#define BCW_RX_MAX 0x0404 /* max packet length */ #define BCW_TX_MAX 0x0408 #define BCW_MI_CTL 0x0410 #define BCW_MI_COMM 0x0414 @@ -142,9 +141,9 @@ /* mii status bits */ #define BCW_MIINTR 0x00000001 /* mii mdio interrupt */ -#define BCW_FILT_LOW 0x0420 /* mac low 4 bytes */ -#define BCW_FILT_HI 0x0424 /* mac hi 2 bytes */ -#define BCW_FILT_CTL 0x0428 /* packet filter ctrl */ +#define BCW_FILT_LOW 0x0420 /* mac low 4 bytes */ +#define BCW_FILT_HI 0x0424 /* mac hi 2 bytes */ +#define BCW_FILT_CTL 0x0428 /* packet filter ctrl */ #define BCW_ENET_CTL 0x042C /* bits for mac control */ #define EC_EE 0x00000001 /* emac enable */ @@ -154,7 +153,7 @@ #define BCW_TX_CTL 0x0430 /* bits for transmit control */ #define EXC_FD 0x00000001 /* full duplex */ -#define BCW_TX_WATER 0x0434 /* tx watermark */ +#define BCW_TX_WATER 0x0434 /* tx watermark */ /* statistics counters */ #define BCW_RX_PKTS 0x058C @@ -163,12 +162,12 @@ #define BCW_SBIMSTATE 0x0f90 #define BCW_SBTMSTATELOW 0x0f98 #define BCW_SBTMSTATEHI 0x0f9C -#define SBTML_RESET 0x1 /* reset */ -#define SBTML_REJ 0x6 /* reject */ -#define SBTML_CLK 0x10000 /* clock enable */ +#define SBTML_RESET 0x1 /* reset */ +#define SBTML_REJ 0x6 /* reject */ +#define SBTML_CLK 0x10000 /* clock enable */ #define SBTML_FGC 0x20000 /* force gated clocks on */ -#define SBTML_80211FLAG 0x40000 /* core specific flag */ -#define SBTML_80211PHY 0x20000000 /* Attach PHY */ +#define SBTML_80211FLAG 0x40000 /* core specific flag */ +#define SBTML_80211PHY 0x20000000 /* Attach PHY */ #define SBTMH_BUSY 0x4 #define SBIM_MAGIC_ERRORBITS 0x60000 @@ -200,17 +199,17 @@ #define BCW_SHM_DATA 0x164 /* Data - 32bit */ #define BCW_SHM_DATALOW 0x164 /* Data Low - 16bit */ #define BCW_SHM_DATAHIGH 0x166 /* Data High - 16 bit */ -#define BCW_SHM_CONTROL_SHARED 0x0001 /* Select SHM Routing shared memory */ -#define BCW_SHM_CONTROL_80211 0x0002 /* Select 80211 settings */ -#define BCW_SHM_CONTROL_PCM 0x0003 /* Select PCM data */ -#define BCW_SHM_CONTROL_HWMAC 0x0004 /* Security Hardware MAC Address list */ -#define BCW_SHM_CONTROL_MCODE 0x0300 /* Microcode */ -#define BCW_SHM_CONTROL_INIMCODE 0x0301 /* Initial Value Microcode? */ +#define BCW_SHM_CONTROL_SHARED 0x0001 /* Select SHM Routing shared memory */ +#define BCW_SHM_CONTROL_80211 0x0002 /* Select 80211 settings */ +#define BCW_SHM_CONTROL_PCM 0x0003 /* Select PCM data */ +#define BCW_SHM_CONTROL_HWMAC 0x0004 /* Security Hardware MAC Address list */ +#define BCW_SHM_CONTROL_MCODE 0x0300 /* Microcode */ +#define BCW_SHM_CONTROL_INIMCODE 0x0301 /* Initial Value Microcode? */ /* SHM Addresses */ #define BCW_SHM_MICROCODEFLAGSLOW 0x005e /* Flags for Microcode ops */ #define BCW_SHM_MICROCODEFLAGSHIGH 0x0060 /* Flags for Microcode ops */ -/* http://bcm-specs.sipsolutions.net/MicrocodeFlagsBitfield */ -#define BCW_SHM_MICROCODEFLAGS +/* http://bcm-specs.sipsolutions.net/MicrocodeFlagsBitfield */ +#define BCW_SHM_MICROCODEFLAGS /* 0x200 DMA Register space */ /* 0x300 PIO Register space */ @@ -231,7 +230,6 @@ #define BCW_SPROM_ET0MACADDR 0x104e /* ethernet MAC */ #define BCW_SPROM_ET1MACADDR 0x1054 /* 802.11a MAC */ - #define BCW_SPROM_PA0B0 0x105e #define BCW_SPROM_PA0B1 0x1060 #define BCW_SPROM_PA0B2 0x1062 @@ -243,9 +241,6 @@ #define BCW_SPROM_ANTGAIN 0x1074 /* bits 7-0 for an A PHY bits 15-8 for B/G PHYs */ - - - #define BCW_PHY_TYPEA 0x0 /* 802.11a PHY */ #define BCW_PHY_TYPEB 0x1 /* 802.11b PHY */ #define BCW_PHY_TYPEG 0x2 /* 802.11g PHY */ @@ -274,4 +269,3 @@ #define BCW_CLR(regs, reg, mask) \ BCW_WRITE32((regs), (reg), BCW_READ32((regs), (reg)) & ~(mask)) - diff --git a/sys/dev/ic/bcwvar.h b/sys/dev/ic/bcwvar.h index 91960c11254..bd497ab93ad 100644 --- a/sys/dev/ic/bcwvar.h +++ b/sys/dev/ic/bcwvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bcwvar.h,v 1.1 2006/11/17 18:58:31 mglocker Exp $ */ +/* $OpenBSD: bcwvar.h,v 1.2 2006/11/17 20:49:27 mglocker Exp $ */ /* * Copyright (c) 2006 Jon Simola <jsimola@gmail.com> @@ -35,7 +35,6 @@ * Cliff Wright cliff@snipe444.org */ - #define BCW_MAX_RADIOS 2 struct bcw_radio { u_int16_t id; @@ -53,14 +52,15 @@ struct bcw_core { /* number of descriptors used in a ring */ #define BCW_NRXDESC 128 #define BCW_NTXDESC 128 + /* -* Mbuf pointers. We need these to keep track of the virtual addresses -* of our mbuf chains since we can only convert from physical to virtual, -* not the other way around. -* -* The chip has 6 DMA engines, looks like we only need to use one each -* for TX and RX, the others stay disabled. -*/ + * Mbuf pointers. We need these to keep track of the virtual addresses + * of our mbuf chains since we can only convert from physical to virtual, + * not the other way around. + * + * The chip has 6 DMA engines, looks like we only need to use one each + * for TX and RX, the others stay disabled. + */ struct bcw_chain_data { struct mbuf *bcw_tx_chain[BCW_NTXDESC]; struct mbuf *bcw_rx_chain[BCW_NRXDESC]; @@ -83,12 +83,14 @@ struct bcw_regs { void (*r_write32)(void *, u_int32_t, u_int32_t); void (*r_barrier)(void *, u_int32_t, u_int32_t, int); }; + /* Needs to have garbage removed */ struct bcw_softc { struct device bcw_dev; struct ieee80211com bcw_ic; struct bcw_regs bcw_regs; - int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); int (*sc_enable)(struct bcw_softc *); void (*sc_disable)(struct bcw_softc *); bus_space_tag_t bcw_btag; @@ -113,8 +115,8 @@ struct bcw_softc { u_int16_t bcw_chipid; /* Chip ID */ u_int16_t bcw_chiprev; /* Chip Revision */ u_int16_t bcw_prodid; /* Product ID */ -// struct bcw_core core[BCW_MAX_CORES]; -// struct bcw_radio radio[BCW_MAX_RADIOS]; +// struct bcw_core core[BCW_MAX_CORES]; +// struct bcw_radio radio[BCW_MAX_RADIOS]; u_int16_t bcw_phy_version; u_int16_t bcw_phy_type; u_int16_t bcw_phy_rev; @@ -154,19 +156,19 @@ int bcw_intr(void *); * Some legacy stuff from bce and iwi to make this compile */ /* transmit buffer max frags allowed */ -#define BCW_NTXFRAGS 16 +#define BCW_NTXFRAGS 16 /* ring descriptor */ struct bcw_dma_slot { - u_int32_t ctrl; + u_int32_t ctrl; u_int32_t addr; }; - -#define CTRL_BC_MASK 0x1fff /* buffer byte count */ -#define CTRL_EOT 0x10000000 /* end of descriptor table */ -#define CTRL_IOC 0x20000000 /* interrupt on completion */ -#define CTRL_EOF 0x40000000 /* end of frame */ -#define CTRL_SOF 0x80000000 /* start of frame */ + +#define CTRL_BC_MASK 0x1fff /* buffer byte count */ +#define CTRL_EOT 0x10000000 /* end of descriptor table */ +#define CTRL_IOC 0x20000000 /* interrupt on completion */ +#define CTRL_EOF 0x40000000 /* end of frame */ +#define CTRL_SOF 0x80000000 /* start of frame */ /* Packet status is returned in a pre-packet header */ struct rx_pph { @@ -213,4 +215,3 @@ static const struct ieee80211_rateset bcw_rateset_11b = { 4, { 2, 4, 11, 22 } }; static const struct ieee80211_rateset bcw_rateset_11g = { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; - |