driver for the Tigon I & Tigon II gigabit ethernet chipsets written by

Bill Paul <wpaul@freebsd.org>

5 files changed, 12468 insertions, 1 deletions

diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index 64fc753e9e3..6c0a64af8b1 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.42 1999/07/25 04:38:26 csapuntz Exp $
+#	$OpenBSD: files.pci,v 1.43 1999/07/25 16:51:58 jason Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -157,6 +157,11 @@ device	tx: ether, ifnet, ifmedia
 attach	tx at pci
 file	dev/pci/if_tx.c			tx
 
+# Alteon Tigon I & II
+device	ti: ether, ifnet, ifmedia
+attach	ti at pci
+file	dev/pci/if_ti.c			ti
+
 # NE2000-compatible PCI Ethernet cards
 attach	ne at pci with ne_pci: rtl80x9
 file	dev/pci/if_ne_pci.c		ne_pci
diff --git a/sys/dev/pci/if_ti.c b/sys/dev/pci/if_ti.c
new file mode 100644
index 00000000000..31457a67add
--- /dev/null
+++ b/sys/dev/pci/if_ti.c
@@ -0,0 +1,2442 @@
+/*	$OpenBSD: if_ti.c,v 1.1 1999/07/25 16:51:55 jason Exp $	*/
+
+/*
+ * Copyright (c) 1997, 1998, 1999
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$FreeBSD: if_ti.c,v 1.9 1999/07/06 19:23:29 des Exp $
+ */
+
+/*
+ * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
+ * Manuals, sample driver and firmware source kits are available
+ * from http://www.alteon.com/support/openkits.
+ * 
+ * Written by Bill Paul <wpaul@ctr.columbia.edu>
+ * Electrical Engineering Department
+ * Columbia University, New York City
+ */
+
+/*
+ * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
+ * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
+ * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
+ * Tigon supports hardware IP, TCP and UCP checksumming, multicast
+ * filtering and jumbo (9014 byte) frames. The hardware is largely
+ * controlled by firmware, which must be loaded into the NIC during
+ * initialization.
+ *
+ * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
+ * revision, which supports new features such as extended commands,
+ * extended jumbo receive ring desciptors and a mini receive ring.
+ *
+ * Alteon Networks is to be commended for releasing such a vast amount
+ * of development material for the Tigon NIC without requiring an NDA
+ * (although they really should have done it a long time ago). With
+ * any luck, the other vendors will finally wise up and follow Alteon's
+ * stellar example.
+ *
+ * The firmware for the Tigon 1 and 2 NICs is compiled directly into
+ * this driver by #including it as a C header file. This bloats the
+ * driver somewhat, but it's the easiest method considering that the
+ * driver code and firmware code need to be kept in sync. The source
+ * for the firmware is not provided with the FreeBSD distribution since
+ * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
+ *
+ * The following people deserve special thanks:
+ * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
+ *   for testing
+ * - Raymond Lee of Netgear, for providing a pair of Netgear
+ *   GA620 Tigon 2 boards for testing
+ * - Ulf Zimmermann, for bringing the GA260 to my attention and
+ *   convincing me to write this driver.
+ * - Andrew Gallatin for providing FreeBSD/Alpha support.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/device.h>
+#include <sys/queue.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <net/if_media.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <vm/vm.h>              /* for vtophys */
+#include <vm/pmap.h>            /* for vtophys */
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+#include <machine/bus.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/if_tireg.h>
+#include <dev/pci/ti_fw.h>
+#include <dev/pci/ti_fw2.h>
+
+#ifdef M_HWCKSUM
+/*#define TI_CSUM_OFFLOAD*/
+#endif
+
+#define bootverbose	1
+
+static int ti_probe	__P((struct device *, void *, void *));
+static void ti_attach	__P((struct device *, struct device *, void *));
+
+static void ti_txeof		__P((struct ti_softc *));
+static void ti_rxeof		__P((struct ti_softc *));
+
+static void ti_stats_update	__P((struct ti_softc *));
+static int ti_encap		__P((struct ti_softc *, struct mbuf *,
+					u_int32_t *));
+
+static int ti_intr		__P((void *));
+static void ti_start		__P((struct ifnet *));
+static int ti_ioctl		__P((struct ifnet *, u_long, caddr_t));
+static void ti_init		__P((void *));
+static void ti_init2		__P((struct ti_softc *));
+static void ti_stop		__P((struct ti_softc *));
+static void ti_watchdog		__P((struct ifnet *));
+static void ti_shutdown		__P((void *));
+static int ti_ifmedia_upd	__P((struct ifnet *));
+static void ti_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
+
+static u_int32_t ti_eeprom_putbyte	__P((struct ti_softc *, int));
+static u_int8_t	ti_eeprom_getbyte	__P((struct ti_softc *,
+						int, u_int8_t *));
+static int ti_read_eeprom	__P((struct ti_softc *, caddr_t, int, int));
+
+static void ti_add_mcast	__P((struct ti_softc *, struct ether_addr *));
+static void ti_del_mcast	__P((struct ti_softc *, struct ether_addr *));
+static void ti_setmulti		__P((struct ti_softc *));
+
+static void ti_mem		__P((struct ti_softc *, u_int32_t,
+					u_int32_t, caddr_t));
+static void ti_loadfw		__P((struct ti_softc *));
+static void ti_cmd		__P((struct ti_softc *, struct ti_cmd_desc *));
+static void ti_cmd_ext		__P((struct ti_softc *, struct ti_cmd_desc *,
+					caddr_t, int));
+static void ti_handle_events	__P((struct ti_softc *));
+static int ti_alloc_jumbo_mem	__P((struct ti_softc *));
+static void *ti_jalloc		__P((struct ti_softc *));
+static void ti_jfree		__P((caddr_t, u_int));
+#if 0
+static void ti_jref		__P((caddr_t, u_int));
+#endif
+static int ti_newbuf_std	__P((struct ti_softc *, int, struct mbuf *));
+static int ti_newbuf_mini	__P((struct ti_softc *, int, struct mbuf *));
+static int ti_newbuf_jumbo	__P((struct ti_softc *, int, struct mbuf *));
+static int ti_init_rx_ring_std	__P((struct ti_softc *));
+static void ti_free_rx_ring_std	__P((struct ti_softc *));
+static int ti_init_rx_ring_jumbo	__P((struct ti_softc *));
+static void ti_free_rx_ring_jumbo	__P((struct ti_softc *));
+static int ti_init_rx_ring_mini	__P((struct ti_softc *));
+static void ti_free_rx_ring_mini	__P((struct ti_softc *));
+static void ti_free_tx_ring	__P((struct ti_softc *));
+static int ti_init_tx_ring	__P((struct ti_softc *));
+
+static int ti_64bitslot_war	__P((struct ti_softc *));
+static int ti_chipinit		__P((struct ti_softc *));
+static int ti_gibinit		__P((struct ti_softc *));
+
+/*
+ * Send an instruction or address to the EEPROM, check for ACK.
+ */
+static u_int32_t ti_eeprom_putbyte(sc, byte)
+	struct ti_softc		*sc;
+	int			byte;
+{
+	register int		i, ack = 0;
+
+	/*
+	 * Make sure we're in TX mode.
+	 */
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
+
+	/*
+	 * Feed in each bit and stobe the clock.
+	 */
+	for (i = 0x80; i; i >>= 1) {
+		if (byte & i) {
+			TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
+		} else {
+			TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
+		}
+		DELAY(1);
+		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+		DELAY(1);
+		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+	}
+
+	/*
+	 * Turn off TX mode.
+	 */
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
+
+	/*
+	 * Check for ack.
+	 */
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+	ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+
+	return(ack);
+}
+
+/*
+ * Read a byte of data stored in the EEPROM at address 'addr.'
+ * We have to send two address bytes since the EEPROM can hold
+ * more than 256 bytes of data.
+ */
+static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
+	struct ti_softc		*sc;
+	int			addr;
+	u_int8_t		*dest;
+{
+	register int		i;
+	u_int8_t		byte = 0;
+
+	EEPROM_START;
+
+	/*
+	 * Send write control code to EEPROM.
+	 */
+	if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
+		printf("%s: failed to send write command, status: %x\n",
+		    sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
+		return(1);
+	}
+
+	/*
+	 * Send first byte of address of byte we want to read.
+	 */
+	if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
+		printf("%s: failed to send address, status: %x\n",
+		    sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
+		return(1);
+	}
+	/*
+	 * Send second byte address of byte we want to read.
+	 */
+	if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
+		printf("%s: failed to send address, status: %x\n",
+		    sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
+		return(1);
+	}
+
+	EEPROM_STOP;
+	EEPROM_START;
+	/*
+	 * Send read control code to EEPROM.
+	 */
+	if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
+		printf("%s: failed to send read command, status: %x\n",
+		    sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
+		return(1);
+	}
+
+	/*
+	 * Start reading bits from EEPROM.
+	 */
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
+	for (i = 0x80; i; i >>= 1) {
+		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+		DELAY(1);
+		if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
+			byte |= i;
+		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+		DELAY(1);
+	}
+
+	EEPROM_STOP;
+
+	/*
+	 * No ACK generated for read, so just return byte.
+	 */
+
+	*dest = byte;
+
+	return(0);
+}
+
+/*
+ * Read a sequence of bytes from the EEPROM.
+ */
+static int ti_read_eeprom(sc, dest, off, cnt)
+	struct ti_softc		*sc;
+	caddr_t			dest;
+	int			off;
+	int			cnt;
+{
+	int			err = 0, i;
+	u_int8_t		byte = 0;
+
+	for (i = 0; i < cnt; i++) {
+		err = ti_eeprom_getbyte(sc, off + i, &byte);
+		if (err)
+			break;
+		*(dest + i) = byte;
+	}
+
+	return(err ? 1 : 0);
+}
+
+/*
+ * NIC memory access function. Can be used to either clear a section
+ * of NIC local memory or (if buf is non-NULL) copy data into it.
+ */
+static void ti_mem(sc, addr, len, buf)
+	struct ti_softc		*sc;
+	u_int32_t		addr, len;
+	caddr_t			buf;
+{
+	int			segptr, segsize, cnt;
+	caddr_t			ti_winbase, ptr;
+
+	segptr = addr;
+	cnt = len;
+#ifdef __i386__
+	ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW);
+#endif
+#ifdef __alpha__
+	ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
+#endif
+	ptr = buf;
+
+	while(cnt) {
+		if (cnt < TI_WINLEN)
+			segsize = cnt;
+		else
+			segsize = TI_WINLEN - (segptr % TI_WINLEN);
+		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
+		if (buf == NULL)
+			bzero((char *)ti_winbase + (segptr &
+			    (TI_WINLEN - 1)), segsize);
+		else {
+			bcopy((char *)ptr, (char *)ti_winbase +
+			    (segptr & (TI_WINLEN - 1)), segsize);
+			ptr += segsize;
+		}
+		segptr += segsize;
+		cnt -= segsize;
+	}
+
+	return;
+}
+
+/*
+ * Load firmware image into the NIC. Check that the firmware revision
+ * is acceptable and see if we want the firmware for the Tigon 1 or
+ * Tigon 2.
+ */
+static void ti_loadfw(sc)
+	struct ti_softc		*sc;
+{
+	switch(sc->ti_hwrev) {
+	case TI_HWREV_TIGON:
+		if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
+		    tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
+		    tigonFwReleaseFix != TI_FIRMWARE_FIX) {
+			printf("%s: firmware revision mismatch; want "
+			    "%d.%d.%d, got %d.%d.%d\n", sc->sc_dv.dv_xname,
+			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
+			    TI_FIRMWARE_FIX, tigonFwReleaseMajor,
+			    tigonFwReleaseMinor, tigonFwReleaseFix);
+			return;
+		}
+		ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
+		    (caddr_t)tigonFwText);
+		ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
+		    (caddr_t)tigonFwData);
+		ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
+		    (caddr_t)tigonFwRodata);
+		ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
+		ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
+		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
+		break;
+	case TI_HWREV_TIGON_II:
+		if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
+		    tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
+		    tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
+			printf("%s: firmware revision mismatch; want "
+			    "%d.%d.%d, got %d.%d.%d\n", sc->sc_dv.dv_xname,
+			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
+			    TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
+			    tigon2FwReleaseMinor, tigon2FwReleaseFix);
+			return;
+		}
+		ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
+		    (caddr_t)tigon2FwText);
+		ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
+		    (caddr_t)tigon2FwData);
+		ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
+		    (caddr_t)tigon2FwRodata);
+		ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
+		ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
+		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
+		break;
+	default:
+		printf("%s: can't load firmware: unknown hardware rev\n",
+		    sc->sc_dv.dv_xname);
+		break;
+	}
+
+	return;
+}
+
+/*
+ * Send the NIC a command via the command ring.
+ */
+static void ti_cmd(sc, cmd)
+	struct ti_softc		*sc;
+	struct ti_cmd_desc	*cmd;
+{
+	u_int32_t		index;
+
+	if (sc->ti_rdata->ti_cmd_ring == NULL)
+		return;
+
+	index = sc->ti_cmd_saved_prodidx;
+	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
+	TI_INC(index, TI_CMD_RING_CNT);
+	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
+	sc->ti_cmd_saved_prodidx = index;
+
+	return;
+}
+
+/*
+ * Send the NIC an extended command. The 'len' parameter specifies the
+ * number of command slots to include after the initial command.
+ */
+static void ti_cmd_ext(sc, cmd, arg, len)
+	struct ti_softc		*sc;
+	struct ti_cmd_desc	*cmd;
+	caddr_t			arg;
+	int			len;
+{
+	u_int32_t		index;
+	register int		i;
+
+	if (sc->ti_rdata->ti_cmd_ring == NULL)
+		return;
+
+	index = sc->ti_cmd_saved_prodidx;
+	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
+	TI_INC(index, TI_CMD_RING_CNT);
+	for (i = 0; i < len; i++) {
+		CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
+		    *(u_int32_t *)(&arg[i * 4]));
+		TI_INC(index, TI_CMD_RING_CNT);
+	}
+	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
+	sc->ti_cmd_saved_prodidx = index;
+
+	return;
+}
+
+/*
+ * Handle events that have triggered interrupts.
+ */
+static void ti_handle_events(sc)
+	struct ti_softc		*sc;
+{
+	struct ti_event_desc	*e;
+
+	if (sc->ti_rdata->ti_event_ring == NULL)
+		return;
+
+	while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
+		e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
+		switch(e->ti_event) {
+		case TI_EV_LINKSTAT_CHANGED:
+			sc->ti_linkstat = e->ti_code;
+			if (e->ti_code == TI_EV_CODE_LINK_UP)
+				printf("%s: 10/100 link up\n",
+				    sc->sc_dv.dv_xname);
+			else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
+				printf("%s: gigabit link up\n",
+				    sc->sc_dv.dv_xname);
+			else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
+				printf("%s: link down\n", sc->sc_dv.dv_xname);
+			break;
+		case TI_EV_ERROR:
+			if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
+				printf("%s: invalid command\n",
+				    sc->sc_dv.dv_xname);
+			else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
+				printf("%s: unknown command\n",
+				    sc->sc_dv.dv_xname);
+			else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
+				printf("%s: bad config data\n",
+				    sc->sc_dv.dv_xname);
+			break;
+		case TI_EV_FIRMWARE_UP:
+			ti_init2(sc);
+			break;
+		case TI_EV_STATS_UPDATED:
+			ti_stats_update(sc);
+			break;
+		case TI_EV_RESET_JUMBO_RING:
+		case TI_EV_MCAST_UPDATED:
+			/* Who cares. */
+			break;
+		default:
+			printf("%s: unknown event: %d\n",
+			    sc->sc_dv.dv_xname, e->ti_event);
+			break;
+		}
+		/* Advance the consumer index. */
+		TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
+		CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
+	}
+
+	return;
+}
+
+/*
+ * Memory management for the jumbo receive ring is a pain in the
+ * butt. We need to allocate at least 9018 bytes of space per frame,
+ * _and_ it has to be contiguous (unless you use the extended
+ * jumbo descriptor format). Using malloc() all the time won't
+ * work: malloc() allocates memory in powers of two, which means we
+ * would end up wasting a considerable amount of space by allocating
+ * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
+ * to do our own memory management.
+ *
+ * The driver needs to allocate a contiguous chunk of memory at boot
+ * time. We then chop this up ourselves into 9K pieces and use them
+ * as external mbuf storage.
+ *
+ * One issue here is how much memory to allocate. The jumbo ring has
+ * 256 slots in it, but at 9K per slot than can consume over 2MB of
+ * RAM. This is a bit much, especially considering we also need
+ * RAM for the standard ring and mini ring (on the Tigon 2). To
+ * save space, we only actually allocate enough memory for 64 slots
+ * by default, which works out to between 500 and 600K. This can
+ * be tuned by changing a #define in if_tireg.h.
+ */
+
+static int ti_alloc_jumbo_mem(sc)
+	struct ti_softc		*sc;
+{
+	caddr_t			ptr;
+	register int		i;
+	struct ti_jpool_entry   *entry;
+
+	/* Grab a big chunk o' storage. */
+	sc->ti_cdata.ti_jumbo_buf = (caddr_t) vm_page_alloc_contig(
+	    TI_JMEM, 0x100000, 0xffffffff, PAGE_SIZE);
+
+	if (sc->ti_cdata.ti_jumbo_buf == NULL) {
+		printf("%s: no memory for jumbo buffers!\n",
+		    sc->sc_dv.dv_xname);
+		return(ENOBUFS);
+	}
+
+	LIST_INIT(&sc->ti_jfree_listhead);
+	LIST_INIT(&sc->ti_jinuse_listhead);
+
+	/*
+	 * Now divide it up into 9K pieces and save the addresses
+	 * in an array. Note that we play an evil trick here by using
+	 * the first few bytes in the buffer to hold the the address
+	 * of the softc structure for this interface. This is because
+	 * ti_jfree() needs it, but it is called by the mbuf management
+	 * code which will not pass it to us explicitly.
+	 */
+	ptr = sc->ti_cdata.ti_jumbo_buf;
+	for (i = 0; i < TI_JSLOTS; i++) {
+		u_int64_t		**aptr;
+		aptr = (u_int64_t **)ptr;
+		aptr[0] = (u_int64_t *)sc;
+		ptr += sizeof(u_int64_t);
+		sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
+		sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
+		ptr += (TI_JLEN - sizeof(u_int64_t));
+		entry = malloc(sizeof(struct ti_jpool_entry), 
+			       M_DEVBUF, M_NOWAIT);
+		if (entry == NULL) {
+			free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF);
+			sc->ti_cdata.ti_jumbo_buf = NULL;
+			printf("%s: no memory for jumbo "
+			    "buffer queue!\n", sc->sc_dv.dv_xname);
+			return(ENOBUFS);
+		}
+		entry->slot = i;
+		LIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
+	}
+
+	return(0);
+}
+
+/*
+ * Allocate a jumbo buffer.
+ */
+static void *ti_jalloc(sc)
+	struct ti_softc		*sc;
+{
+	struct ti_jpool_entry   *entry;
+	
+	entry = LIST_FIRST(&sc->ti_jfree_listhead);
+	
+	if (entry == NULL) {
+		printf("%s: no free jumbo buffers\n", sc->sc_dv.dv_xname);
+		return(NULL);
+	}
+
+	LIST_REMOVE(entry, jpool_entries);
+	LIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
+	sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
+	return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
+}
+
+#if 0
+/*
+ * Adjust usage count on a jumbo buffer. In general this doesn't
+ * get used much because our jumbo buffers don't get passed around
+ * too much, but it's implemented for correctness.
+ */
+static void ti_jref(buf, size)
+	caddr_t			buf;
+	u_int			size;
+{
+	struct ti_softc		*sc;
+	u_int64_t		**aptr;
+	register int		i;
+
+	/* Extract the softc struct pointer. */
+	aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
+	sc = (struct ti_softc *)(aptr[0]);
+
+	if (sc == NULL)
+		panic("ti_jref: can't find softc pointer!");
+
+	if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN)
+		panic("ti_jref: adjusting refcount of buf of wrong size!");
+
+	/* calculate the slot this buffer belongs to */
+
+	i = ((vm_offset_t)aptr 
+	     - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
+
+	if ((i < 0) || (i >= TI_JSLOTS))
+		panic("ti_jref: asked to reference buffer "
+		    "that we don't manage!");
+	else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
+		panic("ti_jref: buffer already free!");
+	else
+		sc->ti_cdata.ti_jslots[i].ti_inuse++;
+
+	return;
+}
+#endif
+
+/*
+ * Release a jumbo buffer.
+ */
+static void ti_jfree(buf, size)
+	caddr_t			buf;
+	u_int			size;
+{
+	struct ti_softc		*sc;
+	u_int64_t		**aptr;
+	int		        i;
+	struct ti_jpool_entry   *entry;
+
+	/* Extract the softc struct pointer. */
+	aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
+	sc = (struct ti_softc *)(aptr[0]);
+
+	if (sc == NULL)
+		panic("ti_jfree: can't find softc pointer!");
+
+	if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN)
+		panic("ti_jfree: freeing buffer of wrong size!");
+
+	/* calculate the slot this buffer belongs to */
+
+	i = ((vm_offset_t)aptr 
+	     - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
+
+	if ((i < 0) || (i >= TI_JSLOTS))
+		panic("ti_jfree: asked to free buffer that we don't manage!");
+	else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
+		panic("ti_jfree: buffer already free!");
+	else {
+		sc->ti_cdata.ti_jslots[i].ti_inuse--;
+		if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
+			entry = LIST_FIRST(&sc->ti_jinuse_listhead);
+			if (entry == NULL)
+				panic("ti_jfree: buffer not in use!");
+			entry->slot = i;
+			LIST_REMOVE(entry, jpool_entries);
+			LIST_INSERT_HEAD(&sc->ti_jfree_listhead, 
+					  entry, jpool_entries);
+		}
+	}
+
+	return;
+}
+
+
+/*
+ * Intialize a standard receive ring descriptor.
+ */
+static int ti_newbuf_std(sc, i, m)
+	struct ti_softc		*sc;
+	int			i;
+	struct mbuf		*m;
+{
+	struct mbuf		*m_new = NULL;
+	struct ti_rx_desc	*r;
+
+	if (m != NULL) {
+		m_new = m;
+	} else {
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL) {
+			printf("%s: mbuf allocation failed "
+			    "-- packet dropped!\n", sc->sc_dv.dv_xname);
+			return(ENOBUFS);
+		}
+
+		MCLGET(m_new, M_DONTWAIT);
+		if (!(m_new->m_flags & M_EXT)) {
+			printf("sc->sc_dv.dv_xname: cluster allocation failed "
+			    "-- packet dropped!\n", sc->sc_dv.dv_xname);
+			m_freem(m_new);
+			return(ENOBUFS);
+		}
+	}
+
+	m_adj(m_new, ETHER_ALIGN);
+	sc->ti_cdata.ti_rx_std_chain[i] = m_new;
+	r = &sc->ti_rdata->ti_rx_std_ring[i];
+	TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
+	r->ti_type = TI_BDTYPE_RECV_BD;
+#ifdef TI_CSUM_OFFLOAD
+	r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
+#else
+	r->ti_flags = 0;
+#endif
+	r->ti_len = MCLBYTES - ETHER_ALIGN;
+	r->ti_idx = i;
+
+	return(0);
+}
+
+/*
+ * Intialize a mini receive ring descriptor. This only applies to
+ * the Tigon 2.
+ */
+static int ti_newbuf_mini(sc, i, m)
+	struct ti_softc		*sc;
+	int			i;
+	struct mbuf		*m;
+{
+	struct mbuf		*m_new = NULL;
+	struct ti_rx_desc	*r;
+
+	if (m != NULL) {
+		m_new = m;
+	} else {
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL) {
+			printf("%s: mbuf allocation failed "
+			    "-- packet dropped!\n", sc->sc_dv.dv_xname);
+			return(ENOBUFS);
+		}
+	}
+	m_adj(m_new, ETHER_ALIGN);
+	r = &sc->ti_rdata->ti_rx_mini_ring[i];
+	sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
+	TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
+	r->ti_type = TI_BDTYPE_RECV_BD;
+	r->ti_flags = TI_BDFLAG_MINI_RING;
+#ifdef TI_CSUM_OFFLOAD
+	r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
+#endif
+	r->ti_len = MHLEN - ETHER_ALIGN;
+	r->ti_idx = i;
+
+	return(0);
+}
+
+/*
+ * Initialize a jumbo receive ring descriptor. This allocates
+ * a jumbo buffer from the pool managed internally by the driver.
+ */
+static int ti_newbuf_jumbo(sc, i, m)
+	struct ti_softc		*sc;
+	int			i;
+	struct mbuf		*m;
+{
+	struct mbuf		*m_new = NULL;
+	struct ti_rx_desc	*r;
+
+	if (m != NULL) {
+		m_new = m;
+	} else {
+		caddr_t			*buf = NULL;
+
+		/* Allocate the mbuf. */
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL) {
+			printf("%s: mbuf allocation failed "
+			    "-- packet dropped!\n", sc->sc_dv.dv_xname);
+			return(ENOBUFS);
+		}
+
+		/* Allocate the jumbo buffer */
+		buf = ti_jalloc(sc);
+		if (buf == NULL) {
+			m_freem(m_new);
+			printf("%s: jumbo allocation failed "
+			    "-- packet dropped!\n", sc->sc_dv.dv_xname);
+			return(ENOBUFS);
+		}
+
+		/* Attach the buffer to the mbuf. */
+		m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
+		m_new->m_data += ETHER_ALIGN;
+		m_new->m_flags |= M_EXT;
+		m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN - ETHER_ALIGN;
+		m_new->m_ext.ext_free = ti_jfree;
+#if 0
+		m_new->m_ext.ext_ref = ti_jref;
+#endif
+	}
+
+	/* Set up the descriptor. */
+	r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
+	sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
+	TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
+	r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
+	r->ti_flags = TI_BDFLAG_JUMBO_RING;
+#ifdef TI_CSUM_OFFLOAD
+	r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
+#endif
+	r->ti_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN;
+	r->ti_idx = i;
+
+	return(0);
+}
+
+/*
+ * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
+ * that's 1MB or memory, which is a lot. For now, we fill only the first
+ * 256 ring entries and hope that our CPU is fast enough to keep up with
+ * the NIC.
+ */
+static int ti_init_rx_ring_std(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+	struct ti_cmd_desc	cmd;
+
+	for (i = 0; i < TI_SSLOTS; i++) {
+		if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
+			return(ENOBUFS);
+	};
+
+	TI_UPDATE_STDPROD(sc, i - 1);
+	sc->ti_std = i - 1;
+
+	return(0);
+}
+
+static void ti_free_rx_ring_std(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+
+	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
+		if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
+			m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
+			sc->ti_cdata.ti_rx_std_chain[i] = NULL;
+		}
+		bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
+		    sizeof(struct ti_rx_desc));
+	}
+
+	return;
+}
+
+static int ti_init_rx_ring_jumbo(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+	struct ti_cmd_desc	cmd;
+
+	for (i = 0; i < (TI_JSLOTS - 20); i++) {
+		if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
+			return(ENOBUFS);
+	};
+
+	TI_UPDATE_JUMBOPROD(sc, i - 1);
+	sc->ti_jumbo = i - 1;
+
+	return(0);
+}
+
+static void ti_free_rx_ring_jumbo(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+
+	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
+		if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
+			m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
+			sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
+		}
+		bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
+		    sizeof(struct ti_rx_desc));
+	}
+
+	return;
+}
+
+static int ti_init_rx_ring_mini(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+
+	for (i = 0; i < TI_MSLOTS; i++) {
+		if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
+			return(ENOBUFS);
+	};
+
+	TI_UPDATE_MINIPROD(sc, i - 1);
+	sc->ti_mini = i - 1;
+
+	return(0);
+}
+
+static void ti_free_rx_ring_mini(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+
+	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
+		if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
+			m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
+			sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
+		}
+		bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
+		    sizeof(struct ti_rx_desc));
+	}
+
+	return;
+}
+
+static void ti_free_tx_ring(sc)
+	struct ti_softc		*sc;
+{
+	register int		i;
+
+	if (sc->ti_rdata->ti_tx_ring == NULL)
+		return;
+
+	for (i = 0; i < TI_TX_RING_CNT; i++) {
+		if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
+			m_freem(sc->ti_cdata.ti_tx_chain[i]);
+			sc->ti_cdata.ti_tx_chain[i] = NULL;
+		}
+		bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
+		    sizeof(struct ti_tx_desc));
+	}
+
+	return;
+}
+
+static int ti_init_tx_ring(sc)
+	struct ti_softc		*sc;
+{
+	sc->ti_txcnt = 0;
+	sc->ti_tx_saved_considx = 0;
+	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
+	return(0);
+}
+
+/*
+ * The Tigon 2 firmware has a new way to add/delete multicast addresses,
+ * but we have to support the old way too so that Tigon 1 cards will
+ * work.
+ */
+void ti_add_mcast(sc, addr)
+	struct ti_softc		*sc;
+	struct ether_addr	*addr;
+{
+	struct ti_cmd_desc	cmd;
+	u_int16_t		*m;
+	u_int32_t		ext[2] = {0, 0};
+
+	m = (u_int16_t *)&addr->ether_addr_octet[0];
+
+	switch(sc->ti_hwrev) {
+	case TI_HWREV_TIGON:
+		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
+		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
+		TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
+		break;
+	case TI_HWREV_TIGON_II:
+		ext[0] = htons(m[0]);
+		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
+		TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
+		break;
+	default:
+		printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname);
+		break;
+	}
+
+	return;
+}
+
+void ti_del_mcast(sc, addr)
+	struct ti_softc		*sc;
+	struct ether_addr	*addr;
+{
+	struct ti_cmd_desc	cmd;
+	u_int16_t		*m;
+	u_int32_t		ext[2] = {0, 0};
+
+	m = (u_int16_t *)&addr->ether_addr_octet[0];
+
+	switch(sc->ti_hwrev) {
+	case TI_HWREV_TIGON:
+		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
+		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
+		TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
+		break;
+	case TI_HWREV_TIGON_II:
+		ext[0] = htons(m[0]);
+		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
+		TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
+		break;
+	default:
+		printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname);
+		break;
+	}
+
+	return;
+}
+
+/*
+ * Configure the Tigon's multicast address filter.
+ *
+ * The actual multicast table management is a bit of a pain, thanks to
+ * slight brain damage on the part of both Alteon and us. With our
+ * multicast code, we are only alerted when the multicast address table
+ * changes and at that point we only have the current list of addresses:
+ * we only know the current state, not the previous state, so we don't
+ * actually know what addresses were removed or added. The firmware has
+ * state, but we can't get our grubby mits on it, and there is no 'delete
+ * all multicast addresses' command. Hence, we have to maintain our own
+ * state so we know what addresses have been programmed into the NIC at
+ * any given time.
+ */
+static void ti_setmulti(sc)
+	struct ti_softc		*sc;
+{
+	struct ifnet		*ifp;
+	struct arpcom		*ac = &sc->arpcom;
+	struct ether_multi	*enm;
+	struct ether_multistep	step;
+	struct ti_cmd_desc	cmd;
+	struct ti_mc_entry	*mc;
+	u_int32_t		intrs;
+	struct ti_mc_entry *p;
+
+	ifp = &sc->arpcom.ac_if;
+
+	if (ifp->if_flags & IFF_ALLMULTI) {
+		TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
+		return;
+	} else {
+		TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
+	}
+
+	/* Disable interrupts. */
+	intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
+
+	/* First, zot all the existing filters. */
+	p = LIST_FIRST(&sc->ti_mc_listhead);
+	while (p != NULL) {
+		mc = p;
+		ti_del_mcast(sc, &mc->mc_addr);
+		p = LIST_FIRST(&sc->ti_mc_listhead);
+		LIST_REMOVE(mc, mc_entries);
+		p = LIST_NEXT(p, mc_entries);
+		free(mc, M_DEVBUF);
+	}
+
+	/* Now program new ones. */
+	ETHER_FIRST_MULTI(step, ac, enm);
+	while (enm != NULL) {
+		mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
+		bcopy(enm->enm_addrlo, (char *)&mc->mc_addr, ETHER_ADDR_LEN);
+		LIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
+		ti_add_mcast(sc, &mc->mc_addr);
+	}
+
+	/* Re-enable interrupts. */
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
+
+	return;
+}
+
+/*
+ * Check to see if the BIOS has configured us for a 64 bit slot when
+ * we aren't actually in one. If we detect this condition, we can work
+ * around it on the Tigon 2 by setting a bit in the PCI state register,
+ * but for the Tigon 1 we must give up and abort the interface attach.
+ */
+static int ti_64bitslot_war(sc)
+	struct ti_softc		*sc;
+{
+	if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
+		CSR_WRITE_4(sc, 0x600, 0);
+		CSR_WRITE_4(sc, 0x604, 0);
+		CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
+		if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
+			if (sc->ti_hwrev == TI_HWREV_TIGON)
+				return(EINVAL);
+			else {
+				TI_SETBIT(sc, TI_PCI_STATE,
+				    TI_PCISTATE_32BIT_BUS);
+				return(0);
+			}
+		}
+	}
+
+	return(0);
+}
+
+/*
+ * Do endian, PCI and DMA initialization. Also check the on-board ROM
+ * self-test results.
+ */
+static int ti_chipinit(sc)
+	struct ti_softc		*sc;
+{
+	u_int32_t		cacheline;
+	u_int32_t		pci_writemax = 0;
+
+	/* Initialize link to down state. */
+	sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
+
+	/* Set endianness before we access any non-PCI registers. */
+#if BYTE_ORDER == BIG_ENDIAN
+	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
+	    TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
+#else
+	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
+	    TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
+#endif
+
+	/* Check the ROM failed bit to see if self-tests passed. */
+	if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
+		printf("%s: board self-diagnostics failed!\n",
+		    sc->sc_dv.dv_xname);
+		return(ENODEV);
+	}
+
+	/* Halt the CPU. */
+	TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
+
+	/* Figure out the hardware revision. */
+	switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
+	case TI_REV_TIGON_I:
+		sc->ti_hwrev = TI_HWREV_TIGON;
+		break;
+	case TI_REV_TIGON_II:
+		sc->ti_hwrev = TI_HWREV_TIGON_II;
+		break;
+	default:
+		printf("%s: unsupported chip revision\n", sc->sc_dv.dv_xname);
+		return(ENODEV);
+	}
+
+	/* Do special setup for Tigon 2. */
+	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
+		TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
+		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
+		TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
+	}
+
+	/* Set up the PCI state register. */
+	CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
+	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
+		TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
+	}
+
+	/* Clear the read/write max DMA parameters. */
+	TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
+	    TI_PCISTATE_READ_MAXDMA));
+
+	/* Get cache line size. */
+	cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
+
+	/*
+	 * If the system has set enabled the PCI memory write
+	 * and invalidate command in the command register, set
+	 * the write max parameter accordingly. This is necessary
+	 * to use MWI with the Tigon 2.
+	 */
+	if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
+		switch(cacheline) {
+		case 1:
+		case 4:
+		case 8:
+		case 16:
+		case 32:
+		case 64:
+			break;
+		default:
+		/* Disable PCI memory write and invalidate. */
+			if (bootverbose)
+				printf("%s: cache line size %d not "
+				    "supported; disabling PCI MWI\n",
+				    sc->sc_dv.dv_xname, cacheline);
+			CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
+			    TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
+			break;
+		}
+	}
+
+#ifdef __brokenalpha__
+	/*
+	 * From the Alteon sample driver:
+	 * Must insure that we do not cross an 8K (bytes) boundary
+	 * for DMA reads.  Our highest limit is 1K bytes.  This is a 
+	 * restriction on some ALPHA platforms with early revision 
+	 * 21174 PCI chipsets, such as the AlphaPC 164lx 
+	 */
+	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
+#else
+	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
+#endif
+
+	/* This sets the min dma param all the way up (0xff). */
+	TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
+
+	/* Configure DMA variables. */
+#if BYTE_ORDER == BIG_ENDIAN
+	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
+	    TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
+	    TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
+	    TI_OPMODE_DONT_FRAG_JUMBO);
+#else
+	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
+	    TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
+	    TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
+#endif
+
+	/*
+	 * Only allow 1 DMA channel to be active at a time.
+	 * I don't think this is a good idea, but without it
+	 * the firmware racks up lots of nicDmaReadRingFull
+	 * errors.
+	 */
+#ifndef TI_CSUM_OFFLOAD
+	TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
+#endif
+
+	/* Recommended settings from Tigon manual. */
+	CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
+	CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
+
+	if (ti_64bitslot_war(sc)) {
+		printf("%s: bios thinks we're in a 64 bit slot, "
+		    "but we aren't", sc->sc_dv.dv_xname);
+		return(EINVAL);
+	}
+
+	return(0);
+}
+
+/*
+ * Initialize the general information block and firmware, and
+ * start the CPU(s) running.
+ */
+static int ti_gibinit(sc)
+	struct ti_softc		*sc;
+{
+	struct ti_rcb		*rcb;
+	int			i;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/* Disable interrupts for now. */
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
+
+	/* Tell the chip where to find the general information block. */
+	CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
+	CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
+
+	/* Load the firmware into SRAM. */
+	ti_loadfw(sc);
+
+	/* Set up the contents of the general info and ring control blocks. */
+
+	/* Set up the event ring and producer pointer. */
+	rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
+
+	TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
+	rcb->ti_flags = 0;
+	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
+	    vtophys(&sc->ti_ev_prodidx);
+	sc->ti_ev_prodidx.ti_idx = 0;
+	CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
+	sc->ti_ev_saved_considx = 0;
+
+	/* Set up the command ring and producer mailbox. */
+	rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
+
+#ifdef __i386__
+	sc->ti_rdata->ti_cmd_ring =
+	    (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING);
+#endif
+#ifdef __alpha__
+	sc->ti_rdata->ti_cmd_ring =
+	    (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
+#endif
+	TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
+	rcb->ti_flags = 0;
+	rcb->ti_max_len = 0;
+	for (i = 0; i < TI_CMD_RING_CNT; i++) {
+		CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
+	}
+	CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
+	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
+	sc->ti_cmd_saved_prodidx = 0;
+
+	/*
+	 * Assign the address of the stats refresh buffer.
+	 * We re-use the current stats buffer for this to
+	 * conserve memory.
+	 */
+	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
+	    vtophys(&sc->ti_rdata->ti_info.ti_stats);
+
+	/* Set up the standard receive ring. */
+	rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
+	TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
+	rcb->ti_max_len = TI_FRAMELEN;
+	rcb->ti_flags = 0;
+#ifdef TI_CSUM_OFFLOAD
+	rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
+#endif
+#if NVLAN > 0
+	rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
+#endif
+
+	/* Set up the jumbo receive ring. */
+	rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
+	TI_HOSTADDR(rcb->ti_hostaddr) =
+	    vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
+	rcb->ti_max_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN;
+	rcb->ti_flags = 0;
+#ifdef TI_CSUM_OFFLOAD
+	rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
+#endif
+#if NVLAN > 0
+	rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
+#endif
+
+	/*
+	 * Set up the mini ring. Only activated on the
+	 * Tigon 2 but the slot in the config block is
+	 * still there on the Tigon 1.
+	 */
+	rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
+	TI_HOSTADDR(rcb->ti_hostaddr) =
+	    vtophys(&sc->ti_rdata->ti_rx_mini_ring);
+	rcb->ti_max_len = MHLEN;
+	if (sc->ti_hwrev == TI_HWREV_TIGON)
+		rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
+	else
+		rcb->ti_flags = 0;
+#ifdef TI_CSUM_OFFLOAD
+	rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
+#endif
+#if NVLAN > 0
+	rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
+#endif
+
+	/*
+	 * Set up the receive return ring.
+	 */
+	rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
+	TI_HOSTADDR(rcb->ti_hostaddr) =
+	    vtophys(&sc->ti_rdata->ti_rx_return_ring);
+	rcb->ti_flags = 0;
+	rcb->ti_max_len = TI_RETURN_RING_CNT;
+	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
+	    vtophys(&sc->ti_return_prodidx);
+
+	/*
+	 * Set up the tx ring. Note: for the Tigon 2, we have the option
+	 * of putting the transmit ring in the host's address space and
+	 * letting the chip DMA it instead of leaving the ring in the NIC's
+	 * memory and accessing it through the shared memory region. We
+	 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
+	 * so we have to revert to the shared memory scheme if we detect
+	 * a Tigon 1 chip.
+	 */
+	CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
+	if (sc->ti_hwrev == TI_HWREV_TIGON) {
+#ifdef __i386__
+		sc->ti_rdata->ti_tx_ring_nic =
+		    (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW);
+#endif
+#ifdef __alpha__
+		sc->ti_rdata->ti_tx_ring_nic =
+		    (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
+#endif
+	}
+	bzero((char *)sc->ti_rdata->ti_tx_ring,
+	    TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
+	rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
+	if (sc->ti_hwrev == TI_HWREV_TIGON)
+		rcb->ti_flags = 0;
+	else
+		rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
+#if NVLAN > 0
+	rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
+#endif
+	rcb->ti_max_len = TI_TX_RING_CNT;
+	if (sc->ti_hwrev == TI_HWREV_TIGON)
+		TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
+	else
+		TI_HOSTADDR(rcb->ti_hostaddr) =
+		    vtophys(&sc->ti_rdata->ti_tx_ring);
+	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
+	    vtophys(&sc->ti_tx_considx);
+
+	/* Set up tuneables */
+	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
+		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
+		    (sc->ti_rx_coal_ticks / 10));
+	else
+		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
+	CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
+	CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
+	CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
+	CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
+	CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
+
+	/* Turn interrupts on. */
+	CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
+
+	/* Start CPU. */
+	TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
+
+	return(0);
+}
+
+/*
+ * Probe for a Tigon chip. Check the PCI vendor and device IDs
+ * against our list and return its name if we find a match.
+ */
+static int
+ti_probe(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
+
+	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR &&
+	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620)
+		return (1);
+
+	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON &&
+	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC)
+		return (1);
+
+	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3COM &&
+	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3COM_3C985)
+		return (1);
+
+	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SGI &&
+	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SGI_TIGON)
+		return (1);
+
+	return (0);
+}
+
+
+static void
+ti_attach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct ti_softc *sc = (struct ti_softc *)self;
+	struct pci_attach_args *pa = aux;
+	pci_chipset_tag_t pc = pa->pa_pc;
+	pci_intr_handle_t ih;
+	const char *intrstr = NULL;
+	bus_addr_t iobase;
+	bus_size_t iosize;
+	int s;
+	u_int32_t command;
+	struct ifnet *ifp;
+
+	s = splimp();
+
+	/*
+	 * Map control/status registers.
+	 */
+	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+	command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
+	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
+	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+
+	if (!(command & PCI_COMMAND_MEM_ENABLE)) {
+		printf("%s: failed to enable memory mapping!\n",
+		    sc->sc_dv.dv_xname);
+		free(sc, M_DEVBUF);
+		goto fail;
+	}
+	if (pci_mem_find(pc, pa->pa_tag, TI_PCI_LOMEM, &iobase, &iosize, NULL)) {
+		printf(": can't find mem space\n");
+		goto fail;
+	}
+	if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->ti_bhandle)) {
+		printf(": can't map mem space\n");
+		goto fail;
+	}
+	sc->ti_btag = pa->pa_memt;
+
+	if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
+	    pa->pa_intrline, &ih)) {
+		printf(": couldn't map interrupt\n");
+		goto fail;
+	}
+	intrstr = pci_intr_string(pc, ih);
+	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc,
+	    self->dv_xname);
+	if (sc->sc_ih == NULL) {
+		printf(": couldn't establish interrupt");
+		if (intrstr != NULL)
+			printf(" at %s", intrstr);
+		printf("\n");
+		goto fail;
+	}
+
+	if (ti_chipinit(sc)) {
+		printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname);
+		goto fail;
+	}
+
+	/* Zero out the NIC's on-board SRAM. */
+	ti_mem(sc, 0x2000, 0x100000 - 0x2000,  NULL);
+
+	/* Init again -- zeroing memory may have clobbered some registers. */
+	if (ti_chipinit(sc)) {
+		printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname);
+		goto fail;
+	}
+
+	/*
+	 * Get station address from the EEPROM. Note: the manual states
+	 * that the MAC address is at offset 0x8c, however the data is
+	 * stored as two longwords (since that's how it's loaded into
+	 * the NIC). This means the MAC address is actually preceeded
+	 * by two zero bytes. We need to skip over those.
+	 */
+	if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
+				TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
+		printf("%s: failed to read station address\n",
+		    sc->sc_dv.dv_xname);
+		free(sc, M_DEVBUF);
+		goto fail;
+	}
+
+	/*
+	 * A Tigon chip was detected. Inform the world.
+	 */
+	printf(": %s address %s\n", intrstr,
+	     ether_sprintf(sc->arpcom.ac_enaddr));
+
+	/* Allocate the general information block and ring buffers. */
+	sc->ti_rdata_ptr = (caddr_t) vm_page_alloc_contig(
+	    sizeof(struct ti_ring_data), 0x100000, 0xffffffff, PAGE_SIZE);
+
+	if (sc->ti_rdata_ptr == NULL) {
+		printf("%s: no memory for list buffers!\n", sc->sc_dv.dv_xname);
+		goto fail;
+	}
+
+	sc->ti_rdata = (struct ti_ring_data *)sc->ti_rdata_ptr;
+	bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
+
+	/* Try to allocate memory for jumbo buffers. */
+	if (ti_alloc_jumbo_mem(sc)) {
+		printf("%s: jumbo buffer allocation failed\n",
+		    sc->sc_dv.dv_xname);
+		goto fail;
+	}
+
+	/* Set default tuneable values. */
+	sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
+	sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
+	sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
+	sc->ti_rx_max_coal_bds = 64;
+	sc->ti_tx_max_coal_bds = 128;
+	sc->ti_tx_buf_ratio = 21;
+
+	/* Set up ifnet structure */
+	ifp = &sc->arpcom.ac_if;
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = ti_ioctl;
+	ifp->if_output = ether_output;
+	ifp->if_start = ti_start;
+	ifp->if_watchdog = ti_watchdog;
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
+	bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ);
+
+	/* Set up ifmedia support. */
+	ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
+	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
+	ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
+
+	/*
+	 * Call MI attach routines.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+#if NBPFILTER > 0
+	bpfattach(&sc->arpcom.ac_if.if_bpf, ifp,
+	    DLT_EN10MB, sizeof(struct ether_header));
+#endif
+
+	shutdownhook_establish(ti_shutdown, sc);
+
+fail:
+	splx(s);
+
+	return;
+}
+
+/*
+ * Frame reception handling. This is called if there's a frame
+ * on the receive return list.
+ *
+ * Note: we have to be able to handle three possibilities here:
+ * 1) the frame is from the mini receive ring (can only happen)
+ *    on Tigon 2 boards)
+ * 2) the frame is from the jumbo recieve ring
+ * 3) the frame is from the standard receive ring
+ */
+
+static void ti_rxeof(sc)
+	struct ti_softc		*sc;
+{
+	struct ifnet		*ifp;
+	struct ti_cmd_desc	cmd;
+
+	ifp = &sc->arpcom.ac_if;
+
+	while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
+		struct ti_rx_desc	*cur_rx;
+		u_int32_t		rxidx;
+		struct ether_header	*eh;
+		struct mbuf		*m = NULL;
+#if NVLAN > 0
+		u_int16_t		vlan_tag = 0;
+		int			have_tag = 0;
+#endif
+#ifdef TI_CSUM_OFFLOAD
+		struct ip		*ip;
+#endif
+
+		cur_rx =
+		    &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
+		rxidx = cur_rx->ti_idx;
+		TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
+
+#if NVLAN > 0
+		if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
+			have_tag = 1;
+			vlan_tag = cur_rx->ti_vlan_tag;
+		}
+#endif
+
+		if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
+			TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
+			m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
+			sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
+			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
+				ifp->if_ierrors++;
+				ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
+				continue;
+			}
+			if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
+				ifp->if_ierrors++;
+				ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
+				continue;
+			}
+		} else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
+			TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
+			m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
+			sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
+			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
+				ifp->if_ierrors++;
+				ti_newbuf_mini(sc, sc->ti_mini, m);
+				continue;
+			}
+			if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
+				ifp->if_ierrors++;
+				ti_newbuf_mini(sc, sc->ti_mini, m);
+				continue;
+			}
+		} else {
+			TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
+			m = sc->ti_cdata.ti_rx_std_chain[rxidx];
+			sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
+			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
+				ifp->if_ierrors++;
+				ti_newbuf_std(sc, sc->ti_std, m);
+				continue;
+			}
+			if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
+				ifp->if_ierrors++;
+				ti_newbuf_std(sc, sc->ti_std, m);
+				continue;
+			}
+		}
+
+		m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
+		ifp->if_ipackets++;
+		eh = mtod(m, struct ether_header *);
+		m->m_pkthdr.rcvif = ifp;
+
+#if NBPFILTER > 0
+		/*
+	 	 * Handle BPF listeners. Let the BPF user see the packet.
+	 	 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m);
+#endif
+
+		/* Remove header from mbuf and pass it on. */
+		m_adj(m, sizeof(struct ether_header));
+
+#ifdef TI_CSUM_OFFLOAD
+		ip = mtod(m, struct ip *);
+		if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) &&
+		    !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF)))
+			m->m_flags |= M_HWCKSUM;
+#endif
+
+#if NVLAN > 0
+		/*
+		 * If we received a packet with a vlan tag, pass it
+		 * to vlan_input() instead of ether_input().
+		 */
+		if (have_tag) {
+			vlan_input_tag(eh, m, vlan_tag);
+			have_tag = vlan_tag = 0;
+			continue;
+		}
+#endif
+		ether_input(ifp, eh, m);
+	}
+
+	/* Only necessary on the Tigon 1. */
+	if (sc->ti_hwrev == TI_HWREV_TIGON)
+		CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
+		    sc->ti_rx_saved_considx);
+
+	TI_UPDATE_STDPROD(sc, sc->ti_std);
+	TI_UPDATE_MINIPROD(sc, sc->ti_mini);
+	TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
+
+	return;
+}
+
+static void ti_txeof(sc)
+	struct ti_softc		*sc;
+{
+	struct ti_tx_desc	*cur_tx = NULL;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/*
+	 * Go through our tx ring and free mbufs for those
+	 * frames that have been sent.
+	 */
+	while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
+		u_int32_t		idx = 0;
+
+		idx = sc->ti_tx_saved_considx;
+		if (sc->ti_hwrev == TI_HWREV_TIGON) {
+			if (idx > 383)
+				CSR_WRITE_4(sc, TI_WINBASE,
+				    TI_TX_RING_BASE + 6144);
+			else if (idx > 255)
+				CSR_WRITE_4(sc, TI_WINBASE,
+				    TI_TX_RING_BASE + 4096);
+			else if (idx > 127)
+				CSR_WRITE_4(sc, TI_WINBASE,
+				    TI_TX_RING_BASE + 2048);
+			else
+				CSR_WRITE_4(sc, TI_WINBASE,
+				    TI_TX_RING_BASE);
+			cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
+		} else
+			cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
+		if (cur_tx->ti_flags & TI_BDFLAG_END)
+			ifp->if_opackets++;
+		if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
+			m_freem(sc->ti_cdata.ti_tx_chain[idx]);
+			sc->ti_cdata.ti_tx_chain[idx] = NULL;
+		}
+		sc->ti_txcnt--;
+		TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
+		ifp->if_timer = 0;
+	}
+
+	if (cur_tx != NULL)
+		ifp->if_flags &= ~IFF_OACTIVE;
+
+	return;
+}
+
+static int ti_intr(xsc)
+	void			*xsc;
+{
+	struct ti_softc		*sc;
+	struct ifnet		*ifp;
+	int			claimed = 0;
+
+	sc = xsc;
+	ifp = &sc->arpcom.ac_if;
+
+#ifdef notdef
+	/* Avoid this for now -- checking this register is expensive. */
+	/* Make sure this is really our interrupt. */
+	if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
+		return;
+#endif
+
+	/* Ack interrupt and stop others from occuring. */
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
+
+	if (ifp->if_flags & IFF_RUNNING) {
+		claimed = 1;
+
+		/* Check RX return ring producer/consumer */
+		ti_rxeof(sc);
+
+		/* Check TX ring producer/consumer */
+		ti_txeof(sc);
+	}
+
+	ti_handle_events(sc);
+
+	/* Re-enable interrupts. */
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
+
+	if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
+		ti_start(ifp);
+
+	return (claimed);
+}
+
+static void ti_stats_update(sc)
+	struct ti_softc		*sc;
+{
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	ifp->if_collisions +=
+	   (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
+	   sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
+	   sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
+	   sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
+	   ifp->if_collisions;
+
+	return;
+}
+
+/*
+ * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
+ * pointers to descriptors.
+ */
+static int ti_encap(sc, m_head, txidx)
+	struct ti_softc		*sc;
+	struct mbuf		*m_head;
+	u_int32_t		*txidx;
+{
+	struct ti_tx_desc	*f = NULL;
+	struct mbuf		*m;
+	u_int32_t		frag, cur, cnt = 0;
+#if NVLAN > 0
+	struct ifvlan		*ifv = NULL;
+
+	if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
+	    m_head->m_pkthdr.rcvif != NULL &&
+	    m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN)
+		ifv = m_head->m_pkthdr.rcvif->if_softc;
+#endif
+
+	m = m_head;
+	cur = frag = *txidx;
+
+	/*
+ 	 * Start packing the mbufs in this chain into
+	 * the fragment pointers. Stop when we run out
+ 	 * of fragments or hit the end of the mbuf chain.
+	 */
+	for (m = m_head; m != NULL; m = m->m_next) {
+		if (m->m_len != 0) {
+			if (sc->ti_hwrev == TI_HWREV_TIGON) {
+				if (frag > 383)
+					CSR_WRITE_4(sc, TI_WINBASE,
+					    TI_TX_RING_BASE + 6144);
+				else if (frag > 255)
+					CSR_WRITE_4(sc, TI_WINBASE,
+					    TI_TX_RING_BASE + 4096);
+				else if (frag > 127)
+					CSR_WRITE_4(sc, TI_WINBASE,
+					    TI_TX_RING_BASE + 2048);
+				else
+					CSR_WRITE_4(sc, TI_WINBASE,
+					    TI_TX_RING_BASE);
+				f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
+			} else
+				f = &sc->ti_rdata->ti_tx_ring[frag];
+			if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
+				break;
+			TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
+			f->ti_len = m->m_len;
+			f->ti_flags = 0;
+#if NVLAN > 0
+			if (ifv != NULL) {
+				f->ti_flags |= TI_BDFLAG_VLAN_TAG;
+				f->ti_vlan_tag = ifv->ifv_tag;
+			} else {
+				f->ti_vlan_tag = 0;
+			}
+#endif
+			/*
+			 * Sanity check: avoid coming within 16 descriptors
+			 * of the end of the ring.
+			 */
+			if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
+				return(ENOBUFS);
+			cur = frag;
+			TI_INC(frag, TI_TX_RING_CNT);
+			cnt++;
+		}
+	}
+
+	if (m != NULL)
+		return(ENOBUFS);
+
+	if (frag == sc->ti_tx_saved_considx)
+		return(ENOBUFS);
+
+	if (sc->ti_hwrev == TI_HWREV_TIGON)
+		sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
+		    TI_BDFLAG_END;
+	else
+		sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
+	sc->ti_cdata.ti_tx_chain[cur] = m_head;
+	sc->ti_txcnt += cnt;
+
+	*txidx = frag;
+
+	return(0);
+}
+
+/*
+ * Main transmit routine. To avoid having to do mbuf copies, we put pointers
+ * to the mbuf data regions directly in the transmit descriptors.
+ */
+static void ti_start(ifp)
+	struct ifnet		*ifp;
+{
+	struct ti_softc		*sc;
+	struct mbuf		*m_head = NULL;
+	u_int32_t		prodidx = 0;
+
+	sc = ifp->if_softc;
+
+	prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
+
+	while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
+		IF_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		/*
+		 * Pack the data into the transmit ring. If we
+		 * don't have room, set the OACTIVE flag and wait
+		 * for the NIC to drain the ring.
+		 */
+		if (ti_encap(sc, m_head, &prodidx)) {
+			IF_PREPEND(&ifp->if_snd, m_head);
+			ifp->if_flags |= IFF_OACTIVE;
+			break;
+		}
+
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+#if NBPFILTER > 0
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m_head);
+#endif
+	}
+
+	/* Transmit */
+	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
+
+	/*
+	 * Set a timeout in case the chip goes out to lunch.
+	 */
+	ifp->if_timer = 5;
+
+	return;
+}
+
+static void ti_init(xsc)
+	void			*xsc;
+{
+	struct ti_softc		*sc = xsc;
+        int			s;
+
+	s = splimp();
+
+	/* Cancel pending I/O and flush buffers. */
+	ti_stop(sc);
+
+	/* Init the gen info block, ring control blocks and firmware. */
+	if (ti_gibinit(sc)) {
+		printf("%s: initialization failure\n", sc->sc_dv.dv_xname);
+		splx(s);
+		return;
+	}
+
+	splx(s);
+
+	return;
+}
+
+static void ti_init2(sc)
+	struct ti_softc		*sc;
+{
+	struct ti_cmd_desc	cmd;
+	struct ifnet		*ifp;
+	u_int16_t		*m;
+	struct ifmedia		*ifm;
+	int			tmp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/* Specify MTU and interface index. */
+	CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dv.dv_unit);
+	CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
+	    ETHER_HDR_LEN + ETHER_CRC_LEN);
+	TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
+
+	/* Load our MAC address. */
+	m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
+	CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
+	CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
+	TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
+
+	/* Enable or disable promiscuous mode as needed. */
+	if (ifp->if_flags & IFF_PROMISC) {
+		TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
+	} else {
+		TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
+	}
+
+	/* Program multicast filter. */
+	ti_setmulti(sc);
+
+	/*
+	 * If this is a Tigon 1, we should tell the
+	 * firmware to use software packet filtering.
+	 */
+	if (sc->ti_hwrev == TI_HWREV_TIGON) {
+		TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
+	}
+
+	/* Init RX ring. */
+	ti_init_rx_ring_std(sc);
+
+	/* Init jumbo RX ring. */
+	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
+		ti_init_rx_ring_jumbo(sc);
+
+	/*
+	 * If this is a Tigon 2, we can also configure the
+	 * mini ring.
+	 */
+	if (sc->ti_hwrev == TI_HWREV_TIGON_II)
+		ti_init_rx_ring_mini(sc);
+
+	CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
+	sc->ti_rx_saved_considx = 0;
+
+	/* Init TX ring. */
+	ti_init_tx_ring(sc);
+
+	/* Tell firmware we're alive. */
+	TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
+
+	/* Enable host interrupts. */
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	/*
+	 * Make sure to set media properly. We have to do this
+	 * here since we have to issue commands in order to set
+	 * the link negotiation and we can't issue commands until
+	 * the firmware is running.
+	 */
+	ifm = &sc->ifmedia;
+	tmp = ifm->ifm_media;
+	ifm->ifm_media = ifm->ifm_cur->ifm_media;
+	ti_ifmedia_upd(ifp);
+	ifm->ifm_media = tmp;
+
+	return;
+}
+
+/*
+ * Set media options.
+ */
+static int ti_ifmedia_upd(ifp)
+	struct ifnet		*ifp;
+{
+	struct ti_softc		*sc;
+	struct ifmedia		*ifm;
+	struct ti_cmd_desc	cmd;
+
+	sc = ifp->if_softc;
+	ifm = &sc->ifmedia;
+
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+		return(EINVAL);
+
+	switch(IFM_SUBTYPE(ifm->ifm_media)) {
+	case IFM_AUTO:
+		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
+		    TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
+		    TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
+		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
+		    TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
+		    TI_LNK_AUTONEGENB|TI_LNK_ENB);
+		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
+		    TI_CMD_CODE_NEGOTIATE_BOTH, 0);
+		break;
+	case IFM_1000_SX:
+		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
+		    TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
+		CSR_WRITE_4(sc, TI_GCR_LINK, 0);
+		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
+		    TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
+		break;
+	case IFM_100_FX:
+	case IFM_10_FL:
+		CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
+		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
+		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) {
+			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
+		} else {
+			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
+		}
+		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
+			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
+		} else {
+			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
+		}
+		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
+		    TI_CMD_CODE_NEGOTIATE_10_100, 0);
+		break;
+	}
+
+	return(0);
+}
+
+/*
+ * Report current media status.
+ */
+static void ti_ifmedia_sts(ifp, ifmr)
+	struct ifnet		*ifp;
+	struct ifmediareq	*ifmr;
+{
+	struct ti_softc		*sc;
+
+	sc = ifp->if_softc;
+
+	ifmr->ifm_status = IFM_AVALID;
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
+		return;
+
+	ifmr->ifm_status |= IFM_ACTIVE;
+
+	if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
+		ifmr->ifm_active |= IFM_1000_SX|IFM_FDX;
+	else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
+		u_int32_t		media;
+		media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
+		if (media & TI_LNK_100MB)
+			ifmr->ifm_active |= IFM_100_FX;
+		if (media & TI_LNK_10MB)
+			ifmr->ifm_active |= IFM_10_FL;
+		if (media & TI_LNK_FULL_DUPLEX)
+			ifmr->ifm_active |= IFM_FDX;
+		if (media & TI_LNK_HALF_DUPLEX)
+			ifmr->ifm_active |= IFM_HDX;
+	}
+	
+	return;
+}
+
+static int ti_ioctl(ifp, command, data)
+	struct ifnet		*ifp;
+	u_long			command;
+	caddr_t			data;
+{
+	struct ti_softc		*sc = ifp->if_softc;
+	struct ifreq		*ifr = (struct ifreq *) data;
+	struct ifaddr		*ifa = (struct ifaddr *) data;
+	int			s, error = 0;
+	struct ti_cmd_desc	cmd;
+
+	s = splimp();
+
+	if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
+		splx(s);
+		return (error);
+	}
+
+	switch(command) {
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			ti_init(sc);
+			arp_ifinit(&sc->arpcom, ifa);
+			break;
+#endif /* INET */
+		default:
+			ti_init(sc);
+			break;
+		}
+		break;
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			/*
+			 * If only the state of the PROMISC flag changed,
+			 * then just use the 'set promisc mode' command
+			 * instead of reinitializing the entire NIC. Doing
+			 * a full re-init means reloading the firmware and
+			 * waiting for it to start up, which may take a
+			 * second or two.
+			 */
+			if (ifp->if_flags & IFF_RUNNING &&
+			    ifp->if_flags & IFF_PROMISC &&
+			    !(sc->ti_if_flags & IFF_PROMISC)) {
+				TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
+				    TI_CMD_CODE_PROMISC_ENB, 0);
+			} else if (ifp->if_flags & IFF_RUNNING &&
+			    !(ifp->if_flags & IFF_PROMISC) &&
+			    sc->ti_if_flags & IFF_PROMISC) {
+				TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
+				    TI_CMD_CODE_PROMISC_DIS, 0);
+			} else
+				ti_init(sc);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING) {
+				ti_stop(sc);
+			}
+		}
+		sc->ti_if_flags = ifp->if_flags;
+		error = 0;
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		if (ifp->if_flags & IFF_RUNNING) {
+			ti_setmulti(sc);
+			error = 0;
+		}
+		break;
+	case SIOCSIFMEDIA:
+	case SIOCGIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
+		break;
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	(void)splx(s);
+
+	return(error);
+}
+
+static void ti_watchdog(ifp)
+	struct ifnet		*ifp;
+{
+	struct ti_softc		*sc;
+
+	sc = ifp->if_softc;
+
+	printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname);
+	ti_stop(sc);
+	ti_init(sc);
+
+	ifp->if_oerrors++;
+
+	return;
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void ti_stop(sc)
+	struct ti_softc		*sc;
+{
+	struct ifnet		*ifp;
+	struct ti_cmd_desc	cmd;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/* Disable host interrupts. */
+	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
+	/*
+	 * Tell firmware we're shutting down.
+	 */
+	TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
+
+	/* Halt and reinitialize. */
+	ti_chipinit(sc);
+	ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
+	ti_chipinit(sc);
+
+	/* Free the RX lists. */
+	ti_free_rx_ring_std(sc);
+
+	/* Free jumbo RX list. */
+	ti_free_rx_ring_jumbo(sc);
+
+	/* Free mini RX list. */
+	ti_free_rx_ring_mini(sc);
+
+	/* Free TX buffers. */
+	ti_free_tx_ring(sc);
+
+	sc->ti_ev_prodidx.ti_idx = 0;
+	sc->ti_return_prodidx.ti_idx = 0;
+	sc->ti_tx_considx.ti_idx = 0;
+	sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
+
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+	return;
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static void ti_shutdown(xsc)
+	void			*xsc;
+{
+	struct ti_softc		*sc;
+
+	sc = xsc;
+
+	ti_chipinit(sc);
+
+	return;
+}
+
+struct cfattach ti_ca = {
+	sizeof(struct ti_softc), ti_probe, ti_attach
+};
+
+struct cfdriver ti_cd = {
+	0, "ti", DV_IFNET
+};
diff --git a/sys/dev/pci/if_tireg.h b/sys/dev/pci/if_tireg.h
new file mode 100644
index 00000000000..3914df541b0
--- /dev/null
+++ b/sys/dev/pci/if_tireg.h
@@ -0,0 +1,1192 @@
+/*	$OpenBSD: if_tireg.h,v 1.1 1999/07/25 16:51:55 jason Exp $	*/
+
+/*
+ * Copyright (c) 1997, 1998, 1999
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$FreeBSD: if_tireg.h,v 1.5 1999/07/05 20:19:41 wpaul Exp $
+ */
+
+/*
+ * Tigon register offsets. These are memory mapped registers
+ * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
+ * Each register must be accessed using 32 bit operations.
+ *
+ * All reegisters are accessed through a 16K shared memory block.
+ * The first group of registers are actually copies of the PCI
+ * configuration space registers.
+ */
+
+#define TI_PCI_ID			0x000 /* PCI device/vendor ID */
+#define TI_PCI_CMDSTAT			0x004
+#define TI_PCI_CLASSCODE		0x008
+#define TI_PCI_BIST			0x00C
+#define TI_PCI_LOMEM			0x010 /* Shared memory base address */
+#define TI_PCI_SUBSYS			0x02C
+#define TI_PCI_ROMBASE			0x030
+#define TI_PCI_INT			0x03C
+
+#ifndef PCIM_CMD_MWIEN
+#define PCIM_CMD_MWIEN			0x0010
+#endif
+
+/*
+ * Alteon AceNIC PCI vendor/device ID.
+ */
+#define ALT_VENDORID			0x12AE
+#define ALT_DEVICEID_ACENIC		0x0001
+
+/*
+ * 3Com 3c985 PCI vendor/device ID.
+ */
+#define TC_VENDORID			0x10B7
+#define TC_DEVICEID_3C985		0x0001
+
+/*
+ * Netgear GA620 PCI vendor/device ID.
+ */
+#define NG_VENDORID			0x1385
+#define NG_DEVICEID_GA620		0x620A
+
+/*
+ * SGI device/vendor ID.
+ */
+#define SGI_VENDORID			0x10A9
+#define SGI_DEVICEID_TIGON		0x0009
+
+/*
+ * Tigon configuration and control registers.
+ */
+#define TI_MISC_HOST_CTL		0x040
+#define TI_MISC_LOCAL_CTL		0x044
+#define TI_SEM_AB			0x048 /* Tigon 2 only */
+#define TI_MISC_CONF			0x050 /* Tigon 2 only */
+#define TI_TIMER_BITS			0x054
+#define TI_TIMERREF			0x058
+#define TI_PCI_STATE			0x05C
+#define TI_MAIN_EVENT_A			0x060
+#define TI_MAILBOX_EVENT_A		0x064
+#define TI_WINBASE			0x068
+#define TI_WINDATA			0x06C
+#define TI_MAIN_EVENT_B			0x070 /* Tigon 2 only */
+#define TI_MAILBOX_EVENT_B		0x074 /* Tigon 2 only */
+#define TI_TIMERREF_B			0x078 /* Tigon 2 only */
+#define TI_SERIAL			0x07C
+
+/*
+ * Misc host control bits.
+ */
+#define TI_MHC_INTSTATE			0x00000001
+#define TI_MHC_CLEARINT			0x00000002
+#define TI_MHC_RESET			0x00000008
+#define TI_MHC_BYTE_SWAP_ENB		0x00000010
+#define TI_MHC_WORD_SWAP_ENB		0x00000020
+#define TI_MHC_MASK_INTS		0x00000040
+#define TI_MHC_CHIP_REV_MASK		0xF0000000
+
+#define TI_MHC_BIGENDIAN_INIT	\
+	(TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
+
+#define TI_MHC_LITTLEENDIAN_INIT	\
+	(TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
+
+/*
+ * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
+ * Rev 5 is also the Tigon 2, but is a broken version which was never
+ * used in any actual hardware, so we ignore it.
+ */
+#define TI_REV_TIGON_I			0x40000000
+#define TI_REV_TIGON_II			0x60000000
+
+/*
+ * Firmware revision that we want.
+ */
+#define TI_FIRMWARE_MAJOR		0xc
+#define TI_FIRMWARE_MINOR		0x3
+#define TI_FIRMWARE_FIX			0xa
+
+/*
+ * Miscelaneous Local Control register.
+ */
+#define TI_MLC_EE_WRITE_ENB		0x00000010
+#define TI_MLC_SRAM_BANK_256K		0x00000200
+#define TI_MLC_SRAM_BANK_SIZE		0x00000300 /* Tigon 2 only */
+#define TI_MLC_LOCALADDR_21		0x00004000
+#define TI_MLC_LOCALADDR_22		0x00008000
+#define TI_MLC_SBUS_WRITEERR		0x00080000
+#define TI_MLC_EE_CLK			0x00100000
+#define TI_MLC_EE_TXEN			0x00200000
+#define TI_MLC_EE_DOUT			0x00400000
+#define TI_MLC_EE_DIN			0x00800000
+
+/*
+ * Offset of MAC address inside EEPROM.
+ */
+#define TI_EE_MAC_OFFSET		0x8c
+
+#define TI_DMA_ASSIST			0x11C
+#define TI_CPU_STATE			0x140
+#define TI_CPU_PROGRAM_COUNTER		0x144
+#define TI_SRAM_ADDR			0x154
+#define TI_SRAM_DATA			0x158
+#define TI_GEN_0			0x180
+#define TI_GEN_X			0x1FC
+#define TI_MAC_TX_STATE			0x200
+#define TI_MAC_RX_STATE			0x220
+#define TI_CPU_CTL_B			0x240 /* Tigon 2 only */
+#define TI_CPU_PROGRAM_COUNTER_B	0x244 /* Tigon 2 only */
+#define TI_SRAM_ADDR_B			0x254 /* Tigon 2 only */
+#define TI_SRAM_DATA_B			0x258 /* Tigon 2 only */
+#define TI_GEN_B_0			0x280 /* Tigon 2 only */
+#define TI_GEN_B_X			0x2FC /* Tigon 2 only */
+
+/*
+ * Misc config register.
+ */
+#define TI_MCR_SRAM_SYNCHRONOUS		0x00100000 /* Tigon 2 only */
+
+/*
+ * PCI state register.
+ */
+#define TI_PCISTATE_FORCE_RESET		0x00000001
+#define TI_PCISTATE_PROVIDE_LEN		0x00000002
+#define TI_PCISTATE_READ_MAXDMA		0x0000001C
+#define TI_PCISTATE_WRITE_MAXDMA	0x000000E0
+#define TI_PCISTATE_MINDMA		0x0000FF00
+#define TI_PCISTATE_FIFO_RETRY_ENB	0x00010000
+#define TI_PCISTATE_USE_MEM_RD_MULT	0x00020000
+#define TI_PCISTATE_NO_SWAP_READ_DMA	0x00040000
+#define TI_PCISTATE_NO_SWAP_WRITE_DMA	0x00080000
+#define TI_PCISTATE_66MHZ_BUS		0x00080000 /* Tigon 2 only */
+#define TI_PCISTATE_32BIT_BUS		0x00100000 /* Tigon 2 only */
+#define TI_PCISTATE_ENB_BYTE_ENABLES	0x00800000 /* Tigon 2 only */
+#define TI_PCISTATE_READ_CMD		0x0F000000
+#define TI_PCISTATE_WRITE_CMD		0xF0000000
+
+#define TI_PCI_READMAX_4		0x04
+#define TI_PCI_READMAX_16		0x08
+#define TI_PCI_READMAX_32		0x0C
+#define TI_PCI_READMAX_64		0x10
+#define TI_PCI_READMAX_128		0x14
+#define TI_PCI_READMAX_256		0x18
+#define TI_PCI_READMAX_1024		0x1C
+
+#define TI_PCI_WRITEMAX_4		0x20
+#define TI_PCI_WRITEMAX_16		0x40
+#define TI_PCI_WRITEMAX_32		0x60
+#define TI_PCI_WRITEMAX_64		0x80
+#define TI_PCI_WRITEMAX_128		0xA0
+#define TI_PCI_WRITEMAX_256		0xC0
+#define TI_PCI_WRITEMAX_1024		0xE0
+
+#define TI_PCI_READ_CMD			0x06000000
+#define TI_PCI_WRITE_CMD		0x70000000
+
+/*
+ * DMA state register.
+ */
+#define TI_DMASTATE_ENABLE		0x00000001
+#define TI_DMASTATE_PAUSE		0x00000002
+
+/*
+ * CPU state register.
+ */
+#define TI_CPUSTATE_RESET		0x00000001
+#define TI_CPUSTATE_STEP		0x00000002
+#define TI_CPUSTATE_ROMFAIL		0x00000010
+#define TI_CPUSTATE_HALT		0x00010000
+/*
+ * MAC TX state register
+ */
+#define TI_TXSTATE_RESET		0x00000001
+#define TI_TXSTATE_ENB			0x00000002
+#define TI_TXSTATE_STOP			0x00000004
+
+/*
+ * MAC RX state register
+ */
+#define TI_RXSTATE_RESET		0x00000001
+#define TI_RXSTATE_ENB			0x00000002
+#define TI_RXSTATE_STOP			0x00000004
+
+/*
+ * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
+ * split into 64 bit registers. Only the lower 32 bits of each mailbox
+ * are used.
+ */
+#define TI_MB_HOSTINTR_HI		0x500
+#define TI_MB_HOSTINTR_LO		0x504
+#define TI_MB_HOSTINTR			TI_MB_HOSTINTR_LO
+#define TI_MB_CMDPROD_IDX_HI		0x508
+#define TI_MB_CMDPROD_IDX_LO		0x50C
+#define TI_MB_CMDPROD_IDX		TI_MB_CMDPROD_IDX_LO
+#define TI_MB_SENDPROD_IDX_HI		0x510
+#define TI_MB_SENDPROD_IDX_LO		0x514
+#define TI_MB_SENDPROD_IDX		TI_MB_SENDPROD_IDX_LO
+#define TI_MB_STDRXPROD_IDX_HI		0x518 /* Tigon 2 only */
+#define TI_MB_STDRXPROD_IDX_LO		0x51C /* Tigon 2 only */
+#define TI_MB_STDRXPROD_IDX		TI_MB_STDRXPROD_IDX_LO
+#define TI_MB_JUMBORXPROD_IDX_HI	0x520 /* Tigon 2 only */
+#define TI_MB_JUMBORXPROD_IDX_LO	0x524 /* Tigon 2 only */
+#define TI_MB_JUMBORXPROD_IDX		TI_MB_JUMBORXPROD_IDX_LO
+#define TI_MB_MINIRXPROD_IDX_HI		0x528 /* Tigon 2 only */
+#define TI_MB_MINIRXPROD_IDX_LO		0x52C /* Tigon 2 only */
+#define TI_MB_MINIRXPROD_IDX		TI_MB_MINIRXPROD_IDX_LO
+#define TI_MB_RSVD			0x530
+
+/*
+ * Tigon 2 general communication registers. These are 64 and 32 bit
+ * registers which are only valid after the firmware has been
+ * loaded and started. They actually exist in NIC memory but are
+ * mapped into the host memory via the shared memory region.
+ *
+ * The NIC internally maps these registers starting at address 0,
+ * so to determine the NIC address of any of these registers, we
+ * subtract 0x600 (the address of the first register).
+ */
+
+#define TI_GCR_BASE			0x600
+#define TI_GCR_MACADDR			0x600
+#define TI_GCR_PAR0			0x600
+#define TI_GCR_PAR1			0x604
+#define TI_GCR_GENINFO_HI		0x608
+#define TI_GCR_GENINFO_LO		0x60C
+#define TI_GCR_MCASTADDR		0x610 /* obsolete */
+#define TI_GCR_MAR0			0x610 /* obsolete */
+#define TI_GCR_MAR1			0x614 /* obsolete */
+#define TI_GCR_OPMODE			0x618
+#define TI_GCR_DMA_READCFG		0x61C
+#define TI_GCR_DMA_WRITECFG		0x620
+#define TI_GCR_TX_BUFFER_RATIO		0x624
+#define TI_GCR_EVENTCONS_IDX		0x628
+#define TI_GCR_CMDCONS_IDX		0x62C
+#define TI_GCR_TUNEPARMS		0x630
+#define TI_GCR_RX_COAL_TICKS		0x630
+#define TI_GCR_TX_COAL_TICKS		0x634
+#define TI_GCR_STAT_TICKS		0x638
+#define TI_GCR_TX_MAX_COAL_BD		0x63C
+#define TI_GCR_RX_MAX_COAL_BD		0x640
+#define TI_GCR_NIC_TRACING		0x644
+#define TI_GCR_GLINK			0x648
+#define TI_GCR_LINK			0x64C
+#define TI_GCR_NICTRACE_PTR		0x650
+#define TI_GCR_NICTRACE_START		0x654
+#define TI_GCR_NICTRACE_LEN		0x658
+#define TI_GCR_IFINDEX			0x65C
+#define TI_GCR_IFMTU			0x660
+#define TI_GCR_MASK_INTRS		0x664
+#define TI_GCR_GLINK_STAT		0x668
+#define TI_GCR_LINK_STAT		0x66C
+#define TI_GCR_RXRETURNCONS_IDX		0x680
+#define TI_GCR_CMDRING			0x700
+
+#define TI_GCR_NIC_ADDR(x)		(x - TI_GCR_BASE);
+
+/*
+ * Local memory window. The local memory window is a 2K shared
+ * memory region which can be used to access the NIC's internal
+ * SRAM. The window can be mapped to a given 2K region using
+ * the TI_WINDOW_BASE register.
+ */
+#define TI_WINDOW			0x800
+#define TI_WINLEN			0x800
+
+#define TI_TICKS_PER_SEC		1000000
+
+/*
+ * Operation mode register.
+ */
+#define TI_OPMODE_BYTESWAP_BD		0x00000002
+#define TI_OPMODE_WORDSWAP_BD		0x00000004
+#define TI_OPMODE_WARN_ENB		0x00000008 /* not yet implimented */
+#define TI_OPMODE_BYTESWAP_DATA		0x00000010
+#define TI_OPMODE_1_DMA_ACTIVE		0x00000040
+#define TI_OPMODE_SBUS			0x00000100
+#define TI_OPMODE_DONT_FRAG_JUMBO	0x00000200
+#define TI_OPMODE_INCLUDE_CRC		0x00000400
+#define TI_OPMODE_RX_BADFRAMES		0x00000800
+#define TI_OPMODE_NO_EVENT_INTRS	0x00001000
+#define TI_OPMODE_NO_TX_INTRS		0x00002000
+#define TI_OPMODE_NO_RX_INTRS		0x00004000
+#define TI_OPMODE_FATAL_ENB		0x40000000 /* not yet implimented */
+
+/*
+ * DMA configuration thresholds.
+ */
+#define TI_DMA_STATE_THRESH_16W		0x00000100
+#define TI_DMA_STATE_THRESH_8W		0x00000080
+#define TI_DMA_STATE_THRESH_4W		0x00000040
+#define TI_DMA_STATE_THRESH_2W		0x00000020
+#define TI_DMA_STATE_THRESH_1W		0x00000010
+
+#define TI_DMA_STATE_FORCE_32_BIT	0x00000008
+
+/*
+ * Gigabit link status bits.
+ */
+#define TI_GLNK_SENSE_NO_BEG		0x00002000
+#define TI_GLNK_LOOPBACK		0x00004000
+#define TI_GLNK_PREF			0x00008000
+#define TI_GLNK_1000MB			0x00040000
+#define TI_GLNK_FULL_DUPLEX		0x00080000
+#define TI_GLNK_TX_FLOWCTL_Y		0x00200000 /* Tigon 2 only */
+#define TI_GLNK_RX_FLOWCTL_Y		0x00800000
+#define TI_GLNK_AUTONEGENB		0x20000000
+#define TI_GLNK_ENB			0x40000000
+
+/*
+ * Link status bits.
+ */
+#define TI_LNK_LOOPBACK			0x00004000
+#define TI_LNK_PREF			0x00008000
+#define TI_LNK_10MB			0x00010000
+#define TI_LNK_100MB			0x00020000
+#define TI_LNK_1000MB			0x00040000
+#define TI_LNK_FULL_DUPLEX		0x00080000
+#define TI_LNK_HALF_DUPLEX		0x00100000
+#define TI_LNK_TX_FLOWCTL_Y		0x00200000 /* Tigon 2 only */
+#define TI_LNK_RX_FLOWCTL_Y		0x00800000
+#define TI_LNK_AUTONEGENB		0x20000000
+#define TI_LNK_ENB			0x40000000
+
+/*
+ * Ring size constants.
+ */
+#define TI_EVENT_RING_CNT	256
+#define TI_CMD_RING_CNT		64
+#define TI_STD_RX_RING_CNT	512
+#define TI_JUMBO_RX_RING_CNT	256
+#define TI_MINI_RX_RING_CNT	1024
+#define TI_RETURN_RING_CNT	2048
+
+/*
+ * Possible TX ring sizes.
+ */
+#define TI_TX_RING_CNT_128	128
+#define TI_TX_RING_BASE_128	0x3800
+
+#define TI_TX_RING_CNT_256	256
+#define TI_TX_RING_BASE_256	0x3000
+
+#define TI_TX_RING_CNT_512	512
+#define TI_TX_RING_BASE_512	0x2000
+
+#define TI_TX_RING_CNT		TI_TX_RING_CNT_512
+#define TI_TX_RING_BASE		TI_TX_RING_BASE_512
+
+/*
+ * The Tigon can have up to 8MB of external SRAM, however the Tigon 1
+ * is limited to 2MB total, and in general I think most adapters have
+ * around 1MB. We use this value for zeroing the NIC's SRAM, so to
+ * be safe we use the largest possible value (zeroing memory that
+ * isn't there doesn't hurt anything).
+ */
+#define TI_MEM_MAX		0x7FFFFF
+
+/*
+ * Even on the alpha, pci addresses are 32-bit quantities
+ */
+
+#ifdef __64_bit_pci_addressing__ 
+typedef struct {
+	u_int64_t		ti_addr;
+} ti_hostaddr;
+#define TI_HOSTADDR(x)	x.ti_addr
+#else
+typedef struct {
+	u_int32_t		ti_addr_hi;
+	u_int32_t		ti_addr_lo;
+} ti_hostaddr;
+#define TI_HOSTADDR(x)	x.ti_addr_lo
+#endif
+
+/*
+ * Ring control block structure. The rules for the max_len field
+ * are as follows:
+ * 
+ * For the send ring, max_len indicates the number of entries in the
+ * ring (128, 256 or 512).
+ *
+ * For the standard receive ring, max_len indicates the threshold
+ * used to decide when a frame should be put in the jumbo receive ring
+ * instead of the standard one.
+ *
+ * For the mini ring, max_len indicates the size of the buffers in the
+ * ring. This is the value used to decide when a frame is small enough
+ * to be placed in the mini ring.
+ *
+ * For the return receive ring, max_len indicates the number of entries
+ * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
+ * 2048 for backwards compatibility). The value 1024 can only be used
+ * if the mini ring is disabled.
+ */
+struct ti_rcb {
+	ti_hostaddr		ti_hostaddr;
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_max_len;
+	u_int16_t		ti_flags;
+#else
+	u_int16_t		ti_flags;
+	u_int16_t		ti_max_len;
+#endif
+	u_int32_t		ti_unused;
+};
+
+#define TI_RCB_FLAG_TCP_UDP_CKSUM	0x00000001
+#define TI_RCB_FLAG_IP_CKSUM		0x00000002
+#define TI_RCB_FLAG_NO_PHDR_CKSUM	0x00000008
+#define TI_RCB_FLAG_VLAN_ASSIST		0x00000010
+#define TI_RCB_FLAG_COAL_UPD_ONLY	0x00000020
+#define TI_RCB_FLAG_HOST_RING		0x00000040
+#define TI_RCB_FLAG_IEEE_SNAP_CKSUM	0x00000080
+#define TI_RCB_FLAG_USE_EXT_RX_BD	0x00000100
+#define TI_RCB_FLAG_RING_DISABLED	0x00000200
+
+struct ti_producer {
+	u_int32_t		ti_idx;
+	u_int32_t		ti_unused;
+};
+
+/*
+ * Tigon statistics counters.
+ */
+struct ti_stats {
+	/*
+	 * MAC stats, taken from RFC 1643, ethernet-like MIB
+	 */
+	volatile u_int32_t dot3StatsAlignmentErrors;		/* 0 */
+	volatile u_int32_t dot3StatsFCSErrors;			/* 1 */
+	volatile u_int32_t dot3StatsSingleCollisionFrames;	/* 2 */
+	volatile u_int32_t dot3StatsMultipleCollisionFrames;	/* 3 */
+	volatile u_int32_t dot3StatsSQETestErrors;		/* 4 */
+	volatile u_int32_t dot3StatsDeferredTransmissions;	/* 5 */
+	volatile u_int32_t dot3StatsLateCollisions;		/* 6 */
+	volatile u_int32_t dot3StatsExcessiveCollisions;	/* 7 */
+	volatile u_int32_t dot3StatsInternalMacTransmitErrors;	/* 8 */
+	volatile u_int32_t dot3StatsCarrierSenseErrors;		/* 9 */
+	volatile u_int32_t dot3StatsFrameTooLongs;		/* 10 */
+	volatile u_int32_t dot3StatsInternalMacReceiveErrors;	/* 11 */
+	/*
+	 * interface stats, taken from RFC 1213, MIB-II, interfaces group
+	 */
+	volatile u_int32_t ifIndex;				/* 12 */
+	volatile u_int32_t ifType;				/* 13 */
+	volatile u_int32_t ifMtu;				/* 14 */
+	volatile u_int32_t ifSpeed;				/* 15 */
+	volatile u_int32_t ifAdminStatus;			/* 16 */
+#define IF_ADMIN_STATUS_UP      1
+#define IF_ADMIN_STATUS_DOWN    2
+#define IF_ADMIN_STATUS_TESTING 3
+	volatile u_int32_t ifOperStatus;			/* 17 */
+#define IF_OPER_STATUS_UP       1
+#define IF_OPER_STATUS_DOWN     2
+#define IF_OPER_STATUS_TESTING  3
+#define IF_OPER_STATUS_UNKNOWN  4
+#define IF_OPER_STATUS_DORMANT  5
+	volatile u_int32_t ifLastChange;			/* 18 */
+	volatile u_int32_t ifInDiscards;			/* 19 */
+	volatile u_int32_t ifInErrors;				/* 20 */
+	volatile u_int32_t ifInUnknownProtos;			/* 21 */
+	volatile u_int32_t ifOutDiscards;			/* 22 */
+	volatile u_int32_t ifOutErrors;				/* 23 */
+	volatile u_int32_t ifOutQLen;     /* deprecated */	/* 24 */
+	volatile u_int8_t  ifPhysAddress[8]; /* 8 bytes */	/* 25 - 26 */
+	volatile u_int8_t  ifDescr[32];				/* 27 - 34 */
+	u_int32_t alignIt;      /* align to 64 bit for u_int64_ts following */
+	/*
+	 * more interface stats, taken from RFC 1573, MIB-IIupdate,
+	 * interfaces group
+	 */
+	volatile u_int64_t ifHCInOctets;			/* 36 - 37 */
+	volatile u_int64_t ifHCInUcastPkts;			/* 38 - 39 */
+	volatile u_int64_t ifHCInMulticastPkts;			/* 40 - 41 */
+	volatile u_int64_t ifHCInBroadcastPkts;			/* 42 - 43 */
+	volatile u_int64_t ifHCOutOctets;			/* 44 - 45 */
+	volatile u_int64_t ifHCOutUcastPkts;			/* 46 - 47 */
+	volatile u_int64_t ifHCOutMulticastPkts;		/* 48 - 49 */
+	volatile u_int64_t ifHCOutBroadcastPkts;		/* 50 - 51 */
+	volatile u_int32_t ifLinkUpDownTrapEnable;		/* 52 */
+	volatile u_int32_t ifHighSpeed;				/* 53 */
+	volatile u_int32_t ifPromiscuousMode; 			/* 54 */
+	volatile u_int32_t ifConnectorPresent; /* follow link state 55 */
+	/*
+	 * Host Commands
+	 */
+	volatile u_int32_t nicCmdsHostState;			/* 56 */
+	volatile u_int32_t nicCmdsFDRFiltering;			/* 57 */
+	volatile u_int32_t nicCmdsSetRecvProdIndex;		/* 58 */
+	volatile u_int32_t nicCmdsUpdateGencommStats;		/* 59 */
+	volatile u_int32_t nicCmdsResetJumboRing;		/* 60 */
+	volatile u_int32_t nicCmdsAddMCastAddr;			/* 61 */
+	volatile u_int32_t nicCmdsDelMCastAddr;			/* 62 */
+	volatile u_int32_t nicCmdsSetPromiscMode;		/* 63 */
+	volatile u_int32_t nicCmdsLinkNegotiate;		/* 64 */
+	volatile u_int32_t nicCmdsSetMACAddr;			/* 65 */
+	volatile u_int32_t nicCmdsClearProfile;			/* 66 */
+	volatile u_int32_t nicCmdsSetMulticastMode;		/* 67 */
+	volatile u_int32_t nicCmdsClearStats;			/* 68 */
+	volatile u_int32_t nicCmdsSetRecvJumboProdIndex;	/* 69 */
+	volatile u_int32_t nicCmdsSetRecvMiniProdIndex;		/* 70 */
+	volatile u_int32_t nicCmdsRefreshStats;			/* 71 */
+	volatile u_int32_t nicCmdsUnknown;			/* 72 */
+	/*
+	 * NIC Events
+	 */
+	volatile u_int32_t nicEventsNICFirmwareOperational;	/* 73 */
+	volatile u_int32_t nicEventsStatsUpdated;		/* 74 */
+	volatile u_int32_t nicEventsLinkStateChanged;		/* 75 */
+	volatile u_int32_t nicEventsError;			/* 76 */
+	volatile u_int32_t nicEventsMCastListUpdated;		/* 77 */
+	volatile u_int32_t nicEventsResetJumboRing;		/* 78 */
+	/*
+	 * Ring manipulation
+	 */
+	volatile u_int32_t nicRingSetSendProdIndex;		/* 79 */
+	volatile u_int32_t nicRingSetSendConsIndex;		/* 80 */
+	volatile u_int32_t nicRingSetRecvReturnProdIndex;	/* 81 */
+	/*
+	 * Interrupts
+	 */
+	volatile u_int32_t nicInterrupts;			/* 82 */
+	volatile u_int32_t nicAvoidedInterrupts;		/* 83 */
+	/*
+	 * BD Coalessing Thresholds
+	 */
+	volatile u_int32_t nicEventThresholdHit;		/* 84 */
+	volatile u_int32_t nicSendThresholdHit;			/* 85 */
+	volatile u_int32_t nicRecvThresholdHit;			/* 86 */
+	/*
+	 * DMA Attentions
+	 */
+	volatile u_int32_t nicDmaRdOverrun;			/* 87 */
+	volatile u_int32_t nicDmaRdUnderrun;			/* 88 */
+	volatile u_int32_t nicDmaWrOverrun;			/* 89 */
+	volatile u_int32_t nicDmaWrUnderrun;			/* 90 */
+	volatile u_int32_t nicDmaWrMasterAborts;		/* 91 */
+	volatile u_int32_t nicDmaRdMasterAborts;		/* 92 */
+	/*
+	 * NIC Resources
+	 */
+	volatile u_int32_t nicDmaWriteRingFull;			/* 93 */
+	volatile u_int32_t nicDmaReadRingFull;			/* 94 */
+	volatile u_int32_t nicEventRingFull;			/* 95 */
+	volatile u_int32_t nicEventProducerRingFull;		/* 96 */
+	volatile u_int32_t nicTxMacDescrRingFull;		/* 97 */
+	volatile u_int32_t nicOutOfTxBufSpaceFrameRetry;	/* 98 */
+	volatile u_int32_t nicNoMoreWrDMADescriptors;		/* 99 */
+	volatile u_int32_t nicNoMoreRxBDs;			/* 100 */
+	volatile u_int32_t nicNoSpaceInReturnRing;		/* 101 */
+	volatile u_int32_t nicSendBDs;            /* current count 102 */
+	volatile u_int32_t nicRecvBDs;            /* current count 103 */
+	volatile u_int32_t nicJumboRecvBDs;       /* current count 104 */
+	volatile u_int32_t nicMiniRecvBDs;        /* current count 105 */
+	volatile u_int32_t nicTotalRecvBDs;       /* current count 106 */
+	volatile u_int32_t nicTotalSendBDs;       /* current count 107 */
+	volatile u_int32_t nicJumboSpillOver;			/* 108 */
+	volatile u_int32_t nicSbusHangCleared;			/* 109 */
+	volatile u_int32_t nicEnqEventDelayed;			/* 110 */
+	/*
+	 * Stats from MAC rx completion
+	 */
+	volatile u_int32_t nicMacRxLateColls;			/* 111 */
+	volatile u_int32_t nicMacRxLinkLostDuringPkt;		/* 112 */
+	volatile u_int32_t nicMacRxPhyDecodeErr;		/* 113 */
+	volatile u_int32_t nicMacRxMacAbort;			/* 114 */
+	volatile u_int32_t nicMacRxTruncNoResources;		/* 115 */
+	/*
+	 * Stats from the mac_stats area
+	 */
+	volatile u_int32_t nicMacRxDropUla;			/* 116 */
+	volatile u_int32_t nicMacRxDropMcast;			/* 117 */
+	volatile u_int32_t nicMacRxFlowControl;			/* 118 */
+	volatile u_int32_t nicMacRxDropSpace;			/* 119 */
+	volatile u_int32_t nicMacRxColls;			/* 120 */
+	/*
+ 	 * MAC RX Attentions
+	 */
+	volatile u_int32_t nicMacRxTotalAttns;			/* 121 */
+	volatile u_int32_t nicMacRxLinkAttns;			/* 122 */
+	volatile u_int32_t nicMacRxSyncAttns;			/* 123 */
+	volatile u_int32_t nicMacRxConfigAttns;			/* 124 */
+	volatile u_int32_t nicMacReset;				/* 125 */
+	volatile u_int32_t nicMacRxBufDescrAttns;		/* 126 */
+	volatile u_int32_t nicMacRxBufAttns;			/* 127 */
+	volatile u_int32_t nicMacRxZeroFrameCleanup;		/* 128 */
+	volatile u_int32_t nicMacRxOneFrameCleanup;		/* 129 */
+	volatile u_int32_t nicMacRxMultipleFrameCleanup;	/* 130 */
+	volatile u_int32_t nicMacRxTimerCleanup;		/* 131 */
+	volatile u_int32_t nicMacRxDmaCleanup;			/* 132 */
+	/*
+	 * Stats from the mac_stats area
+	 */
+	volatile u_int32_t nicMacTxCollisionHistogram[15];	/* 133 */
+	/*
+	 * MAC TX Attentions
+	 */
+	volatile u_int32_t nicMacTxTotalAttns;			/* 134 */
+	/*
+	 * NIC Profile
+	 */
+	volatile u_int32_t nicProfile[32];			/* 135 */
+	/*
+	 * Pat to 1024 bytes.
+	 */
+	u_int32_t		pad[75];
+};
+/*
+ * Tigon general information block. This resides in host memory
+ * and contains the status counters, ring control blocks and
+ * producer pointers.
+ */
+
+struct ti_gib {
+	struct ti_stats		ti_stats;
+	struct ti_rcb		ti_ev_rcb;
+	struct ti_rcb		ti_cmd_rcb;
+	struct ti_rcb		ti_tx_rcb;
+	struct ti_rcb		ti_std_rx_rcb;
+	struct ti_rcb		ti_jumbo_rx_rcb;
+	struct ti_rcb		ti_mini_rx_rcb;
+	struct ti_rcb		ti_return_rcb;
+	ti_hostaddr		ti_ev_prodidx_ptr;
+	ti_hostaddr		ti_return_prodidx_ptr;
+	ti_hostaddr		ti_tx_considx_ptr;
+	ti_hostaddr		ti_refresh_stats_ptr;
+};
+
+/*
+ * Buffer descriptor structures. There are basically three types
+ * of structures: normal receive descriptors, extended receive
+ * descriptors and transmit descriptors. The extended receive
+ * descriptors are optionally used only for the jumbo receive ring.
+ */
+
+struct ti_rx_desc {
+	ti_hostaddr		ti_addr;
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_idx;
+	u_int16_t		ti_len;
+#else
+	u_int16_t		ti_len;
+	u_int16_t		ti_idx;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_type;
+	u_int16_t		ti_flags;
+#else
+	u_int16_t		ti_flags;
+	u_int16_t		ti_type;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_ip_cksum;
+	u_int16_t		ti_tcp_udp_cksum;
+#else
+	u_int16_t		ti_tcp_udp_cksum;
+	u_int16_t		ti_ip_cksum;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_error_flags;
+	u_int16_t		ti_vlan_tag;
+#else
+	u_int16_t		ti_vlan_tag;
+	u_int16_t		ti_error_flags;
+#endif
+	u_int32_t		ti_rsvd;
+	u_int32_t		ti_opaque;
+};
+
+struct ti_rx_desc_ext {
+	ti_hostaddr		ti_addr1;
+	ti_hostaddr		ti_addr2;
+	ti_hostaddr		ti_addr3;
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_len1;
+	u_int16_t		ti_len2;
+#else
+	u_int16_t		ti_len2;
+	u_int16_t		ti_len1;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_len3;
+	u_int16_t		ti_rsvd0;
+#else
+	u_int16_t		ti_rsvd0;
+	u_int16_t		ti_len3;
+#endif
+	ti_hostaddr		ti_addr0;
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_idx;
+	u_int16_t		ti_len0;
+#else
+	u_int16_t		ti_len0;
+	u_int16_t		ti_idx;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_type;
+	u_int16_t		ti_flags;
+#else
+	u_int16_t		ti_flags;
+	u_int16_t		ti_type;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_ip_cksum;
+	u_int16_t		ti_tcp_udp_cksum;
+#else
+	u_int16_t		ti_tcp_udp_cksum;
+	u_int16_t		ti_ip_cksum;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_error_flags;
+	u_int16_t		ti_vlan_tag;
+#else
+	u_int16_t		ti_vlan_tag;
+	u_int16_t		ti_error_flags;
+#endif
+	u_int32_t		ti_rsvd1;
+	u_int32_t		ti_opaque;
+};
+
+/*
+ * Transmit descriptors are, mercifully, very small.
+ */
+struct ti_tx_desc {
+	ti_hostaddr		ti_addr;
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_len;
+	u_int16_t		ti_flags;
+#else
+	u_int16_t		ti_flags;
+	u_int16_t		ti_len;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int16_t		ti_rsvd;
+	u_int16_t		ti_vlan_tag;
+#else
+	u_int16_t		ti_vlan_tag;
+	u_int16_t		ti_rsvd;
+#endif
+};
+
+/*
+ * NOTE!  On the Alpha, we have an alignment constraint.
+ * The first thing in the packet is a 14-byte Ethernet header.
+ * This means that the packet is misaligned.  To compensate,
+ * we actually offset the data 2 bytes into the cluster.  This
+ * alignes the packet after the Ethernet header at a 32-bit
+ * boundary.
+ */
+
+#ifdef __alpha__
+#define ETHER_ALIGN 2
+#endif
+
+#ifdef __i386__
+#define ETHER_ALIGN 0
+#endif
+
+
+#define TI_FRAMELEN		1518
+#define TI_JUMBO_FRAMELEN	9018 + ETHER_ALIGN
+#define TI_JUMBO_MTU		(TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define TI_PAGE_SIZE		PAGE_SIZE
+#define TI_MIN_FRAMELEN		60
+
+/*
+ * Buffer descriptor error flags.
+ */
+#define TI_BDERR_CRC			0x0001
+#define TI_BDERR_COLLDETECT		0x0002
+#define TI_BDERR_LINKLOST		0x0004
+#define TI_BDERR_DECODE			0x0008
+#define TI_BDERR_ODD_NIBBLES		0x0010
+#define TI_BDERR_MAC_ABRT		0x0020
+#define TI_BDERR_RUNT			0x0040
+#define TI_BDERR_TRUNC			0x0080
+#define TI_BDERR_GIANT			0x0100
+
+/*
+ * Buffer descriptor flags.
+ */
+#define TI_BDFLAG_TCP_UDP_CKSUM		0x0001
+#define TI_BDFLAG_IP_CKSUM		0x0002
+#define TI_BDFLAG_END			0x0004
+#define TI_BDFLAG_MORE			0x0008
+#define TI_BDFLAG_JUMBO_RING		0x0010
+#define TI_BDFLAG_UCAST_PKT		0x0020
+#define TI_BDFLAG_MCAST_PKT		0x0040
+#define TI_BDFLAG_BCAST_PKT		0x0060
+#define TI_BDFLAG_IP_FRAG		0x0080
+#define TI_BDFLAG_IP_FRAG_END		0x0100
+#define TI_BDFLAG_VLAN_TAG		0x0200
+#define TI_BDFLAG_ERROR			0x0400
+#define TI_BDFLAG_COAL_NOW		0x0800
+#define	TI_BDFLAG_MINI_RING		0x1000
+
+/*
+ * Descriptor type flags. I think these only have meaning for
+ * the Tigon 1. I had to extract them from the sample driver source
+ * since they aren't in the manual.
+ */
+#define TI_BDTYPE_TYPE_NULL			0x0000
+#define TI_BDTYPE_SEND_BD			0x0001
+#define TI_BDTYPE_RECV_BD			0x0002
+#define TI_BDTYPE_RECV_JUMBO_BD			0x0003
+#define TI_BDTYPE_RECV_BD_LAST			0x0004
+#define TI_BDTYPE_SEND_DATA			0x0005
+#define TI_BDTYPE_SEND_DATA_LAST		0x0006
+#define TI_BDTYPE_RECV_DATA			0x0007
+#define TI_BDTYPE_RECV_DATA_LAST		0x000b
+#define TI_BDTYPE_EVENT_RUPT			0x000c
+#define TI_BDTYPE_EVENT_NO_RUPT			0x000d
+#define TI_BDTYPE_ODD_START			0x000e
+#define TI_BDTYPE_UPDATE_STATS			0x000f
+#define TI_BDTYPE_SEND_DUMMY_DMA		0x0010
+#define TI_BDTYPE_EVENT_PROD			0x0011
+#define TI_BDTYPE_TX_CONS			0x0012
+#define TI_BDTYPE_RX_PROD			0x0013
+#define TI_BDTYPE_REFRESH_STATS			0x0014
+#define TI_BDTYPE_SEND_DATA_LAST_VLAN		0x0015
+#define TI_BDTYPE_SEND_DATA_COAL		0x0016
+#define TI_BDTYPE_SEND_DATA_LAST_COAL		0x0017
+#define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL	0x0018
+#define TI_BDTYPE_TX_CONS_NO_INTR		0x0019
+
+/*
+ * Tigon command structure.
+ */
+struct ti_cmd_desc {
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int32_t		ti_cmd:8;
+	u_int32_t		ti_code:12;
+	u_int32_t		ti_idx:12;
+#else
+	u_int32_t		ti_idx:12;
+	u_int32_t		ti_code:12;
+	u_int32_t		ti_cmd:8;
+#endif
+};
+
+#define TI_CMD_HOST_STATE		0x01
+#define TI_CMD_CODE_STACK_UP		0x01
+#define TI_CMD_CODE_STACK_DOWN		0x02
+
+/*
+ * This command enables software address filtering. It's a workaround
+ * for a bug in the Tigon 1 and not implemented for the Tigon 2.
+ */
+#define TI_CMD_FDR_FILTERING		0x02
+#define TI_CMD_CODE_FILT_ENB		0x01
+#define TI_CMD_CODE_FILT_DIS		0x02
+
+#define TI_CMD_SET_RX_PROD_IDX		0x03 /* obsolete */
+#define TI_CMD_UPDATE_GENCOM		0x04
+#define TI_CMD_RESET_JUMBO_RING		0x05
+#define TI_CMD_SET_PARTIAL_RX_CNT	0x06
+#define TI_CMD_ADD_MCAST_ADDR		0x08 /* obsolete */
+#define TI_CMD_DEL_MCAST_ADDR		0x09 /* obsolete */
+
+#define TI_CMD_SET_PROMISC_MODE		0x0A
+#define TI_CMD_CODE_PROMISC_ENB		0x01
+#define TI_CMD_CODE_PROMISC_DIS		0x02
+
+#define TI_CMD_LINK_NEGOTIATION		0x0B
+#define TI_CMD_CODE_NEGOTIATE_BOTH	0x00
+#define TI_CMD_CODE_NEGOTIATE_GIGABIT	0x01
+#define TI_CMD_CODE_NEGOTIATE_10_100	0x02
+
+#define TI_CMD_SET_MAC_ADDR		0x0C
+#define TI_CMD_CLR_PROFILE		0x0D
+
+#define TI_CMD_SET_ALLMULTI		0x0E
+#define TI_CMD_CODE_ALLMULTI_ENB	0x01
+#define TI_CMD_CODE_ALLMULTI_DIS	0x02
+
+#define TI_CMD_CLR_STATS		0x0F
+#define TI_CMD_SET_RX_JUMBO_PROD_IDX	0x10 /* obsolete */
+#define TI_CMD_RFRSH_STATS		0x11
+
+#define TI_CMD_EXT_ADD_MCAST		0x12
+#define TI_CMD_EXT_DEL_MCAST		0x13
+
+/*
+ * Utility macros to make issuing commands a little simpler. Assumes
+ * that 'sc' and 'cmd' are in local scope.
+ */
+#define TI_DO_CMD(x, y, z)		\
+	cmd.ti_cmd = x;			\
+	cmd.ti_code = y;		\
+	cmd.ti_idx = z;			\
+	ti_cmd(sc, &cmd);
+
+#define TI_DO_CMD_EXT(x, y, z, v, w)	\
+	cmd.ti_cmd = x;			\
+	cmd.ti_code = y;		\
+	cmd.ti_idx = z;			\
+	ti_cmd_ext(sc, &cmd, v, w);
+
+/*
+ * Other utility macros.
+ */
+#define TI_INC(x, y)	(x) = (x + 1) % y
+
+#define TI_UPDATE_JUMBOPROD(x, y)					\
+	if (x->ti_hwrev == TI_HWREV_TIGON) {				\
+		TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y);	\
+	} else {							\
+		CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y);		\
+	}
+
+#define TI_UPDATE_MINIPROD(x, y)					\
+		CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y);
+
+#define TI_UPDATE_STDPROD(x, y)						\
+	if (x->ti_hwrev == TI_HWREV_TIGON) {				\
+		TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y);		\
+	} else {							\
+		CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y);			\
+	}
+
+
+/*
+ * Tigon event structure.
+ */
+struct ti_event_desc {
+#if BYTE_ORDER == BIG_ENDIAN
+	u_int32_t		ti_event:8;
+	u_int32_t		ti_code:12;
+	u_int32_t		ti_idx:12;
+#else
+	u_int32_t		ti_idx:12;
+	u_int32_t		ti_code:12;
+	u_int32_t		ti_event:8;
+#endif
+	u_int32_t		ti_rsvd;
+};
+
+/*
+ * Tigon events.
+ */
+#define TI_EV_FIRMWARE_UP		0x01
+#define TI_EV_STATS_UPDATED		0x04
+
+#define TI_EV_LINKSTAT_CHANGED		0x06
+#define TI_EV_CODE_GIG_LINK_UP		0x01
+#define TI_EV_CODE_LINK_DOWN		0x02
+#define TI_EV_CODE_LINK_UP		0x03
+
+#define TI_EV_ERROR			0x07
+#define TI_EV_CODE_ERR_INVAL_CMD	0x01
+#define TI_EV_CODE_ERR_UNIMP_CMD	0x02
+#define TI_EV_CODE_ERR_BADCFG		0x03
+
+#define TI_EV_MCAST_UPDATED		0x08
+#define TI_EV_CODE_MCAST_ADD		0x01
+#define TI_EV_CODE_MCAST_DEL		0x02
+
+#define TI_EV_RESET_JUMBO_RING		0x09
+/*
+ * Register access macros. The Tigon always uses memory mapped register
+ * accesses and all registers must be accessed with 32 bit operations.
+ */
+
+#define CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg)		\
+	bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg)
+
+#define TI_SETBIT(sc, reg, x)	\
+	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
+#define TI_CLRBIT(sc, reg, x)	\
+	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
+
+/*
+ * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
+ * values are tuneable. They control the actual amount of buffers
+ * allocated for the standard, mini and jumbo receive rings.
+ */
+
+#define TI_SSLOTS	256
+#define TI_MSLOTS	256
+#define TI_JSLOTS	256
+
+#define TI_JRAWLEN (TI_JUMBO_FRAMELEN + sizeof(u_int64_t))
+#define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \
+	(TI_JRAWLEN % sizeof(u_int64_t))))
+#define TI_JPAGESZ PAGE_SIZE
+#define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ)
+#define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID)
+
+struct ti_jslot {
+	caddr_t			ti_buf;
+	int			ti_inuse;
+};
+
+/*
+ * Ring structures. Most of these reside in host memory and we tell
+ * the NIC where they are via the ring control blocks. The exceptions
+ * are the tx and command rings, which live in NIC memory and which
+ * we access via the shared memory window.
+ */
+struct ti_ring_data {
+	struct ti_rx_desc	ti_rx_std_ring[TI_STD_RX_RING_CNT];
+	struct ti_rx_desc	ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT];
+	struct ti_rx_desc	ti_rx_mini_ring[TI_MINI_RX_RING_CNT];
+	struct ti_rx_desc	ti_rx_return_ring[TI_RETURN_RING_CNT];
+	struct ti_event_desc	ti_event_ring[TI_EVENT_RING_CNT];
+	struct ti_tx_desc	ti_tx_ring[TI_TX_RING_CNT];
+	/*
+	 * Make sure producer structures are aligned on 32-byte cache
+	 * line boundaries.
+	 */
+	struct ti_producer	ti_ev_prodidx_r;
+	u_int32_t		ti_pad0[6];
+	struct ti_producer	ti_return_prodidx_r;
+	u_int32_t		ti_pad1[6];
+	struct ti_producer	ti_tx_considx_r;
+	u_int32_t		ti_pad2[6];
+	struct ti_tx_desc	*ti_tx_ring_nic;/* pointer to shared mem */
+	struct ti_cmd_desc	*ti_cmd_ring;	/* pointer to shared mem */
+	struct ti_gib		ti_info;
+};
+
+/*
+ * Mbuf pointers. We need these to keep track of the virtual addresses
+ * of our mbuf chains since we can only convert from physical to virtual,
+ * not the other way around.
+ */
+struct ti_chain_data {
+	struct mbuf		*ti_tx_chain[TI_TX_RING_CNT];
+	struct mbuf		*ti_rx_std_chain[TI_STD_RX_RING_CNT];
+	struct mbuf		*ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT];
+	struct mbuf		*ti_rx_mini_chain[TI_MINI_RX_RING_CNT];
+	/* Stick the jumbo mem management stuff here too. */
+	struct ti_jslot		ti_jslots[TI_JSLOTS];
+	void			*ti_jumbo_buf;
+};
+
+struct ti_type {
+	u_int16_t		ti_vid;
+	u_int16_t		ti_did;
+	char			*ti_name;
+};
+
+#define TI_HWREV_TIGON		0x01
+#define TI_HWREV_TIGON_II	0x02
+#define TI_TIMEOUT		1000
+#define TI_TXCONS_UNSET		0xFFFF	/* impossible value */
+
+struct ti_mc_entry {
+	struct ether_addr		mc_addr;
+	LIST_ENTRY(ti_mc_entry)		mc_entries;
+};
+
+struct ti_jpool_entry {
+	int                             slot;
+	LIST_ENTRY(ti_jpool_entry)	jpool_entries;
+};
+
+struct ti_softc {
+	struct device		sc_dv;
+	void *			sc_ih;
+	struct arpcom		arpcom;		/* interface info */
+	bus_space_handle_t	ti_bhandle;
+	bus_space_tag_t		ti_btag;
+	struct ifmedia		ifmedia;	/* media info */
+	u_int8_t		ti_hwrev;	/* Tigon rev (1 or 2) */
+	u_int8_t		ti_linkstat;	/* Link state */
+	caddr_t			ti_rdata_ptr;	/* Raw ring data */
+	struct ti_ring_data	*ti_rdata;	/* rings */
+	struct ti_chain_data	ti_cdata;	/* mbufs */
+#define ti_ev_prodidx		ti_rdata->ti_ev_prodidx_r
+#define ti_return_prodidx	ti_rdata->ti_return_prodidx_r
+#define ti_tx_considx		ti_rdata->ti_tx_considx_r
+	u_int16_t		ti_tx_saved_considx;
+	u_int16_t		ti_rx_saved_considx;
+	u_int16_t		ti_ev_saved_considx;
+	u_int16_t		ti_cmd_saved_prodidx;
+	u_int16_t		ti_std;		/* current std ring head */
+	u_int16_t		ti_mini;	/* current mini ring head */
+	u_int16_t		ti_jumbo;	/* current jumo ring head */
+	LIST_HEAD(__ti_mchead, ti_mc_entry)	ti_mc_listhead;
+	LIST_HEAD(__ti_jfreehead, ti_jpool_entry)	ti_jfree_listhead;
+	LIST_HEAD(__ti_jinusehead, ti_jpool_entry)	ti_jinuse_listhead;
+	u_int32_t		ti_stat_ticks;
+	u_int32_t		ti_rx_coal_ticks;
+	u_int32_t		ti_tx_coal_ticks;
+	u_int32_t		ti_rx_max_coal_bds;
+	u_int32_t		ti_tx_max_coal_bds;
+	u_int32_t		ti_tx_buf_ratio;
+	int			ti_if_flags;
+	int			ti_txcnt;
+};
+
+/*
+ * Microchip Technology 24Cxx EEPROM control bytes
+ */
+#define EEPROM_CTL_READ			0xA1	/* 0101 0001 */
+#define EEPROM_CTL_WRITE		0xA0	/* 0101 0000 */
+
+/*
+ * Note that EEPROM_START leaves transmission enabled.
+ */
+#define EEPROM_START							\
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */	\
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */
+
+/*
+ * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
+ * that no further data can be written to the EEPROM I/O pin.
+ */
+#define EEPROM_STOP							\
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */	\
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */	\
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */	\
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */	\
+	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */	\
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */	\
+	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */
+
+#ifdef __alpha__
+#undef vtophys
+#define vtophys(va)     (pmap_kextract(((vm_offset_t) (va))) \
+                         + 1*1024*1024*1024)
+#endif
+
+#ifndef ETHER_CRC_LEN
+#define ETHER_CRC_LEN	4
+#endif
+
+#ifndef ETHER_HDR_LEN
+#define	ETHER_HDR_LEN	14
+#endif
diff --git a/sys/dev/pci/ti_fw.h b/sys/dev/pci/ti_fw.h
new file mode 100644
index 00000000000..3543403d7fa
--- /dev/null
+++ b/sys/dev/pci/ti_fw.h
@@ -0,0 +1,4461 @@
+/*	$OpenBSD: ti_fw.h,v 1.1 1999/07/25 16:51:55 jason Exp $	*/
+
+/*
+ * Firmware for Alteon Tigon 1 chip.
+ * Generated by genfw.c
+ *
+ *      $FreeBSD: ti_fw.h,v 1.2 1999/05/03 17:44:53 wpaul Exp $
+ */
+static int tigonFwReleaseMajor = 0xc;
+static int tigonFwReleaseMinor = 0x3;
+static int tigonFwReleaseFix = 0xa;
+static u_int32_t tigonFwStartAddr = 0x00004000;
+static u_int32_t tigonFwTextAddr = 0x00004000;
+static int tigonFwTextLen = 0x10920;
+static u_int32_t tigonFwRodataAddr = 0x00014920;
+static int tigonFwRodataLen = 0xaa0;
+static u_int32_t tigonFwDataAddr = 0x000153e0;
+static int tigonFwDataLen = 0x150;
+static u_int32_t tigonFwSbssAddr = 0x00015530;
+static int tigonFwSbssLen = 0x2c;
+static u_int32_t tigonFwBssAddr = 0x00015560;
+static int tigonFwBssLen = 0x2080;
+static u_int32_t tigonFwText[] = {
+0x10000003, 
+0x0, 0xd, 0xd, 0x3c1d0001, 
+0x8fbd5414, 0x3a0f021, 0x3c100000, 0x26104000, 
+0xc00100c, 0x0, 0xd, 0x27bdffd8, 
+0x3c1cc000, 0x3c1b0013, 0x377bd800, 0xd021, 
+0x3c170013, 0x36f75418, 0x2e02021, 0x340583e8, 
+0xafbf0024, 0xc00248c, 0xafb00020, 0xc0023ec, 
+0x0, 0x3c040001, 0x24844984, 0x24050001, 
+0x2e03021, 0x3821, 0x3c100001, 0x261075e0, 
+0xafb00010, 0xc002407, 0xafbb0014, 0x3c02000f, 
+0x3442ffff, 0x2021024, 0x362102b, 0x10400009, 
+0x24050003, 0x3c040001, 0x24844990, 0x2003021, 
+0x3603821, 0x3c020010, 0xafa20010, 0xc002407, 
+0xafa00014, 0x2021, 0x3405c000, 0x3c010001, 
+0x370821, 0xa02083b0, 0x3c010001, 0x370821, 
+0xa02083b2, 0x3c010001, 0x370821, 0xa02083b3, 
+0x3c010001, 0x370821, 0xac2083b4, 0xa2e004d8, 
+0x418c0, 0x24840001, 0x771021, 0xac40727c, 
+0x771021, 0xac407280, 0x2e31021, 0xa445727c, 
+0x2c820020, 0x1440fff7, 0x418c0, 0x2021, 
+0x3405c000, 0x418c0, 0x24840001, 0x771021, 
+0xac40737c, 0x771021, 0xac407380, 0x2e31021, 
+0xa445737c, 0x2c820080, 0x5440fff7, 0x418c0, 
+0xaf800054, 0xaf80011c, 0x8f820044, 0x34420040, 
+0xaf820044, 0x8f820044, 0x34420020, 0xaf820044, 
+0x8f420218, 0x30420002, 0x10400009, 0x0, 
+0x8f420220, 0x3c030002, 0x34630004, 0x431025, 
+0xaee204c4, 0x8f42021c, 0x8001074, 0x34420004, 
+0x8f420220, 0x3c030002, 0x34630006, 0x431025, 
+0xaee204c4, 0x8f42021c, 0x34420006, 0xaee204cc, 
+0x8f420218, 0x30420010, 0x1040000a, 0x0, 
+0x8f42021c, 0x34420004, 0xaee204c8, 0x8f420220, 
+0x3c03000a, 0x34630004, 0x431025, 0x800108a, 
+0xaee204c0, 0x8f420220, 0x3c03000a, 0x34630006, 
+0x431025, 0xaee204c0, 0x8f42021c, 0x34420006, 
+0xaee204c8, 0x8f420218, 0x30420200, 0x10400003, 
+0x24020001, 0x8001091, 0xa2e27248, 0xa2e07248, 
+0x24020001, 0xaf8200a0, 0xaf8200b0, 0x8f830054, 
+0x8f820054, 0x8001099, 0x24630064, 0x8f820054, 
+0x621023, 0x2c420065, 0x1440fffc, 0x0, 
+0xaf800044, 0x8f420208, 0x8f43020c, 0xaee20010, 
+0xaee30014, 0x8ee40010, 0x8ee50014, 0x26e20030, 
+0xaee20028, 0x24020490, 0xaee20018, 0xaf840090, 
+0xaf850094, 0x8ee20028, 0xaf8200b4, 0x96e2001a, 
+0xaf82009c, 0x8f8200b0, 0x8ee304cc, 0x431025, 
+0xaf8200b0, 0x8f8200b0, 0x30420004, 0x1440fffd, 
+0x0, 0x8ee20450, 0x8ee30454, 0xaee304fc, 
+0x8ee204fc, 0x2442e000, 0x2c422001, 0x1440000d, 
+0x26e40030, 0x8ee20450, 0x8ee30454, 0x3c040001, 
+0x2484499c, 0x3c050001, 0xafa00010, 0xafa00014, 
+0x8ee704fc, 0x34a5f000, 0xc002407, 0x603021, 
+0x26e40030, 0xc00248c, 0x24050400, 0x27440080, 
+0xc00248c, 0x24050080, 0x26e4777c, 0xc00248c, 
+0x24050400, 0x8f42025c, 0x26e40094, 0xaee20060, 
+0x8f420260, 0x27450200, 0x24060008, 0xaee20068, 
+0x24020006, 0xc00249e, 0xaee20064, 0x3c023b9a, 
+0x3442ca00, 0x2021, 0x24030002, 0xaee30074, 
+0xaee30070, 0xaee2006c, 0x240203e8, 0xaee20104, 
+0x24020001, 0xaee30100, 0xaee2010c, 0x3c030001, 
+0x641821, 0x906353e0, 0x2e41021, 0x24840001, 
+0xa043009c, 0x2c82000f, 0x1440fff8, 0x0, 
+0x8f820040, 0x2e41821, 0x24840001, 0x21702, 
+0x24420030, 0xa062009c, 0x2e41021, 0xa040009c, 
+0x96e2046a, 0x30420003, 0x14400009, 0x0, 
+0x96e2047a, 0x30420003, 0x50400131, 0x3c030800, 
+0x96e2046a, 0x30420003, 0x1040002a, 0x3c020700, 
+0x96e2047a, 0x30420003, 0x10400026, 0x3c020700, 
+0x96e3047a, 0x96e2046a, 0x14620022, 0x3c020700, 
+0x8ee204c0, 0x24030001, 0xa2e34e20, 0x34420e00, 
+0xaee204c0, 0x8f420218, 0x30420100, 0x10400005, 
+0x0, 0x3c020001, 0x2442e178, 0x800111d, 
+0x21100, 0x3c020001, 0x2442d36c, 0x21100, 
+0x21182, 0x3c030800, 0x431025, 0x3c010001, 
+0xac221238, 0x3c020001, 0x2442f690, 0x21100, 
+0x21182, 0x3c030800, 0x431025, 0x3c010001, 
+0xac221278, 0x8ee20000, 0x34424000, 0x8001238, 
+0xaee20000, 0x34423000, 0xafa20018, 0x8ee20608, 
+0x8f430228, 0x24420001, 0x304900ff, 0x512300e2, 
+0xafa00010, 0x8ee20608, 0x210c0, 0x571021, 
+0x8fa30018, 0x8fa4001c, 0xac43060c, 0xac440610, 
+0x8f870120, 0x27623800, 0x24e80020, 0x102102b, 
+0x50400001, 0x27683000, 0x8f820128, 0x11020004, 
+0x0, 0x8f820124, 0x15020007, 0x1021, 
+0x8ee201a4, 0x3021, 0x24420001, 0xaee201a4, 
+0x80011a0, 0x8ee201a4, 0x8ee40608, 0x420c0, 
+0x801821, 0x8ee40430, 0x8ee50434, 0xa32821, 
+0xa3302b, 0x822021, 0x862021, 0xace40000, 
+0xace50004, 0x8ee30608, 0x24020008, 0xa4e2000e, 
+0x2402000d, 0xace20018, 0xace9001c, 0x318c0, 
+0x2463060c, 0x2e31021, 0xace20008, 0x8ee204c4, 
+0xace20010, 0xaf880120, 0x92e24e20, 0x14400037, 
+0x24060001, 0x8ee24e30, 0x210c0, 0x24425038, 
+0x2e22021, 0x8c830000, 0x24020007, 0x1462001f, 
+0x0, 0x8ee34e30, 0x8ee24e34, 0x1062001b, 
+0x24030040, 0x8c820004, 0x24420001, 0xac820004, 
+0x8ee24e34, 0x8ee54e30, 0x24420001, 0x10430007, 
+0x0, 0x8ee24e34, 0x24420001, 0x10a20005, 
+0x0, 0x800118a, 0x0, 0x14a00005, 
+0x0, 0x8f820128, 0x24420020, 0xaf820128, 
+0x8f820128, 0x8c820004, 0x2c420011, 0x50400013, 
+0xac800000, 0x80011a0, 0x0, 0x8ee24e30, 
+0x24030040, 0x24420001, 0x50430003, 0x1021, 
+0x8ee24e30, 0x24420001, 0xaee24e30, 0x8ee24e30, 
+0x210c0, 0x24425038, 0x2e22021, 0x24020007, 
+0xac820000, 0x24020001, 0xac820004, 0x54c0000c, 
+0xaee90608, 0x3c040001, 0x248449a8, 0xafa00010, 
+0xafa00014, 0x8ee60608, 0x8f470228, 0x3c050009, 
+0xc002407, 0x34a5f000, 0x8001223, 0x0, 
+0x8f830120, 0x27623800, 0x24660020, 0xc2102b, 
+0x50400001, 0x27663000, 0x8f820128, 0x10c20004, 
+0x0, 0x8f820124, 0x14c20007, 0x0, 
+0x8ee201a4, 0x3021, 0x24420001, 0xaee201a4, 
+0x8001207, 0x8ee201a4, 0x8ee20608, 0xac62001c, 
+0x8ee404a0, 0x8ee504a4, 0x2462001c, 0xac620008, 
+0x24020008, 0xa462000e, 0x24020011, 0xac620018, 
+0xac640000, 0xac650004, 0x8ee204c4, 0xac620010, 
+0xaf860120, 0x92e24e20, 0x14400037, 0x24060001, 
+0x8ee24e30, 0x210c0, 0x24425038, 0x2e22021, 
+0x8c830000, 0x24020012, 0x1462001f, 0x0, 
+0x8ee34e30, 0x8ee24e34, 0x1062001b, 0x24030040, 
+0x8c820004, 0x24420001, 0xac820004, 0x8ee24e34, 
+0x8ee54e30, 0x24420001, 0x10430007, 0x0, 
+0x8ee24e34, 0x24420001, 0x10a20005, 0x0, 
+0x80011f1, 0x0, 0x14a00005, 0x0, 
+0x8f820128, 0x24420020, 0xaf820128, 0x8f820128, 
+0x8c820004, 0x2c420011, 0x50400013, 0xac800000, 
+0x8001207, 0x0, 0x8ee24e30, 0x24030040, 
+0x24420001, 0x50430003, 0x1021, 0x8ee24e30, 
+0x24420001, 0xaee24e30, 0x8ee24e30, 0x210c0, 
+0x24425038, 0x2e22021, 0x24020012, 0xac820000, 
+0x24020001, 0xac820004, 0x14c0001b, 0x0, 
+0x3c040001, 0x248449b0, 0xafa00010, 0xafa00014, 
+0x8ee60608, 0x8f470228, 0x3c050009, 0xc002407, 
+0x34a5f001, 0x8ee201b0, 0x24420001, 0xaee201b0, 
+0x8001223, 0x8ee201b0, 0x3c040001, 0x248449bc, 
+0xafa00014, 0x8ee60608, 0x8f470228, 0x3c050009, 
+0xc002407, 0x34a5f005, 0x8ee201ac, 0x24420001, 
+0xaee201ac, 0x8ee201ac, 0x8ee20160, 0x3c040001, 
+0x248449c8, 0x3405f001, 0x24420001, 0xaee20160, 
+0x8ee20160, 0x3021, 0x3821, 0xafa00010, 
+0xc002407, 0xafa00014, 0x8001238, 0x0, 
+0x3c020001, 0x2442f5b8, 0x21100, 0x21182, 
+0x431025, 0x3c010001, 0xac221278, 0x96e2045a, 
+0x30420003, 0x10400025, 0x3c050fff, 0x8ee204c8, 
+0x34a5ffff, 0x34420a00, 0xaee204c8, 0x8ee304c8, 
+0x3c040001, 0x248449d4, 0x24020001, 0xa2e204ec, 
+0xa2e204ed, 0x3c020002, 0x621825, 0x3c020001, 
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+0x8004ff7, 0xac2275d8, 0x111140, 0x3c010001, 
+0x220821, 0xac2075d8, 0x94e30000, 0x32024000, 
+0x10400003, 0xa7a30018, 0x34624000, 0xa7a20018, 
+0x24040001, 0x94e20002, 0x24050004, 0x24e60002, 
+0x34420001, 0xc0048ee, 0xa4e20002, 0x24040001, 
+0x2821, 0xc0048ee, 0x27a60018, 0x3c020001, 
+0x8c425488, 0x24110001, 0x3c010001, 0xac315494, 
+0x14530004, 0x32028000, 0xc00429f, 0x0, 
+0x32028000, 0x10400099, 0x0, 0xc00429f, 
+0x0, 0x24020002, 0x3c010001, 0xac31548c, 
+0x3c010001, 0x80050ac, 0xac225488, 0x24040001, 
+0x24050004, 0x27b0001a, 0xc0048ee, 0x2003021, 
+0x24040001, 0x2821, 0xc0048ee, 0x2003021, 
+0x3c020001, 0x521021, 0x8c4275c4, 0x3c040001, 
+0x8c845488, 0x3c03bfff, 0x3463ffff, 0x3c010001, 
+0xac335494, 0x431024, 0x3c010001, 0x320821, 
+0x10930078, 0xac2275c4, 0x80050ac, 0x0, 
+0x3c02ffec, 0x3442ffff, 0x2028024, 0x3c020008, 
+0x2028025, 0x111140, 0x3c010001, 0x220821, 
+0xac3075c8, 0x3c022000, 0x2021024, 0x10400009, 
+0x0, 0x3c020001, 0x8c425514, 0x14400005, 
+0x24020001, 0x3c010001, 0xac225538, 0x800504d, 
+0x3c024000, 0x3c010001, 0xac205538, 0x3c024000, 
+0x2021024, 0x1440001c, 0x0, 0x3c020001, 
+0x8c425538, 0x10400007, 0x24022020, 0x3c010001, 
+0xac22553c, 0x24020001, 0x3c010001, 0x370821, 
+0xac2283ac, 0x3c04bfff, 0x111940, 0x3c020001, 
+0x431021, 0x8c4275c0, 0x3c050001, 0x8ca55488, 
+0x3484ffff, 0x441024, 0x3c010001, 0x230821, 
+0xac2275c0, 0x24020001, 0x10a20044, 0x0, 
+0x80050aa, 0x0, 0x3c020001, 0x8c425538, 
+0x1040001c, 0x24022000, 0x3c010001, 0xac22553c, 
+0x3c0300a0, 0x2031024, 0x14430005, 0x111140, 
+0x3402a000, 0x3c010001, 0x80050a5, 0xac22553c, 
+0x3c030001, 0x621821, 0x8c6375c8, 0x3c020020, 
+0x621024, 0x10400004, 0x24022001, 0x3c010001, 
+0x80050a5, 0xac22553c, 0x3c020080, 0x621024, 
+0x1040001f, 0x3402a001, 0x3c010001, 0x80050a5, 
+0xac22553c, 0x3c020020, 0x2021024, 0x10400007, 
+0x111940, 0x24020100, 0x3c010001, 0x230821, 
+0xac2275d4, 0x8005099, 0x3c020080, 0x111140, 
+0x3c010001, 0x220821, 0xac2075d4, 0x3c020080, 
+0x2021024, 0x10400006, 0x111940, 0x3c020001, 
+0x3c010001, 0x230821, 0x80050a5, 0xac2275dc, 
+0x111140, 0x3c010001, 0x220821, 0xac2075dc, 
+0x3c030001, 0x8c635488, 0x24020001, 0x10620003, 
+0x0, 0xc00429f, 0x0, 0x8fbf0030, 
+0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020, 
+0x3e00008, 0x27bd0038, 0x27bdffd0, 0xafb40028, 
+0x80a021, 0xafb20020, 0x9021, 0xafb30024, 
+0x9821, 0xafb1001c, 0x8821, 0x24020002, 
+0xafbf002c, 0xafb00018, 0xa7a00012, 0x10a20068, 
+0xa7a00010, 0x2ca20003, 0x10400005, 0x24020001, 
+0x10a2000a, 0x148140, 0x8005176, 0x2201021, 
+0x24020004, 0x10a2005e, 0x24020008, 0x10a2005d, 
+0x142940, 0x8005176, 0x2201021, 0x3c030001, 
+0x701821, 0x8c6375cc, 0x3c024000, 0x621024, 
+0x14400009, 0x24040001, 0x3c027fff, 0x3442ffff, 
+0x628824, 0x3c010001, 0x300821, 0xac3175c4, 
+0x8005176, 0x2201021, 0x24050001, 0xc0048ac, 
+0x27a60010, 0x24040001, 0x24050001, 0xc0048ac, 
+0x27a60010, 0x97a20010, 0x30420004, 0x10400034, 
+0x3c114000, 0x3c030001, 0x8c635550, 0x24020003, 
+0x10620008, 0x2c620004, 0x14400029, 0x3c028000, 
+0x24020004, 0x10620014, 0x24040001, 0x8005119, 
+0x3c028000, 0x24040001, 0x24050011, 0x27b00012, 
+0xc0048ac, 0x2003021, 0x24040001, 0x24050011, 
+0xc0048ac, 0x2003021, 0x97a30012, 0x30624000, 
+0x10400002, 0x3c130010, 0x3c130008, 0x3c120001, 
+0x8005116, 0x30628000, 0x24050014, 0x27b00012, 
+0xc0048ac, 0x2003021, 0x24040001, 0x24050014, 
+0xc0048ac, 0x2003021, 0x97a30012, 0x30621000, 
+0x10400002, 0x3c130010, 0x3c130008, 0x3c120001, 
+0x30620800, 0x54400001, 0x3c120002, 0x3c028000, 
+0x2221025, 0x2531825, 0x8005123, 0x438825, 
+0x3c110001, 0x2308821, 0x8e3175cc, 0x3c027fff, 
+0x3442ffff, 0x2228824, 0x141140, 0x3c010001, 
+0x220821, 0xac3175c4, 0x8005176, 0x2201021, 
+0x142940, 0x3c030001, 0x651821, 0x8c6375c8, 
+0x3c024000, 0x621024, 0x14400008, 0x3c027fff, 
+0x3442ffff, 0x628824, 0x3c010001, 0x250821, 
+0xac3175c0, 0x8005176, 0x2201021, 0x3c020001, 
+0x8c425498, 0x10400033, 0x3c11c00c, 0x3c020001, 
+0x8c425514, 0x3c04c00c, 0x34842000, 0x3c030001, 
+0x8c635538, 0x2102b, 0x21023, 0x441024, 
+0x10600003, 0x518825, 0x3c022000, 0x2228825, 
+0x3c020001, 0x451021, 0x8c4275d4, 0x10400003, 
+0x3c020020, 0x8005153, 0x2228825, 0x3c02ffdf, 
+0x3442ffff, 0x2228824, 0x141140, 0x3c010001, 
+0x220821, 0x8c2275dc, 0x10400003, 0x3c020080, 
+0x800515e, 0x2228825, 0x3c02ff7f, 0x3442ffff, 
+0x2228824, 0x3c020001, 0x8c425500, 0x10400002, 
+0x3c020800, 0x2228825, 0x3c020001, 0x8c425504, 
+0x10400002, 0x3c020400, 0x2228825, 0x3c020001, 
+0x8c425508, 0x10400006, 0x3c020100, 0x8005171, 
+0x2228825, 0x3c027fff, 0x3442ffff, 0x628824, 
+0x141140, 0x3c010001, 0x220821, 0xac3175c0, 
+0x2201021, 0x8fbf002c, 0x8fb40028, 0x8fb30024, 
+0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x3e00008, 
+0x27bd0030, 0x27bdffd8, 0xafb40020, 0x80a021, 
+0xafbf0024, 0xafb3001c, 0xafb20018, 0xafb10014, 
+0xafb00010, 0x8f900200, 0x3c030001, 0x8c635488, 
+0x8f930220, 0x24020002, 0x106200b4, 0x2c620003, 
+0x10400005, 0x24020001, 0x1062000a, 0x141940, 
+0x8005240, 0x0, 0x24020004, 0x1062005a, 
+0x24020008, 0x10620059, 0x149140, 0x8005240, 
+0x0, 0x3c040001, 0x832021, 0x8c8475cc, 
+0x3c110001, 0x2238821, 0x8e3175c4, 0x3c024000, 
+0x821024, 0x1040003e, 0x3c020008, 0x2221024, 
+0x10400020, 0x36100002, 0x3c020001, 0x431021, 
+0x8c4275d0, 0x10400005, 0x36100020, 0x36100100, 
+0x3c020020, 0x80051b5, 0x2228825, 0x2402feff, 
+0x2028024, 0x3c02ffdf, 0x3442ffff, 0x2228824, 
+0x141140, 0x3c010001, 0x220821, 0x8c2275d8, 
+0x10400005, 0x3c020001, 0x2629825, 0x3c020080, 
+0x80051d4, 0x2228825, 0x3c02fffe, 0x3442ffff, 
+0x2629824, 0x3c02ff7f, 0x3442ffff, 0x80051d4, 
+0x2228824, 0x2402fedf, 0x2028024, 0x3c02fffe, 
+0x3442ffff, 0x2629824, 0x3c02ff5f, 0x3442ffff, 
+0x2228824, 0x3c010001, 0x230821, 0xac2075d0, 
+0x3c010001, 0x230821, 0xac2075d8, 0xc0047cc, 
+0x0, 0xaf900200, 0xaf930220, 0x8f820220, 
+0x2403fffb, 0x431024, 0xaf820220, 0x8f820220, 
+0x34420002, 0xaf820220, 0x80051eb, 0x141140, 
+0x8f820200, 0x2403fffd, 0x431024, 0xc0047cc, 
+0xaf820200, 0x3c02bfff, 0x3442ffff, 0xc00429f, 
+0x2228824, 0x141140, 0x3c010001, 0x220821, 
+0x8005240, 0xac3175c4, 0x149140, 0x3c040001, 
+0x922021, 0x8c8475c8, 0x3c110001, 0x2328821, 
+0x8e3175c0, 0x3c024000, 0x821024, 0x14400011, 
+0x0, 0x3c020001, 0x8c425538, 0x14400006, 
+0x3c02bfff, 0x8f820200, 0x34420002, 0xc0047cc, 
+0xaf820200, 0x3c02bfff, 0x3442ffff, 0xc00429f, 
+0x2228824, 0x3c010001, 0x320821, 0x8005240, 
+0xac3175c0, 0x3c020001, 0x8c425538, 0x10400005, 
+0x3c020020, 0x3c020001, 0x8c425514, 0x1040002b, 
+0x3c020020, 0x821024, 0x10400007, 0x36100020, 
+0x24020100, 0x3c010001, 0x320821, 0xac2275d4, 
+0x8005220, 0x36100100, 0x3c010001, 0x320821, 
+0xac2075d4, 0x2402feff, 0x2028024, 0x3c020080, 
+0x821024, 0x10400007, 0x141940, 0x3c020001, 
+0x3c010001, 0x230821, 0xac2275dc, 0x8005231, 
+0x2629825, 0x141140, 0x3c010001, 0x220821, 
+0xac2075dc, 0x3c02fffe, 0x3442ffff, 0x2629824, 
+0xc0047cc, 0x0, 0xaf900200, 0xaf930220, 
+0x8f820220, 0x2403fffb, 0x431024, 0xaf820220, 
+0x8f820220, 0x34420002, 0xaf820220, 0x141140, 
+0x3c010001, 0x220821, 0xac3175c0, 0x8fbf0024, 
+0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 
+0x8fb00010, 0x3e00008, 0x27bd0028, 0x0 };
+static u_int32_t tigonFwRodata[] = {
+0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f66776d, 0x61696e2e, 0x632c7620, 0x312e312e, 
+0x322e3131, 0x20313939, 0x382f3034, 0x2f323720, 
+0x32323a31, 0x333a3432, 0x20736875, 0x616e6720, 
+0x45787020, 0x24000000, 0x7468655f, 0x4441574e, 
+0x0, 0x53544143, 0x4b5f3120, 0x0, 
+0x42616453, 0x6e64526e, 0x67000000, 0x3f456e71, 
+0x45767400, 0x3f6e6f51, 0x64457650, 0x0, 
+0x6576526e, 0x6746756c, 0x6c000000, 0x496c6c43, 
+0x6f6e6652, 0x78000000, 0x53656e64, 0x436b5375, 
+0x6d000000, 0x52656376, 0x566c616e, 0x0, 
+0x0, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f74696d, 0x65722e63, 0x2c762031, 0x2e312e32, 
+0x2e382031, 0x3939382f, 0x30372f33, 0x31203137, 
+0x3a35383a, 0x34352073, 0x6875616e, 0x67204578, 
+0x70202400, 0x542d446d, 0x61526431, 0x0, 
+0x542d446d, 0x61424200, 0x542d446d, 0x61320000, 
+0x3f6e6f51, 0x64547845, 0x0, 0x3f6e6f51, 
+0x64527845, 0x0, 0x656e714d, 0x45765046, 
+0x61696c00, 0x656e714d, 0x45764661, 0x696c0000, 
+0x6661696c, 0x456e454d, 0x0, 0x3f456e71, 
+0x45767400, 0x3f6e6f51, 0x64457650, 0x0, 
+0x6576526e, 0x6746756c, 0x6c000000, 0x0, 
+0x0, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f636f6d, 0x6d616e64, 0x2e632c76, 0x20312e31, 
+0x2e322e31, 0x30203139, 0x39382f31, 0x312f3138, 
+0x2031373a, 0x31313a31, 0x38207368, 0x75616e67, 
+0x20457870, 0x20240000, 0x3f4d626f, 0x78457674, 
+0x0, 0x4e4f636f, 0x6d616e64, 0x0, 
+0x68737465, 0x5f455252, 0x0, 0x412d4572, 
+0x72427563, 0x0, 0x4552524f, 0x522d4164, 
+0x64000000, 0x656e714d, 0x45765046, 0x61696c00, 
+0x656e714d, 0x45764661, 0x696c0000, 0x6661696c, 
+0x456e454d, 0x0, 0x442d4572, 0x724c6173, 
+0x74000000, 0x442d4572, 0x72320000, 0x6d437374, 
+0x4d644552, 0x52000000, 0x70726f6d, 0x4d644552, 
+0x52000000, 0x46696c74, 0x4d644552, 0x52000000, 
+0x636d645f, 0x45525200, 0x3f456e71, 0x45767400, 
+0x3f6e6f51, 0x64457650, 0x0, 0x6576526e, 
+0x6746756c, 0x6c000000, 0x0, 0x6ea0, 
+0x7fbc, 0x6e38, 0x8734, 0x82b0, 
+0x8780, 0x8780, 0x6f54, 0x7694, 
+0x7f0c, 0x80a8, 0x8074, 0x8780, 
+0x7e70, 0x80cc, 0x6e64, 0x81cc, 
+0x0, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f646d61, 0x2e632c76, 0x20312e31, 0x2e322e33, 
+0x20313939, 0x382f3034, 0x2f323720, 0x32323a31, 
+0x333a3431, 0x20736875, 0x616e6720, 0x45787020, 
+0x24000000, 0x646d6172, 0x6441544e, 0x0, 
+0x646d6177, 0x7241544e, 0x0, 0x0, 
+0x0, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f747261, 0x63652e63, 0x2c762031, 0x2e312e32, 
+0x2e322031, 0x3939382f, 0x30342f32, 0x37203232, 
+0x3a31333a, 0x35302073, 0x6875616e, 0x67204578, 
+0x70202400, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f646174, 0x612e632c, 0x7620312e, 0x312e322e, 
+0x32203139, 0x39382f30, 0x342f3237, 0x2032323a, 
+0x31333a34, 0x30207368, 0x75616e67, 0x20457870, 
+0x20240000, 0x46575f56, 0x45525349, 0x4f4e3a20, 
+0x23312054, 0x75652041, 0x70722032, 0x30203137, 
+0x3a32313a, 0x30382050, 0x44542031, 0x39393900, 
+0x46575f43, 0x4f4d5049, 0x4c455f54, 0x494d453a, 
+0x2031373a, 0x32313a30, 0x38000000, 0x46575f43, 
+0x4f4d5049, 0x4c455f42, 0x593a2064, 0x65767263, 
+0x73000000, 0x46575f43, 0x4f4d5049, 0x4c455f48, 
+0x4f53543a, 0x20636f6d, 0x70757465, 0x0, 
+0x46575f43, 0x4f4d5049, 0x4c455f44, 0x4f4d4149, 
+0x4e3a2065, 0x6e672e61, 0x6374656f, 0x6e2e636f, 
+0x6d000000, 0x46575f43, 0x4f4d5049, 0x4c45523a, 
+0x20676363, 0x20766572, 0x73696f6e, 0x20322e37, 
+0x2e320000, 0x0, 0x0, 0x0, 
+0x0, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f6d656d, 0x2e632c76, 0x20312e31, 0x2e322e32, 
+0x20313939, 0x382f3034, 0x2f323720, 0x32323a31, 
+0x333a3434, 0x20736875, 0x616e6720, 0x45787020, 
+0x24000000, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f73656e, 0x642e632c, 0x7620312e, 0x312e322e, 
+0x31312031, 0x3939382f, 0x31322f32, 0x32203137, 
+0x3a31373a, 0x35352073, 0x6875616e, 0x67204578, 
+0x70202400, 0x736e6464, 0x654e6f51, 0x20000000, 
+0x6e6f454e, 0x515f5458, 0x0, 0x736e6464, 
+0x744e6f51, 0x20000000, 0x3f6e6f51, 0x64547845, 
+0x0, 0x756e6b72, 0x64747970, 0x65000000, 
+0x0, 0xacdc, 0xacdc, 0xadac, 
+0xaac0, 0xaac0, 0xadac, 0xadac, 
+0xadac, 0xadac, 0xadac, 0xadac, 
+0xadac, 0xadac, 0xadac, 0xadac, 
+0xadac, 0xadac, 0xadac, 0xad8c, 
+0x0, 0xbcb8, 0xbcb8, 0xbd80, 
+0xae5c, 0xb068, 0xbd80, 0xbd80, 
+0xbd80, 0xbd80, 0xbd80, 0xbd80, 
+0xbd80, 0xbd80, 0xbd80, 0xbd80, 
+0xbd80, 0xbd80, 0xbd80, 0xbd64, 
+0xb050, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f726563, 0x762e632c, 0x7620312e, 0x312e322e, 
+0x31392031, 0x3939382f, 0x30372f32, 0x34203231, 
+0x3a33303a, 0x30352073, 0x6875616e, 0x67204578, 
+0x70202400, 0x706b5278, 0x45525200, 0x66726d32, 
+0x4c617267, 0x65000000, 0x72784e6f, 0x52784264, 
+0x0, 0x72785144, 0x6d614446, 0x0, 
+0x72785144, 0x6d614246, 0x0, 0x3f6e6f51, 
+0x64527845, 0x0, 0x706b5278, 0x45525273, 
+0x0, 0x66726d32, 0x4c726753, 0x0, 
+0x72784e6f, 0x42645300, 0x3f724264, 0x446d6146, 
+0x0, 0x3f724a42, 0x64446d46, 0x0, 
+0x0, 0xf688, 0xf688, 0xf688, 
+0xf688, 0xf688, 0xf688, 0xf688, 
+0xf688, 0xf688, 0xf688, 0xf688, 
+0xf688, 0xf688, 0xf688, 0xf688, 
+0xf680, 0xf680, 0xf680, 0x572d444d, 
+0x41456e46, 0x0, 0x0, 0xfdd0, 
+0x1016c, 0xfdec, 0x1016c, 0x1016c, 
+0x1016c, 0x1016c, 0x1016c, 0x1016c, 
+0xf714, 0x1016c, 0x1016c, 0x1016c, 
+0x1016c, 0x1016c, 0x10164, 0x10164, 
+0x10164, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f6d6163, 0x2e632c76, 0x20312e31, 0x2e322e31, 
+0x32203139, 0x39382f30, 0x342f3237, 0x2032323a, 
+0x31333a34, 0x32207368, 0x75616e67, 0x20457870, 
+0x20240000, 0x6d616374, 0x7841544e, 0x0, 
+0x4e745379, 0x6e264c6b, 0x0, 0x72656d61, 
+0x73737274, 0x0, 0x6c696e6b, 0x444f574e, 
+0x0, 0x656e714d, 0x45765046, 0x61696c00, 
+0x656e714d, 0x45764661, 0x696c0000, 0x6661696c, 
+0x456e454d, 0x0, 0x6c696e6b, 0x55500000, 
+0x0, 0x24486561, 0x6465723a, 0x202f7072, 
+0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, 
+0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, 
+0x2f636b73, 0x756d2e63, 0x2c762031, 0x2e312e32, 
+0x2e322031, 0x3939382f, 0x30342f32, 0x37203232, 
+0x3a31333a, 0x33392073, 0x6875616e, 0x67204578, 
+0x70202400, 0x50726f62, 0x65506879, 0x0, 
+0x6c6e6b41, 0x53535254, 0x0, 0x11994, 
+0x119cc, 0x119e4, 0x11a18, 0x11a44, 
+0x11a58, 0x11a94, 0x11e04, 0x11b6c, 
+0x11bac, 0x11bd8, 0x11c18, 0x11c48, 
+0x11c84, 0x11cb8, 0x11e04, 0x12048, 
+0x12060, 0x12088, 0x120a8, 0x120d0, 
+0x12200, 0x12228, 0x1227c, 0x122a4, 
+0x0, 0x1250c, 0x125dc, 0x126b4, 
+0x12784, 0x127e0, 0x128bc, 0x128e4, 
+0x129c0, 0x129e8, 0x12b90, 0x12bb8, 
+0x12d60, 0x12f58, 0x131ec, 0x13100, 
+0x131ec, 0x13218, 0x12d88, 0x12f30, 
+0x0, 0x13604, 0x13648, 0x136e0, 
+0x1372c, 0x1379c, 0x13834, 0x13868, 
+0x138f0, 0x13988, 0x13a58, 0x13a98, 
+0x13b1c, 0x13b40, 0x13c74, 0x646f4261, 
+0x73655067, 0x0, 0x0, 0x0, 
+0x0, 0x73746d61, 0x634c4e4b, 0x0, 
+0x0, 0x0 };
+static u_int32_t tigonFwData[] = {
+0x416c7465, 
+0x6f6e2041, 0x63654e49, 0x43205600, 0x416c7465, 
+0x6f6e2041, 0x63654e49, 0x43205600, 0x42424242, 
+0x0, 0x0, 0x0, 0x135418, 
+0x13e7fc, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x60cf00, 
+0x60, 0xcf000000, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x3, 0x0, 
+0x1, 0x0, 0x0, 0x1, 
+0x0, 0x0, 0x0, 0x1, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x1000000, 0x21000000, 0x12000140, 
+0x0, 0x0, 0x20000000, 0x120000a0, 
+0x0, 0x12000060, 0x12000180, 0x120001e0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x2, 
+0x0, 0x0, 0x30001, 0x1, 
+0x30201, 0x0, 0x0, 0x0 };
diff --git a/sys/dev/pci/ti_fw2.h b/sys/dev/pci/ti_fw2.h
new file mode 100644
index 00000000000..be456fa7bae
--- /dev/null
+++ b/sys/dev/pci/ti_fw2.h
@@ -0,0 +1,4367 @@
+/*	$OpenBSD: ti_fw2.h,v 1.1 1999/07/25 16:51:56 jason Exp $	*/
+
+/*
+ * Generated by genfw.c
+ * Built on Mon May  3 13:16:39 1999 by wpaul@wormhole.ee.columbia.edu
+ * OS: FreeBSD 3.0-19981103-SNAP
+ *
+ *	$FreeBSD: ti_fw2.h,v 1.2 1999/05/03 17:44:53 wpaul Exp $
+ */
+static int tigon2FwReleaseMajor = 0xc;
+static int tigon2FwReleaseMinor = 0x3;
+static int tigon2FwReleaseFix = 0xa;
+static u_int32_t tigon2FwStartAddr = 0x00004000;
+static u_int32_t tigon2FwTextAddr = 0x00004000;
+static int tigon2FwTextLen = 0xfd10;
+static u_int32_t tigon2FwRodataAddr = 0x00013d10;
+static int tigon2FwRodataLen = 0x10a0;
+static u_int32_t tigon2FwDataAddr = 0x00014fa0;
+static int tigon2FwDataLen = 0x170;
+static u_int32_t tigon2FwSbssAddr = 0x00015110;
+static int tigon2FwSbssLen = 0xbc;
+static u_int32_t tigon2FwBssAddr = 0x000151d0;
+static int tigon2FwBssLen = 0x20c0;
+static u_int32_t tigon2FwText[] = {
+0x0, 
+0x10000003, 0x0, 0xd, 0xd, 
+0x3c1d0001, 0x8fbd4ff0, 0x3a0f021, 0x3c100000, 
+0x26104000, 0xc001084, 0x0, 0xd, 
+0x3c1d0001, 0x8fbd4ff4, 0x3a0f021, 0x3c100000, 
+0x26104000, 0xc001971, 0x0, 0xd, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x2000008, 
+0x0, 0x8001913, 0x3c0a0001, 0x8001913, 
+0x3c0a0002, 0x8001913, 0x0, 0x8002ca6, 
+0x0, 0x8002c34, 0x0, 0x8001913, 
+0x3c0a0004, 0x8003d50, 0x0, 0x8001add, 
+0x0, 0x80039fc, 0x0, 0x800398e, 
+0x0, 0x8001913, 0x3c0a0006, 0x8003a7f, 
+0x3c0a0007, 0x8001913, 0x3c0a0008, 0x8001913, 
+0x3c0a0009, 0x8003aec, 0x0, 0x8002ea0, 
+0x0, 0x8001913, 0x3c0a000b, 0x8001913, 
+0x3c0a000c, 0x8001913, 0x3c0a000d, 0x80027e4, 
+0x0, 0x800277a, 0x0, 0x8001913, 
+0x3c0a000e, 0x8002030, 0x0, 0x80019f8, 
+0x0, 0x8001a92, 0x0, 0x8003d90, 
+0x0, 0x8003fe4, 0x0, 0x8001913, 
+0x0, 0x80019a0, 0x0, 0x8001913, 
+0x0, 0x8001913, 0x3c0a0013, 0x8001913, 
+0x3c0a0014, 0x0, 0x0, 0x27bdffe0, 
+0x3c1cc000, 0xafbf001c, 0xafb00018, 0x8f820140, 
+0x24030003, 0xaf8300ec, 0x34420004, 0xc002b78, 
+0xaf820140, 0x3c0100c0, 0xc0018f1, 0xac203ffc, 
+0x403021, 0x3c020008, 0x3c010001, 0xac265128, 
+0x10c2001f, 0x3c100010, 0x10d0001d, 0x24050100, 
+0x3c040001, 0x24843dc4, 0x3821, 0xafa00010, 
+0xc002bdf, 0xafa00014, 0x3c040001, 0x24843dd0, 
+0x24020235, 0xafa20010, 0xafa00014, 0x8f860144, 
+0x3c070001, 0x24e73dd8, 0xc002bdf, 0x3405dead, 
+0x8f82011c, 0x34420002, 0xaf82011c, 0x8f820220, 
+0x34420004, 0xaf820220, 0x8f820140, 0x3c030001, 
+0x3c010001, 0xac305128, 0x431025, 0xaf820140, 
+0x3c020003, 0x34422000, 0x3c010001, 0xac225138, 
+0x24020008, 0x3c010001, 0xac225140, 0x2402001f, 
+0x3c010001, 0xac225150, 0x24020016, 0x3c010001, 
+0xac225124, 0x3c05fffe, 0x34a56f08, 0x3c020001, 
+0x8c425128, 0x3c030001, 0x24637290, 0x3c040001, 
+0x8c844fa4, 0x431023, 0x14800002, 0x458021, 
+0x2610fa48, 0x2402f000, 0x2028024, 0xc00187f, 
+0x2002021, 0x2022823, 0x3c040020, 0x821823, 
+0x651823, 0x247bb000, 0x3c03fffe, 0x3463bf08, 
+0x363b821, 0x3c0600bf, 0x34c6f000, 0x3c070001, 
+0x8ce74fa0, 0x3c0300bf, 0x3463e000, 0x852023, 
+0x3c010001, 0xac245134, 0x822023, 0x3c010001, 
+0xac225110, 0x27620ffc, 0x3c010001, 0xac224ff0, 
+0x27621ffc, 0xdb3023, 0x7b1823, 0x3c010001, 
+0xac25511c, 0x3c010001, 0xac245114, 0x3c010001, 
+0xac224ff4, 0xaf860150, 0xaf830250, 0x10e00026, 
+0x33620fff, 0x10400014, 0x24020264, 0x3c040001, 
+0x24843dd0, 0xafa20010, 0xafa00014, 0x8f860144, 
+0x3c070001, 0x24e73dd8, 0xc002bdf, 0x3405dead, 
+0x8f82011c, 0x34420002, 0xaf82011c, 0x8f820220, 
+0x34420004, 0xaf820220, 0x8f820140, 0x3c030001, 
+0x431025, 0xaf820140, 0x3c1d0001, 0x8fbd4fac, 
+0x3a0f021, 0xc0018a9, 0x0, 0x3c020001, 
+0x8c424fb0, 0x3c030001, 0x8c634fb4, 0x2442fe00, 
+0x24630200, 0x3c010001, 0xac224fb0, 0x3c010001, 
+0x10000004, 0xac234fb4, 0x3c1d0001, 0x8fbd4ff0, 
+0x3a0f021, 0x3c020001, 0x8c424fa4, 0x1040000c, 
+0x26fafa48, 0x3c1a0001, 0x8f5a4fb4, 0x3c020001, 
+0x8c424fb0, 0x3401821, 0x2442fa48, 0x246305b8, 
+0x3c010001, 0xac224fb0, 0x3c010001, 0xac234fb4, 
+0x3c020001, 0x8c424fa8, 0x14400003, 0x0, 
+0x3c010001, 0xac204fb0, 0xc001139, 0x0, 
+0x8fbf001c, 0x8fb00018, 0x3e00008, 0x27bd0020, 
+0x3c020001, 0x8c424fb0, 0x3c030001, 0x8c634fb4, 
+0x27bdffa0, 0xafb00040, 0x3c100001, 0x8e104788, 
+0x3c040001, 0x24843de4, 0xafbf0058, 0xafbe0054, 
+0xafb50050, 0xafb3004c, 0xafb20048, 0xafb10044, 
+0xafa20034, 0xafa30030, 0xafa00010, 0xafa00014, 
+0x8f860040, 0x24050200, 0xc002bdf, 0x2003821, 
+0x8f830040, 0x3c02f000, 0x621824, 0x3c026000, 
+0x1062001f, 0xa3a00038, 0x3c040001, 0x24843dec, 
+0xafa00010, 0xafa00014, 0x8f860040, 0x24050300, 
+0xc002bdf, 0x2003821, 0x3c040001, 0x24843dd0, 
+0x240202ba, 0xafa20010, 0xafa00014, 0x8f860144, 
+0x3c070001, 0x24e73dd8, 0xc002bdf, 0x3405dead, 
+0x8f82011c, 0x34420002, 0xaf82011c, 0x8f820220, 
+0x34420004, 0xaf820220, 0x8f820140, 0x240e0001, 
+0x3c030001, 0xa3ae0038, 0x431025, 0xaf820140, 
+0x8f820240, 0x3c030001, 0x431025, 0xaf820240, 
+0xaf800048, 0x8f820048, 0x14400005, 0x0, 
+0xaf800048, 0x8f820048, 0x10400004, 0x0, 
+0xaf800048, 0x10000003, 0x2e02021, 0xaf80004c, 
+0x2e02021, 0x3c050001, 0xc002c10, 0x34a540f8, 
+0x3402021, 0xc002c10, 0x240505b8, 0x3c020001, 
+0x8c425134, 0x3c040001, 0x24843df8, 0x24050400, 
+0x3c0d0001, 0x8dad5114, 0x3c030001, 0x8c635110, 
+0x3c080001, 0x8d08511c, 0x3c090001, 0x8d295138, 
+0x3c0a0001, 0x8d4a5140, 0x3c0b0001, 0x8d6b5150, 
+0x3c0c0001, 0x8d8c5124, 0x24060001, 0xc03821, 
+0xaf400000, 0xaf420130, 0x2442ff80, 0xaf420134, 
+0xc01021, 0xaf4d012c, 0xaf430138, 0xaf48013c, 
+0xaf490140, 0xaf4a0144, 0xaf4b0148, 0xaf4c014c, 
+0xafa20010, 0xc002bdf, 0xafa00014, 0x8f42012c, 
+0xafa20010, 0x8f420130, 0xafa20014, 0x8f460138, 
+0x8f47013c, 0x3c040001, 0x24843e04, 0xc002bdf, 
+0x24050500, 0xafb70010, 0xafba0014, 0x8f460140, 
+0x8f470144, 0x3c040001, 0x24843e10, 0xc002bdf, 
+0x24050600, 0x3c020001, 0x8c425128, 0x3603821, 
+0x3c060001, 0x24c67290, 0x2448ffff, 0x1061824, 
+0xe81024, 0x43102b, 0x1040001a, 0x24050900, 
+0x3c040001, 0x24843e1c, 0xafa80010, 0xc002bdf, 
+0xafa00014, 0x3c040001, 0x24843dd0, 0x24020313, 
+0xafa20010, 0xafa00014, 0x8f860144, 0x3c070001, 
+0x24e73dd8, 0xc002bdf, 0x3405dead, 0x8f82011c, 
+0x34420002, 0xaf82011c, 0x8f820220, 0x34420004, 
+0xaf820220, 0x8f820140, 0x3c030001, 0x431025, 
+0xaf820140, 0x8f82000c, 0xafa20010, 0x8f82003c, 
+0xafa20014, 0x8f860000, 0x8f870004, 0x3c040001, 
+0x24843e28, 0xc002bdf, 0x24051000, 0x8021, 
+0x8e020220, 0x8e030224, 0x8e060218, 0x8e07021c, 
+0x3c040001, 0x24843e30, 0x24051100, 0xafa20010, 
+0xc002bdf, 0xafa30014, 0xaf800054, 0xaf80011c, 
+0x8e020218, 0x30440002, 0x10800009, 0x0, 
+0x8e020220, 0x3c030002, 0x34630004, 0x431025, 
+0xaf42000c, 0x8e02021c, 0x10000008, 0x34420004, 
+0x8c820220, 0x3c030002, 0x34630006, 0x431025, 
+0xaf42000c, 0x8c82021c, 0x34420006, 0xaf420014, 
+0x1821, 0x8c620218, 0x30440010, 0x1080000a, 
+0x0, 0x8c62021c, 0x34420004, 0xaf420010, 
+0x8c620220, 0x3c03000a, 0x34630004, 0x431025, 
+0x10000009, 0xaf420008, 0x8c820220, 0x3c03000a, 
+0x34630006, 0x431025, 0xaf420008, 0x8c82021c, 
+0x34420006, 0xaf420010, 0x24020001, 0xaf8200a0, 
+0xaf8200b0, 0x8f830054, 0x8f820054, 0x10000002, 
+0x24630064, 0x8f820054, 0x621023, 0x2c420065, 
+0x1440fffc, 0x1021, 0x8c440208, 0x8c45020c, 
+0x26e20028, 0xaee20020, 0x24020490, 0xaee20010, 
+0xaee40008, 0xaee5000c, 0x26e40008, 0x8c820000, 
+0x8c830004, 0xaf820090, 0xaf830094, 0x8c820018, 
+0xaf8200b4, 0x9482000a, 0xaf82009c, 0x8f8200b0, 
+0x8f430014, 0x431025, 0xaf8200b0, 0x8f8200b0, 
+0x30420004, 0x1440fffd, 0x24051200, 0x96e20472, 
+0x96e60452, 0x96e70462, 0xafa20010, 0x96e20482, 
+0x3c040001, 0x24843e38, 0xc002bdf, 0xafa20014, 
+0x96f00452, 0x32020001, 0x10400002, 0xb021, 
+0x24160001, 0x32020002, 0x54400001, 0x36d60002, 
+0x32020008, 0x54400001, 0x36d60004, 0x32020010, 
+0x54400001, 0x36d60008, 0x32020020, 0x54400001, 
+0x36d60010, 0x32020040, 0x54400001, 0x36d60020, 
+0x32020080, 0x54400001, 0x36d60040, 0x96e60482, 
+0x30c20200, 0x54400001, 0x36d64000, 0x96e30472, 
+0x30620200, 0x10400003, 0x30620100, 0x10000003, 
+0x36d62000, 0x54400001, 0x36d61000, 0x96f00462, 
+0x32c24000, 0x14400004, 0x3207009b, 0x30c2009b, 
+0x14e20007, 0x0, 0x32c22000, 0x14400022, 
+0x32020001, 0x3062009b, 0x10e2001f, 0x32020001, 
+0x3c040001, 0x24843e44, 0x24051300, 0x2003821, 
+0xafa30010, 0xc002bdf, 0xafa00014, 0x3c040001, 
+0x24843dd0, 0x240203bc, 0xafa20010, 0xafa00014, 
+0x8f860144, 0x3c070001, 0x24e73dd8, 0xc002bdf, 
+0x3405dead, 0x8f82011c, 0x34420002, 0xaf82011c, 
+0x8f820220, 0x34420004, 0xaf820220, 0x8f820140, 
+0x240f0001, 0x3c030001, 0xa3af0038, 0x431025, 
+0xaf820140, 0x32020001, 0x54400001, 0x36d60080, 
+0x32020002, 0x54400001, 0x36d60100, 0x32020008, 
+0x54400001, 0x36d60200, 0x32020010, 0x54400001, 
+0x36d60400, 0x32020080, 0x54400001, 0x36d60800, 
+0x8021, 0x8e020218, 0x30420200, 0x10400002, 
+0x3c020008, 0x2c2b025, 0x8e020218, 0x30420800, 
+0x10400002, 0x3c020080, 0x2c2b025, 0x8e020218, 
+0x30420400, 0x10400002, 0x3c020100, 0x2c2b025, 
+0x8e020218, 0x30420100, 0x10400002, 0x3c020200, 
+0x2c2b025, 0x8e020218, 0x30420080, 0x10400002, 
+0x3c020400, 0x2c2b025, 0x8e020218, 0x30422000, 
+0x10400002, 0x3c020010, 0x2c2b025, 0x8e020218, 
+0x30424000, 0x10400002, 0x3c020020, 0x2c2b025, 
+0x8e020218, 0x30421000, 0x10400002, 0x3c020040, 
+0x2c2b025, 0x8ee20498, 0x8ee3049c, 0xaf420150, 
+0xaf430154, 0x8ee204a0, 0x8ee304a4, 0xaf420158, 
+0xaf43015c, 0x8ee204a8, 0x8ee304ac, 0xaf420160, 
+0xaf430164, 0x8ee20428, 0x8ee3042c, 0xaf420168, 
+0xaf43016c, 0x8ee20448, 0x8ee3044c, 0xaf420170, 
+0xaf430174, 0x8ee20458, 0x8ee3045c, 0xaf420178, 
+0xaf43017c, 0x8ee20468, 0x8ee3046c, 0xaf420180, 
+0xaf430184, 0x8ee20478, 0x8ee3047c, 0xaf420188, 
+0xaf43018c, 0x8ee20488, 0x8ee3048c, 0xaf420190, 
+0xaf430194, 0x8ee204b0, 0x8ee304b4, 0x24040080, 
+0xaf420198, 0xaf43019c, 0xc002c10, 0x802821, 
+0x8e02025c, 0x27440214, 0xaf4201e0, 0x8e020260, 
+0x24050200, 0x24060008, 0xc002c1b, 0xaf4201e8, 
+0x3c043b9a, 0x3484ca00, 0x3821, 0x24020006, 
+0x24030002, 0xaf4201e4, 0x240203e8, 0xaf4301f4, 
+0xaf4301f0, 0xaf4401ec, 0xaf420284, 0x24020001, 
+0xaf430280, 0xaf42028c, 0x3c030001, 0x671821, 
+0x90634fb8, 0x3471021, 0x24e70001, 0xa043021c, 
+0x2ce2000f, 0x1440fff8, 0x3471821, 0x24e70001, 
+0x3c080001, 0x350840f8, 0x8f820040, 0x3c040001, 
+0x24843e50, 0x24051400, 0xa821, 0x21702, 
+0x24420030, 0xa062021c, 0x3471021, 0xa040021c, 
+0x8ea70218, 0x2c03021, 0x240205b8, 0xafa20010, 
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+0x3c030001, 0x24637220, 0x8c620000, 0x2c424e21, 
+0x14400003, 0x24020002, 0x10000011, 0xac62fff0, 
+0x3c030001, 0x24637240, 0x8c620000, 0x1040000c, 
+0x0, 0x8c62ffdc, 0x14400009, 0x24020002, 
+0x10000007, 0xac62ffd0, 0x3c020001, 0x8c427240, 
+0x10400003, 0x0, 0xc003f28, 0x0, 
+0x8f820220, 0x3c03f700, 0x431025, 0xaf820220, 
+0x8fbf0014, 0x8fb00010, 0x3e00008, 0x27bd0018, 
+0x27bdffe0, 0x3c030001, 0x24637264, 0x30820030, 
+0xafbf0018, 0x14400065, 0xac620000, 0x3c02ffff, 
+0x34421f0e, 0x821024, 0x1440005f, 0x24020030, 
+0x30822000, 0x1040005b, 0x30820001, 0x30838000, 
+0x31a02, 0x21200, 0x3c040001, 0x8c8451ac, 
+0x621825, 0x331c2, 0x30828000, 0x21202, 
+0x30840001, 0x42200, 0x441025, 0x239c2, 
+0x61080, 0xe21021, 0x3c040001, 0x822021, 
+0x908450f8, 0x24020001, 0x10820025, 0x0, 
+0x10800007, 0x24020002, 0x10820013, 0x24020003, 
+0x1082002c, 0x3c05000f, 0x10000037, 0x34a5ffff, 
+0x8f820200, 0x2403feff, 0x431024, 0xaf820200, 
+0x8f820220, 0x3c03fffe, 0x3463ffff, 0x431024, 
+0xaf820220, 0x3c020001, 0x24427284, 0xac400000, 
+0x10000032, 0xac400008, 0x8f820200, 0x34420100, 
+0xaf820200, 0x8f820220, 0x3c03fffe, 0x3463ffff, 
+0x431024, 0x3c030001, 0x24637284, 0xaf820220, 
+0x24020100, 0xac620000, 0x10000024, 0xac600008, 
+0x8f820200, 0x2403feff, 0x431024, 0xaf820200, 
+0x8f820220, 0x3c030001, 0x431025, 0xaf820220, 
+0x3c020001, 0x24427284, 0xac400000, 0x10000017, 
+0xac430008, 0x8f820200, 0x34420100, 0xaf820200, 
+0x8f820220, 0x3c040001, 0x3c030001, 0x24637284, 
+0x441025, 0xaf820220, 0x24020100, 0xac620000, 
+0x1000000a, 0xac640008, 0xafa40010, 0x3c040001, 
+0x24844d70, 0xc002bdf, 0xafa00014, 0x10000003, 
+0x0, 0x24020030, 0xac620004, 0x8fbf0018, 
+0x3e00008, 0x27bd0020, 0x3c030001, 0x24637268, 
+0x8c620000, 0x10400004, 0x34422000, 0xac62fff4, 
+0x3e00008, 0xac600000, 0x3e00008, 0xac64fff4, 
+0x0, 0x0, 0x0, 0x27bdffc8, 
+0xafb20028, 0x809021, 0xafb3002c, 0xa09821, 
+0xafb00020, 0xc08021, 0x3c040001, 0x24844d98, 
+0x3c050009, 0x3c020001, 0x8c425068, 0x34a59001, 
+0x2403021, 0x2603821, 0xafbf0030, 0xafb10024, 
+0xa7a0001a, 0xafb00014, 0xc002bdf, 0xafa20010, 
+0x24020002, 0x126200f2, 0x2e620003, 0x10400005, 
+0x24020001, 0x1262000a, 0x3c02fffb, 0x100000ec, 
+0x0, 0x24020004, 0x12620070, 0x24020008, 
+0x1262006f, 0x3c02ffec, 0x100000e5, 0x0, 
+0x3442ffff, 0x2028024, 0x128940, 0x3c010001, 
+0x310821, 0xac30727c, 0x3c024000, 0x2021024, 
+0x10400048, 0x1023c2, 0x30840030, 0x101382, 
+0x3042000c, 0x3c030001, 0x24635094, 0x431021, 
+0x823821, 0x3c020020, 0x2021024, 0x10400006, 
+0x24020100, 0x3c010001, 0x310821, 0xac227280, 
+0x10000005, 0x3c020080, 0x3c010001, 0x310821, 
+0xac207280, 0x3c020080, 0x2021024, 0x10400007, 
+0x121940, 0x3c020001, 0x3c010001, 0x230821, 
+0xac227288, 0x10000005, 0x0, 0x121140, 
+0x3c010001, 0x220821, 0xac207288, 0x94e30000, 
+0x32024000, 0x10400003, 0xa7a30018, 0x34624000, 
+0xa7a20018, 0x24040001, 0x94e20002, 0x24050004, 
+0x24e60002, 0x441025, 0xc004a09, 0xa4e20002, 
+0x24040001, 0x2821, 0xc004a09, 0x27a60018, 
+0x3c020001, 0x8c425068, 0x24110001, 0x3c010001, 
+0xac315074, 0x14530004, 0x32028000, 0xc003f28, 
+0x0, 0x32028000, 0x1040009d, 0x0, 
+0xc003f28, 0x0, 0x24020002, 0x3c010001, 
+0xac31506c, 0x3c010001, 0xac225068, 0x10000094, 
+0x0, 0x24040001, 0x24050004, 0x27b0001a, 
+0xc004a09, 0x2003021, 0x24040001, 0x2821, 
+0xc004a09, 0x2003021, 0x3c020001, 0x511021, 
+0x8c427274, 0x3c040001, 0x8c845068, 0x3c03bfff, 
+0x3463ffff, 0x3c010001, 0xac335074, 0x431024, 
+0x3c010001, 0x310821, 0xac227274, 0x1093007a, 
+0x0, 0x1000007a, 0x0, 0x3c02ffec, 
+0x3442ffff, 0x2028024, 0x3c020008, 0x2028025, 
+0x121140, 0x3c010001, 0x220821, 0xac307278, 
+0x3c022000, 0x2021024, 0x10400009, 0x0, 
+0x3c020001, 0x8c4250f4, 0x14400005, 0x24020001, 
+0x3c010001, 0xac2251a8, 0x10000004, 0x3c024000, 
+0x3c010001, 0xac2051a8, 0x3c024000, 0x2021024, 
+0x1440001a, 0x0, 0x3c020001, 0x8c4251a8, 
+0x10400005, 0x24022020, 0x3c010001, 0xac2251ac, 
+0x24020001, 0xaee204b8, 0x3c04bfff, 0x121940, 
+0x3c020001, 0x431021, 0x8c427270, 0x3c050001, 
+0x8ca55068, 0x3484ffff, 0x441024, 0x3c010001, 
+0x230821, 0xac227270, 0x24020001, 0x10a20048, 
+0x0, 0x10000044, 0x0, 0x3c020001, 
+0x8c4251a8, 0x1040001f, 0x24022000, 0x3c010001, 
+0xac2251ac, 0x3c0300a0, 0x2031024, 0x14430006, 
+0x121140, 0x3402a000, 0x3c010001, 0xac2251ac, 
+0x10000030, 0x0, 0x3c030001, 0x621821, 
+0x8c637278, 0x3c020020, 0x621024, 0x10400005, 
+0x24022001, 0x3c010001, 0xac2251ac, 0x10000025, 
+0x0, 0x3c020080, 0x621024, 0x10400021, 
+0x3402a001, 0x3c010001, 0xac2251ac, 0x1000001d, 
+0x0, 0x3c020020, 0x2021024, 0x10400007, 
+0x121940, 0x24020100, 0x3c010001, 0x230821, 
+0xac227284, 0x10000006, 0x3c020080, 0x121140, 
+0x3c010001, 0x220821, 0xac207284, 0x3c020080, 
+0x2021024, 0x10400007, 0x121940, 0x3c020001, 
+0x3c010001, 0x230821, 0xac22728c, 0x10000005, 
+0x0, 0x121140, 0x3c010001, 0x220821, 
+0xac20728c, 0x3c030001, 0x8c635068, 0x24020001, 
+0x10620003, 0x0, 0xc003f28, 0x0, 
+0x8fbf0030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 
+0x8fb00020, 0x3e00008, 0x27bd0038, 0x27bdffc8, 
+0xafbe002c, 0x80f021, 0xafb30024, 0x9821, 
+0xafb50028, 0x260a821, 0xafb1001c, 0x2608821, 
+0x24020002, 0xafbf0030, 0xafb20020, 0xafb00018, 
+0xa7a00012, 0x10a2006b, 0xa7a00010, 0x2ca20003, 
+0x10400005, 0x24020001, 0x10a2000a, 0x2201021, 
+0x100000b1, 0x0, 0x24020004, 0x10a20061, 
+0x24020008, 0x10a2005f, 0x2201021, 0x100000aa, 
+0x0, 0x1e9140, 0x3c030001, 0x721821, 
+0x8c63727c, 0x3c024000, 0x621024, 0x14400009, 
+0x24040001, 0x3c027fff, 0x3442ffff, 0x628824, 
+0x3c010001, 0x320821, 0xac317274, 0x1000009a, 
+0x2201021, 0x802821, 0x27b00010, 0xc0049c7, 
+0x2003021, 0x24040001, 0x802821, 0xc0049c7, 
+0x2003021, 0x97a20010, 0x30420004, 0x10400035, 
+0x3c114000, 0x3c030001, 0x8c6351c0, 0x24020003, 
+0x10620008, 0x2c620004, 0x1440002a, 0x3c028000, 
+0x24020004, 0x10620014, 0x3c028000, 0x10000026, 
+0x2221025, 0x24040001, 0x24050011, 0x27b00012, 
+0xc0049c7, 0x2003021, 0x24040001, 0x24050011, 
+0xc0049c7, 0x2003021, 0x97a30012, 0x30624000, 
+0x10400002, 0x3c150010, 0x3c150008, 0x3c130001, 
+0x10000011, 0x30628000, 0x24040001, 0x24050014, 
+0x27b00012, 0xc0049c7, 0x2003021, 0x24040001, 
+0x24050014, 0xc0049c7, 0x2003021, 0x97a30012, 
+0x30621000, 0x10400002, 0x3c150010, 0x3c150008, 
+0x3c130001, 0x30620800, 0x54400001, 0x3c130002, 
+0x3c028000, 0x2221025, 0x2751825, 0x10000007, 
+0x438825, 0x3c110001, 0x2328821, 0x8e31727c, 
+0x3c027fff, 0x3442ffff, 0x2228824, 0x1e1140, 
+0x3c010001, 0x220821, 0xac317274, 0x1000004e, 
+0x2201021, 0x1e2940, 0x3c030001, 0x651821, 
+0x8c637278, 0x3c024000, 0x621024, 0x14400008, 
+0x3c027fff, 0x3442ffff, 0x628824, 0x3c010001, 
+0x250821, 0xac317270, 0x1000003f, 0x2201021, 
+0x3c020001, 0x8c425078, 0x10400033, 0x3c11c00c, 
+0x3c020001, 0x8c4250f4, 0x2202021, 0x34842000, 
+0x3c030001, 0x8c6351a8, 0x2102b, 0x21023, 
+0x441024, 0x10600003, 0x518825, 0x3c022000, 
+0x2228825, 0x3c020001, 0x451021, 0x8c427284, 
+0x10400003, 0x3c020020, 0x10000004, 0x2228825, 
+0x3c02ffdf, 0x3442ffff, 0x2228824, 0x1e1140, 
+0x3c010001, 0x220821, 0x8c22728c, 0x10400003, 
+0x3c020080, 0x10000004, 0x2228825, 0x3c02ff7f, 
+0x3442ffff, 0x2228824, 0x3c020001, 0x8c4250e0, 
+0x10400002, 0x3c020800, 0x2228825, 0x3c020001, 
+0x8c4250e4, 0x10400002, 0x3c020400, 0x2228825, 
+0x3c020001, 0x8c4250e8, 0x10400006, 0x3c020100, 
+0x10000004, 0x2228825, 0x3c027fff, 0x3442ffff, 
+0x628824, 0x1e1140, 0x3c010001, 0x220821, 
+0xac317270, 0x2201021, 0x8fbf0030, 0x8fbe002c, 
+0x8fb50028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 
+0x8fb00018, 0x3e00008, 0x27bd0038, 0x27bdffe0, 
+0xafb20018, 0x809021, 0xafbf001c, 0xafb10014, 
+0xafb00010, 0x8f840200, 0x3c030001, 0x8c635068, 
+0x8f860220, 0x24020002, 0x106200a8, 0x2c620003, 
+0x10400005, 0x24020001, 0x1062000a, 0x121940, 
+0x100000a2, 0x0, 0x24020004, 0x10620054, 
+0x24020008, 0x10620053, 0x128940, 0x1000009b, 
+0x0, 0x3c050001, 0xa32821, 0x8ca5727c, 
+0x3c100001, 0x2038021, 0x8e107274, 0x3c024000, 
+0xa21024, 0x10400038, 0x3c020008, 0x2021024, 
+0x10400020, 0x34840002, 0x3c020001, 0x431021, 
+0x8c427280, 0x10400005, 0x34840020, 0x34840100, 
+0x3c020020, 0x10000006, 0x2028025, 0x2402feff, 
+0x822024, 0x3c02ffdf, 0x3442ffff, 0x2028024, 
+0x121140, 0x3c010001, 0x220821, 0x8c227288, 
+0x10400005, 0x3c020001, 0xc23025, 0x3c020080, 
+0x10000016, 0x2028025, 0x3c02fffe, 0x3442ffff, 
+0xc23024, 0x3c02ff7f, 0x3442ffff, 0x1000000f, 
+0x2028024, 0x2402fedf, 0x822024, 0x3c02fffe, 
+0x3442ffff, 0xc23024, 0x3c02ff5f, 0x3442ffff, 
+0x2028024, 0x3c010001, 0x230821, 0xac207280, 
+0x3c010001, 0x230821, 0xac207288, 0xaf840200, 
+0xaf860220, 0x8f820220, 0x34420002, 0xaf820220, 
+0x1000000a, 0x121140, 0x3c02bfff, 0x3442ffff, 
+0x8f830200, 0x2028024, 0x2402fffd, 0x621824, 
+0xc003f28, 0xaf830200, 0x121140, 0x3c010001, 
+0x220821, 0xac307274, 0x1000004c, 0x0, 
+0x128940, 0x3c050001, 0xb12821, 0x8ca57278, 
+0x3c100001, 0x2118021, 0x8e107270, 0x3c024000, 
+0xa21024, 0x14400011, 0x0, 0x3c020001, 
+0x8c4251a8, 0x14400005, 0x3c02bfff, 0x8f820200, 
+0x34420002, 0xaf820200, 0x3c02bfff, 0x3442ffff, 
+0xc003f28, 0x2028024, 0x3c010001, 0x310821, 
+0xac307270, 0x10000031, 0x0, 0x3c020001, 
+0x8c4251a8, 0x10400005, 0x3c020020, 0x3c020001, 
+0x8c4250f4, 0x10400025, 0x3c020020, 0xa21024, 
+0x10400007, 0x34840020, 0x24020100, 0x3c010001, 
+0x310821, 0xac227284, 0x10000006, 0x822025, 
+0x3c010001, 0x310821, 0xac207284, 0x2402feff, 
+0x822024, 0x3c020080, 0xa21024, 0x10400007, 
+0x121940, 0x3c020001, 0x3c010001, 0x230821, 
+0xac22728c, 0x10000008, 0xc23025, 0x121140, 
+0x3c010001, 0x220821, 0xac20728c, 0x3c02fffe, 
+0x3442ffff, 0xc23024, 0xaf840200, 0xaf860220, 
+0x8f820220, 0x34420002, 0xaf820220, 0x121140, 
+0x3c010001, 0x220821, 0xac307270, 0x8fbf001c, 
+0x8fb20018, 0x8fb10014, 0x8fb00010, 0x3e00008, 
+0x27bd0020, 0x0, 0x0, 0x1821, 
+0x308400ff, 0x2405ffdf, 0x2406ffbf, 0x641007, 
+0x30420001, 0x10400004, 0x0, 0x8f820044, 
+0x10000003, 0x34420040, 0x8f820044, 0x461024, 
+0xaf820044, 0x8f820044, 0x34420020, 0xaf820044, 
+0x8f820044, 0x451024, 0xaf820044, 0x24630001, 
+0x28620008, 0x1440ffee, 0x641007, 0x3e00008, 
+0x0, 0x0, 0x0, 0x0 };
+static u_int32_t tigon2FwRodata[] = {
+0x24486561, 
+0x6465723a, 0x202f7072, 0x6f6a6563, 0x74732f72, 
+0x63732f73, 0x772f6765, 0x2f2e2f6e, 0x69632f66, 
+0x77322f63, 0x6f6d6d6f, 0x6e2f6677, 0x6d61696e, 
+0x2e632c76, 0x20312e31, 0x2e322e34, 0x35203139, 
+0x39392f30, 0x312f3234, 0x2030303a, 0x31303a35, 
+0x35207368, 0x75616e67, 0x20457870, 0x20240000, 
+0x65767452, 0x6e674600, 0x51657674, 0x46000000, 
+0x51657674, 0x505f4600, 0x4d657674, 0x526e6746, 
+0x0, 0x4d516576, 0x74460000, 0x4d516576, 
+0x505f4600, 0x5173436f, 0x6e495f46, 0x0, 
+0x5173436f, 0x6e734600, 0x51725072, 0x6f644600, 
+0x6261644d, 0x656d537a, 0x0, 0x2a50414e, 
+0x49432a00, 0x66776d61, 0x696e2e63, 0x0, 
+0x68774677, 0x56657200, 0x62616448, 0x77566572, 
+0x0, 0x2a2a4441, 0x574e5f41, 0x0, 
+0x74785278, 0x4266537a, 0x0, 0x62664174, 
+0x6e4d726b, 0x0, 0x7265645a, 0x6f6e6531, 
+0x0, 0x70636943, 0x6f6e6600, 0x67656e43, 
+0x6f6e6600, 0x72636246, 0x6c616773, 0x0, 
+0x62616452, 0x78526362, 0x0, 0x676c6f62, 
+0x466c6773, 0x0, 0x2b5f6469, 0x73705f6c, 
+0x6f6f7000, 0x2b65765f, 0x68616e64, 0x6c657200, 
+0x63616e74, 0x31446d61, 0x0, 0x2b715f64, 
+0x6d615f74, 0x6f5f6e69, 0x635f636b, 0x73756d00, 
+0x2b685f73, 0x656e645f, 0x64617461, 0x5f726561, 
+0x64795f63, 0x6b73756d, 0x0, 0x2b685f64, 
+0x6d615f72, 0x645f6173, 0x73697374, 0x5f636b73, 
+0x756d0000, 0x74436b73, 0x6d4f6e00, 0x2b715f64, 
+0x6d615f74, 0x6f5f6e69, 0x63000000, 0x2b685f73, 
+0x656e645f, 0x64617461, 0x5f726561, 0x64790000, 
+0x2b685f64, 0x6d615f72, 0x645f6173, 0x73697374, 
+0x0, 0x74436b73, 0x6d4f6666, 0x0, 
+0x2b685f73, 0x656e645f, 0x62645f72, 0x65616479, 
+0x0, 0x68737453, 0x52696e67, 0x0, 
+0x62616453, 0x52696e67, 0x0, 0x6e696353, 
+0x52696e67, 0x0, 0x77446d61, 0x416c6c41, 
+0x0, 0x2b715f64, 0x6d615f74, 0x6f5f686f, 
+0x73745f63, 0x6b73756d, 0x0, 0x2b685f6d, 
+0x61635f72, 0x785f636f, 0x6d705f63, 0x6b73756d, 
+0x0, 0x2b685f64, 0x6d615f77, 0x725f6173, 
+0x73697374, 0x5f636b73, 0x756d0000, 0x72436b73, 
+0x6d4f6e00, 0x2b715f64, 0x6d615f74, 0x6f5f686f, 
+0x73740000, 0x2b685f6d, 0x61635f72, 0x785f636f, 
+0x6d700000, 0x2b685f64, 0x6d615f77, 0x725f6173, 
+0x73697374, 0x0, 0x72436b73, 0x6d4f6666, 
+0x0, 0x2b685f72, 0x6563765f, 0x62645f72, 
+0x65616479, 0x0, 0x2b685f72, 0x6563765f, 
+0x6a756d62, 0x6f5f6264, 0x5f726561, 0x64790000, 
+0x2b685f72, 0x6563765f, 0x6d696e69, 0x5f62645f, 
+0x72656164, 0x79000000, 0x2b6d685f, 0x636f6d6d, 
+0x616e6400, 0x2b685f74, 0x696d6572, 0x0, 
+0x2b685f64, 0x6f5f7570, 0x64617465, 0x5f74785f, 
+0x636f6e73, 0x0, 0x2b685f64, 0x6f5f7570, 
+0x64617465, 0x5f72785f, 0x70726f64, 0x0, 
+0x2b636b73, 0x756d3136, 0x0, 0x2b706565, 
+0x6b5f6d61, 0x635f7278, 0x0, 0x2b646571, 
+0x5f6d6163, 0x5f727800, 0x2b685f6d, 0x61635f72, 
+0x785f6174, 0x746e0000, 0x62616452, 0x6574537a, 
+0x0, 0x72784264, 0x4266537a, 0x0, 
+0x2b6e756c, 0x6c5f6861, 0x6e646c65, 0x72000000, 
+0x66774f70, 0x4661696c, 0x0, 0x2b685f75, 
+0x70646174, 0x655f6c65, 0x64360000, 0x2b685f75, 
+0x70646174, 0x655f6c65, 0x64320000, 0x696e7453, 
+0x74617465, 0x0, 0x2a2a696e, 0x69744370, 
+0x0, 0x23736372, 0x65616d00, 0x69537461, 
+0x636b4572, 0x0, 0x70726f62, 0x654d656d, 
+0x0, 0x2a2a4441, 0x574e5f42, 0x0, 
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+0x632e6800, 0x11850, 0x11920, 0x119f8, 
+0x11ac8, 0x11b2c, 0x11c08, 0x11c30, 
+0x11d0c, 0x11d34, 0x11edc, 0x11f04, 
+0x120ac, 0x122a4, 0x1253c, 0x1244c, 
+0x1253c, 0x12568, 0x120d4, 0x1227c, 
+0x0, 0x0, 0x0, 0x2a50414e, 
+0x49432a00, 0x2e2e2f63, 0x6f6d6d6f, 0x6e2f6d61, 
+0x632e6800, 0x12a68, 0x12a94, 0x12b0c, 
+0x12b4c, 0x12bac, 0x12c34, 0x12c60, 
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+0x632e6800, 0x73746d61, 0x634c4e4b, 0x0, 
+0x0, 0x0, 0x0, 0x0 };
+static u_int32_t tigon2FwData[] = {
+0x1, 
+0x1, 0x1, 0xc001fc, 0x3ffc, 
+0xc00000, 0x416c7465, 0x6f6e2041, 0x63654e49, 
+0x43205600, 0x0, 0x0, 0x416c7465, 
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+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x3, 0x0, 
+0x1, 0x0, 0x0, 0x1, 
+0x0, 0x0, 0x0, 0x1, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x1000000, 0x21000000, 0x12000140, 
+0x0, 0x0, 0x20000000, 0x120000a0, 
+0x0, 0x12000060, 0x12000180, 0x120001e0, 
+0x0, 0x0, 0x0, 0x0, 
+0x0, 0x0, 0x0, 0x2, 
+0x0, 0x0, 0x30001, 0x1, 
+0x30201, 0x0, 0x0, 0x0 };