diff options
author | Kenneth R Westerback <krw@cvs.openbsd.org> | 2004-03-06 03:03:08 +0000 |
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committer | Kenneth R Westerback <krw@cvs.openbsd.org> | 2004-03-06 03:03:08 +0000 |
commit | 090676220cee4b607f70cde0e711df0b9ba5ed2a (patch) | |
tree | f4624cc2281a7af52363edfc384623c26f08c21f /sys/dev | |
parent | c9c5a960b51917f9efd8121b39d7cc34f28e9e27 (diff) |
Initial version of driver for LSI MPT devices, like the U320 1030.
Basically works but much still to fix/implement.
From NetBSD via Milos Urbanek and Marco Peereboom.
Diffstat (limited to 'sys/dev')
-rw-r--r-- | sys/dev/ic/mpt.c | 1217 | ||||
-rw-r--r-- | sys/dev/ic/mpt.c.orig | 0 | ||||
-rw-r--r-- | sys/dev/ic/mpt.h | 191 | ||||
-rw-r--r-- | sys/dev/ic/mpt.h.orig | 0 | ||||
-rw-r--r-- | sys/dev/ic/mpt_debug.c | 608 | ||||
-rw-r--r-- | sys/dev/ic/mpt_debug.c.orig | 0 | ||||
-rw-r--r-- | sys/dev/ic/mpt_mpilib.h | 4259 | ||||
-rw-r--r-- | sys/dev/ic/mpt_mpilib.h.orig | 0 | ||||
-rw-r--r-- | sys/dev/ic/mpt_openbsd.c | 1388 | ||||
-rw-r--r-- | sys/dev/ic/mpt_openbsd.c.orig | 0 | ||||
-rw-r--r-- | sys/dev/ic/mpt_openbsd.h | 298 | ||||
-rw-r--r-- | sys/dev/ic/mpt_openbsd.h.orig | 0 | ||||
-rw-r--r-- | sys/dev/pci/mpt_pci.c | 402 | ||||
-rw-r--r-- | sys/dev/pci/mpt_pci.c.orig | 0 |
14 files changed, 8363 insertions, 0 deletions
diff --git a/sys/dev/ic/mpt.c b/sys/dev/ic/mpt.c new file mode 100644 index 00000000000..f21241b5052 --- /dev/null +++ b/sys/dev/ic/mpt.c @@ -0,0 +1,1217 @@ +/* $OpenBSD: mpt.c,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt.c,v 1.4 2003/11/02 11:07:45 wiz Exp $ */ + +/* + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +/* + * mpt.c: + * + * Generic routines for LSI Fusion adapters. + * + * Adapted from the FreeBSD "mpt" driver by Jason R. Thorpe for + * Wasabi Systems, Inc. + */ + +#include <sys/cdefs.h> +/* __KERNEL_RCSID(0, "$NetBSD: mpt.c,v 1.4 2003/11/02 11:07:45 wiz Exp $"); */ + +#include <dev/ic/mpt.h> + +#define MPT_MAX_TRYS 3 +#define MPT_MAX_WAIT 300000 + +static int maxwait_ack = 0; +static int maxwait_int = 0; +static int maxwait_state = 0; + +static __inline u_int32_t +mpt_rd_db(mpt_softc_t *mpt) +{ + return mpt_read(mpt, MPT_OFFSET_DOORBELL); +} + +static __inline u_int32_t +mpt_rd_intr(mpt_softc_t *mpt) +{ + return mpt_read(mpt, MPT_OFFSET_INTR_STATUS); +} + +/* Busy wait for a door bell to be read by IOC */ +static int +mpt_wait_db_ack(mpt_softc_t *mpt) +{ + int i; + for (i=0; i < MPT_MAX_WAIT; i++) { + if (!MPT_DB_IS_BUSY(mpt_rd_intr(mpt))) { + maxwait_ack = i > maxwait_ack ? i : maxwait_ack; + return MPT_OK; + } + + DELAY(100); + } + return MPT_FAIL; +} + +/* Busy wait for a door bell interrupt */ +static int +mpt_wait_db_int(mpt_softc_t *mpt) +{ + int i; + for (i=0; i < MPT_MAX_WAIT; i++) { + if (MPT_DB_INTR(mpt_rd_intr(mpt))) { + maxwait_int = i > maxwait_int ? i : maxwait_int; + return MPT_OK; + } + DELAY(100); + } + return MPT_FAIL; +} + +/* Wait for IOC to transition to a give state */ +void +mpt_check_doorbell(mpt_softc_t *mpt) +{ + u_int32_t db = mpt_rd_db(mpt); + if (MPT_STATE(db) != MPT_DB_STATE_RUNNING) { + mpt_prt(mpt, "Device not running"); + mpt_print_db(db); + } +} + +/* Wait for IOC to transition to a give state */ +static int +mpt_wait_state(mpt_softc_t *mpt, enum DB_STATE_BITS state) +{ + int i; + + for (i = 0; i < MPT_MAX_WAIT; i++) { + u_int32_t db = mpt_rd_db(mpt); + if (MPT_STATE(db) == state) { + maxwait_state = i > maxwait_state ? i : maxwait_state; + return (MPT_OK); + } + DELAY(100); + } + return (MPT_FAIL); +} + + +/* Issue the reset COMMAND to the IOC */ +int +mpt_soft_reset(mpt_softc_t *mpt) +{ + if (mpt->verbose) { + mpt_prt(mpt, "soft reset"); + } + + /* Have to use hard reset if we are not in Running state */ + if (MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_RUNNING) { + mpt_prt(mpt, "soft reset failed: device not running"); + return MPT_FAIL; + } + + /* If door bell is in use we don't have a chance of getting + * a word in since the IOC probably crashed in message + * processing. So don't waste our time. + */ + if (MPT_DB_IS_IN_USE(mpt_rd_db(mpt))) { + mpt_prt(mpt, "soft reset failed: doorbell wedged"); + return MPT_FAIL; + } + + /* Send the reset request to the IOC */ + mpt_write(mpt, MPT_OFFSET_DOORBELL, + MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET << MPI_DOORBELL_FUNCTION_SHIFT); + if (mpt_wait_db_ack(mpt) != MPT_OK) { + mpt_prt(mpt, "soft reset failed: ack timeout"); + return MPT_FAIL; + } + + /* Wait for the IOC to reload and come out of reset state */ + if (mpt_wait_state(mpt, MPT_DB_STATE_READY) != MPT_OK) { + mpt_prt(mpt, "soft reset failed: device did not start running"); + return MPT_FAIL; + } + + return MPT_OK; +} + +/* This is a magic diagnostic reset that resets all the ARM + * processors in the chip. + */ +void +mpt_hard_reset(mpt_softc_t *mpt) +{ + /* This extra read comes for the Linux source + * released by LSI. It's function is undocumented! + */ + if (mpt->verbose) { + mpt_prt(mpt, "hard reset"); + } + mpt_read(mpt, MPT_OFFSET_FUBAR); + + /* Enable diagnostic registers */ + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_1); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_2); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_3); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_4); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_5); + + /* Diag. port is now active so we can now hit the reset bit */ + mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, MPT_DIAG_RESET_IOC); + + DELAY(10000); + + /* Disable Diagnostic Register */ + mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFF); + + /* Restore the config register values */ + /* Hard resets are known to screw up the BAR for diagnostic + memory accesses (Mem1). */ + mpt_set_config_regs(mpt); + if (mpt->mpt2 != NULL) { + mpt_set_config_regs(mpt->mpt2); + } + + /* Note that if there is no valid firmware to run, the doorbell will + remain in the reset state (0x00000000) */ +} + +/* + * Reset the IOC when needed. Try software command first then if needed + * poke at the magic diagnostic reset. Note that a hard reset resets + * *both* IOCs on dual function chips (FC929 && LSI1030) as well as + * fouls up the PCI configuration registers. + */ +int +mpt_reset(mpt_softc_t *mpt) +{ + int ret; + + /* Try a soft reset */ + if ((ret = mpt_soft_reset(mpt)) != MPT_OK) { + /* Failed; do a hard reset */ + mpt_hard_reset(mpt); + + /* Wait for the IOC to reload and come out of reset state */ + ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); + if (ret != MPT_OK) { + mpt_prt(mpt, "failed to reset device"); + } + } + + return ret; +} + +/* Return a command buffer to the free queue */ +void +mpt_free_request(mpt_softc_t *mpt, request_t *req) +{ + if (req == NULL || req != &mpt->request_pool[req->index]) { + panic("mpt_free_request bad req ptr\n"); + return; + } + if (req->debug == REQ_FREE) { + /* + * XXX MU this should not happen but do not corrupt the free + * list if it does + */ + mpt_prt(mpt, "request %d already free\n", req->index); + return; + } + req->sequence = 0; + req->xfer = NULL; + req->debug = REQ_FREE; + SLIST_INSERT_HEAD(&mpt->request_free_list, req, link); +} + +/* Initialize command buffer */ +void +mpt_init_request(mpt_softc_t *mpt, request_t *req) +{ + if (req == NULL || req != &mpt->request_pool[req->index]) { + panic("mpt_init_request bad req ptr\n"); + return; + } + req->sequence = 0; + req->xfer = NULL; + req->debug = REQ_FREE; + SLIST_INSERT_HEAD(&mpt->request_free_list, req, link); +} +/* Get a command buffer from the free queue */ +request_t * +mpt_get_request(mpt_softc_t *mpt) +{ + request_t *req; + req = SLIST_FIRST(&mpt->request_free_list); + if (req != NULL) { + if (req != &mpt->request_pool[req->index]) { + panic("mpt_get_request: corrupted request free list\n"); + } + if (req->xfer != NULL) { + panic("mpt_get_request: corrupted request free list (xfer)\n"); + } + SLIST_REMOVE_HEAD(&mpt->request_free_list, link); + req->debug = REQ_IN_PROGRESS; + } + return req; +} + +/* Pass the command to the IOC */ +void +mpt_send_cmd(mpt_softc_t *mpt, request_t *req) +{ + req->sequence = mpt->sequence++; + if (mpt->verbose > 1) { + u_int32_t *pReq; + pReq = req->req_vbuf; + mpt_prt(mpt, "Send Request %d (0x%x):", + req->index, req->req_pbuf); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[0], pReq[1], pReq[2], pReq[3]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[4], pReq[5], pReq[6], pReq[7]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[8], pReq[9], pReq[10], pReq[11]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[12], pReq[13], pReq[14], pReq[15]); + } + MPT_SYNC_REQ(mpt, req, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); + req->debug = REQ_ON_CHIP; + mpt_write(mpt, MPT_OFFSET_REQUEST_Q, (u_int32_t) req->req_pbuf); +} + +/* + * Give the reply buffer back to the IOC after we have + * finished processing it. + */ +void +mpt_free_reply(mpt_softc_t *mpt, u_int32_t ptr) +{ + mpt_write(mpt, MPT_OFFSET_REPLY_Q, ptr); +} + +/* Get a reply from the IOC */ +u_int32_t +mpt_pop_reply_queue(mpt_softc_t *mpt) +{ + return mpt_read(mpt, MPT_OFFSET_REPLY_Q); +} + +/* + * Send a command to the IOC via the handshake register. + * + * Only done at initialization time and for certain unusual + * commands such as device/bus reset as specified by LSI. + */ +int +mpt_send_handshake_cmd(mpt_softc_t *mpt, size_t len, void *cmd) +{ + int i; + u_int32_t data, *data32; + + /* Check condition of the IOC */ + data = mpt_rd_db(mpt); + if (((MPT_STATE(data) != MPT_DB_STATE_READY) && + (MPT_STATE(data) != MPT_DB_STATE_RUNNING) && + (MPT_STATE(data) != MPT_DB_STATE_FAULT)) || + ( MPT_DB_IS_IN_USE(data) )) { + mpt_prt(mpt, "handshake aborted due to invalid doorbell state"); + mpt_print_db(data); + return(EBUSY); + } + + /* We move things in 32 bit chunks */ + len = (len + 3) >> 2; + data32 = cmd; + + /* Clear any left over pending doorbell interrupts */ + if (MPT_DB_INTR(mpt_rd_intr(mpt))) + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + /* + * Tell the handshake reg. we are going to send a command + * and how long it is going to be. + */ + data = (MPI_FUNCTION_HANDSHAKE << MPI_DOORBELL_FUNCTION_SHIFT) | + (len << MPI_DOORBELL_ADD_DWORDS_SHIFT); + mpt_write(mpt, MPT_OFFSET_DOORBELL, data); + + /* Wait for the chip to notice */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_send_handshake_cmd timeout1"); + return ETIMEDOUT; + } + + /* Clear the interrupt */ + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + if (mpt_wait_db_ack(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_send_handshake_cmd timeout2"); + return ETIMEDOUT; + } + + /* Send the command */ + for (i = 0; i < len; i++) { + mpt_write(mpt, MPT_OFFSET_DOORBELL, *data32++); + if (mpt_wait_db_ack(mpt) != MPT_OK) { + mpt_prt(mpt, + "mpt_send_handshake_cmd timeout! index = %d", i); + return ETIMEDOUT; + } + } + return MPT_OK; +} + +/* Get the response from the handshake register */ +int +mpt_recv_handshake_reply(mpt_softc_t *mpt, size_t reply_len, void *reply) +{ + int left, reply_left; + u_int16_t *data16; + MSG_DEFAULT_REPLY *hdr; + + /* We move things out in 16 bit chunks */ + reply_len >>= 1; + data16 = (u_int16_t *)reply; + + hdr = (MSG_DEFAULT_REPLY *)reply; + + /* Get first word */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout1"); + return ETIMEDOUT; + } + *data16++ = mpt_read(mpt, MPT_OFFSET_DOORBELL) & MPT_DB_DATA_MASK; + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + /* Get Second Word */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout2"); + return ETIMEDOUT; + } + *data16++ = mpt_read(mpt, MPT_OFFSET_DOORBELL) & MPT_DB_DATA_MASK; + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + /* With the second word, we can now look at the length */ + if (mpt->verbose > 1 && ((reply_len >> 1) != hdr->MsgLength)) { + mpt_prt(mpt, "reply length does not match message length: " + "got 0x%02x, expected 0x%02x", + hdr->MsgLength << 2, reply_len << 1); + } + + /* Get rest of the reply; but don't overflow the provided buffer */ + left = (hdr->MsgLength << 1) - 2; + reply_left = reply_len - 2; + while (left--) { + u_int16_t datum; + + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout3"); + return ETIMEDOUT; + } + datum = mpt_read(mpt, MPT_OFFSET_DOORBELL); + + if (reply_left-- > 0) + *data16++ = datum & MPT_DB_DATA_MASK; + + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + } + + /* One more wait & clear at the end */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout4"); + return ETIMEDOUT; + } + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + if ((hdr->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + if (mpt->verbose > 1) + mpt_print_reply(hdr); + return (MPT_FAIL | hdr->IOCStatus); + } + + return (0); +} + +static int +mpt_get_iocfacts(mpt_softc_t *mpt, MSG_IOC_FACTS_REPLY *freplp) +{ + MSG_IOC_FACTS f_req; + int error; + + bzero(&f_req, sizeof f_req); + f_req.Function = MPI_FUNCTION_IOC_FACTS; + f_req.MsgContext = 0x12071942; + error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); + if (error) + return(error); + error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); + return (error); +} + +static int +mpt_get_portfacts(mpt_softc_t *mpt, MSG_PORT_FACTS_REPLY *freplp) +{ + MSG_PORT_FACTS f_req; + int error; + + /* XXX: Only getting PORT FACTS for Port 0 */ + bzero(&f_req, sizeof f_req); + f_req.Function = MPI_FUNCTION_PORT_FACTS; + f_req.MsgContext = 0x12071943; + error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); + if (error) + return(error); + error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); + return (error); +} + +/* + * Send the initialization request. This is where we specify how many + * SCSI busses and how many devices per bus we wish to emulate. + * This is also the command that specifies the max size of the reply + * frames from the IOC that we will be allocating. + */ +static int +mpt_send_ioc_init(mpt_softc_t *mpt, u_int32_t who) +{ + int error = 0; + MSG_IOC_INIT init; + MSG_IOC_INIT_REPLY reply; + + bzero(&init, sizeof init); + init.WhoInit = who; + init.Function = MPI_FUNCTION_IOC_INIT; + if (mpt->is_fc) { + init.MaxDevices = 255; + } else { + init.MaxDevices = 16; + } + init.MaxBuses = 1; + init.ReplyFrameSize = MPT_REPLY_SIZE; + init.MsgContext = 0x12071941; + + if ((error = mpt_send_handshake_cmd(mpt, sizeof init, &init)) != 0) { + return(error); + } + + error = mpt_recv_handshake_reply(mpt, sizeof reply, &reply); + return (error); +} + + +/* + * Utiltity routine to read configuration headers and pages + */ + +static int +mpt_read_cfg_header(mpt_softc_t *, int, int, int, fCONFIG_PAGE_HEADER *); + +static int +mpt_read_cfg_header(mpt_softc_t *mpt, int PageType, int PageNumber, + int PageAddress, fCONFIG_PAGE_HEADER *rslt) +{ + int count; + request_t *req; + MSG_CONFIG *cfgp; + MSG_CONFIG_REPLY *reply; + + req = mpt_get_request(mpt); + + cfgp = req->req_vbuf; + bzero(cfgp, sizeof *cfgp); + + cfgp->Action = MPI_CONFIG_ACTION_PAGE_HEADER; + cfgp->Function = MPI_FUNCTION_CONFIG; + cfgp->Header.PageNumber = (U8) PageNumber; + cfgp->Header.PageType = (U8) PageType; + cfgp->PageAddress = PageAddress; + MPI_pSGE_SET_FLAGS(((SGE_SIMPLE32 *) &cfgp->PageBufferSGE), + (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_SIMPLE_ELEMENT | MPI_SGE_FLAGS_END_OF_LIST)); + cfgp->MsgContext = req->index | 0x80000000; + + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 1000) { + mpt_prt(mpt, "read_cfg_header timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + + reply = (MSG_CONFIG_REPLY *) MPT_REPLY_PTOV(mpt, req->sequence); + if ((reply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + mpt_prt(mpt, "mpt_read_cfg_header: Config Info Status %x", + reply->IOCStatus); + mpt_free_reply(mpt, (req->sequence << 1)); + return (-1); + } + bcopy(&reply->Header, rslt, sizeof (fCONFIG_PAGE_HEADER)); + mpt_free_reply(mpt, (req->sequence << 1)); + mpt_free_request(mpt, req); + return (0); +} + +#define CFG_DATA_OFF 128 + +int +mpt_read_cfg_page(mpt_softc_t *mpt, int PageAddress, fCONFIG_PAGE_HEADER *hdr) +{ + int count; + request_t *req; + SGE_SIMPLE32 *se; + MSG_CONFIG *cfgp; + size_t amt; + MSG_CONFIG_REPLY *reply; + + req = mpt_get_request(mpt); + + cfgp = req->req_vbuf; + bzero(cfgp, MPT_REQUEST_AREA); + cfgp->Action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfgp->Function = MPI_FUNCTION_CONFIG; + cfgp->Header = *hdr; + amt = (cfgp->Header.PageLength * sizeof (u_int32_t)); + cfgp->Header.PageType &= MPI_CONFIG_PAGETYPE_MASK; + cfgp->PageAddress = PageAddress; + se = (SGE_SIMPLE32 *) &cfgp->PageBufferSGE; + se->Address = req->req_pbuf + CFG_DATA_OFF; + MPI_pSGE_SET_LENGTH(se, amt); + MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | + MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_END_OF_LIST)); + + cfgp->MsgContext = req->index | 0x80000000; + + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 1000) { + mpt_prt(mpt, "read_cfg_page timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + + reply = (MSG_CONFIG_REPLY *) MPT_REPLY_PTOV(mpt, req->sequence); + if ((reply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + mpt_prt(mpt, "mpt_read_cfg_page: Config Info Status %x", + reply->IOCStatus); + mpt_free_reply(mpt, (req->sequence << 1)); + return (-1); + } + mpt_free_reply(mpt, (req->sequence << 1)); +#if 0 /* XXXJRT */ + bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, + BUS_DMASYNC_POSTREAD); +#endif + if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 0) { + amt = sizeof (fCONFIG_PAGE_SCSI_PORT_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 1) { + amt = sizeof (fCONFIG_PAGE_SCSI_PORT_1); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 2) { + amt = sizeof (fCONFIG_PAGE_SCSI_PORT_2); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 0) { + amt = sizeof (fCONFIG_PAGE_SCSI_DEVICE_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 1) { + amt = sizeof (fCONFIG_PAGE_SCSI_DEVICE_1); + } + bcopy(((caddr_t)req->req_vbuf)+CFG_DATA_OFF, hdr, amt); + mpt_free_request(mpt, req); + return (0); +} + +int +mpt_write_cfg_page(mpt_softc_t *mpt, int PageAddress, fCONFIG_PAGE_HEADER *hdr) +{ + int count, hdr_attr; + request_t *req; + SGE_SIMPLE32 *se; + MSG_CONFIG *cfgp; + size_t amt; + MSG_CONFIG_REPLY *reply; + + req = mpt_get_request(mpt); + + cfgp = req->req_vbuf; + bzero(cfgp, sizeof *cfgp); + + hdr_attr = hdr->PageType & MPI_CONFIG_PAGEATTR_MASK; + if (hdr_attr != MPI_CONFIG_PAGEATTR_CHANGEABLE && + hdr_attr != MPI_CONFIG_PAGEATTR_PERSISTENT) { + mpt_prt(mpt, "page type 0x%x not changeable", + hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); + return (-1); + } + hdr->PageType &= MPI_CONFIG_PAGETYPE_MASK; + + cfgp->Action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; + cfgp->Function = MPI_FUNCTION_CONFIG; + cfgp->Header = *hdr; + amt = (cfgp->Header.PageLength * sizeof (u_int32_t)); + cfgp->PageAddress = PageAddress; + + se = (SGE_SIMPLE32 *) &cfgp->PageBufferSGE; + se->Address = req->req_pbuf + CFG_DATA_OFF; + MPI_pSGE_SET_LENGTH(se, amt); + MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | + MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_END_OF_LIST | MPI_SGE_FLAGS_HOST_TO_IOC)); + + cfgp->MsgContext = req->index | 0x80000000; + + if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 0) { + amt = sizeof (fCONFIG_PAGE_SCSI_PORT_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 1) { + amt = sizeof (fCONFIG_PAGE_SCSI_PORT_1); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 2) { + amt = sizeof (fCONFIG_PAGE_SCSI_PORT_2); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 0) { + amt = sizeof (fCONFIG_PAGE_SCSI_DEVICE_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 1) { + amt = sizeof (fCONFIG_PAGE_SCSI_DEVICE_1); + } + bcopy(hdr, ((caddr_t)req->req_vbuf)+CFG_DATA_OFF, amt); + /* Restore stripped out attributes */ + hdr->PageType |= hdr_attr; + + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 1000) { + hdr->PageType |= hdr_attr; + mpt_prt(mpt, "mpt_write_cfg_page timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + + reply = (MSG_CONFIG_REPLY *) MPT_REPLY_PTOV(mpt, req->sequence); + if ((reply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + mpt_prt(mpt, "mpt_write_cfg_page: Config Info Status %x", + reply->IOCStatus); + mpt_free_reply(mpt, (req->sequence << 1)); + return (-1); + } + mpt_free_reply(mpt, (req->sequence << 1)); + + mpt_free_request(mpt, req); + return (0); +} + +/* + * Read SCSI configuration information + */ +static int +mpt_read_config_info_spi(mpt_softc_t *mpt) +{ + int rv, i; + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_PORT, 0, + 0, &mpt->mpt_port_page0.Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, "SPI Port Page 0 Header: %x %x %x %x", + mpt->mpt_port_page0.Header.PageVersion, + mpt->mpt_port_page0.Header.PageLength, + mpt->mpt_port_page0.Header.PageNumber, + mpt->mpt_port_page0.Header.PageType); + } + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_PORT, 1, + 0, &mpt->mpt_port_page1.Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, "SPI Port Page 1 Header: %x %x %x %x", + mpt->mpt_port_page1.Header.PageVersion, + mpt->mpt_port_page1.Header.PageLength, + mpt->mpt_port_page1.Header.PageNumber, + mpt->mpt_port_page1.Header.PageType); + } + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_PORT, 2, + 0, &mpt->mpt_port_page2.Header); + if (rv) { + return (-1); + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "SPI Port Page 2 Header: %x %x %x %x", + mpt->mpt_port_page1.Header.PageVersion, + mpt->mpt_port_page1.Header.PageLength, + mpt->mpt_port_page1.Header.PageNumber, + mpt->mpt_port_page1.Header.PageType); + } + + for (i = 0; i < 16; i++) { + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_DEVICE, + 0, i, &mpt->mpt_dev_page0[i].Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Device Page 0 Header: %x %x %x %x", + i, mpt->mpt_dev_page0[i].Header.PageVersion, + mpt->mpt_dev_page0[i].Header.PageLength, + mpt->mpt_dev_page0[i].Header.PageNumber, + mpt->mpt_dev_page0[i].Header.PageType); + } + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_DEVICE, + 1, i, &mpt->mpt_dev_page1[i].Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Device Page 1 Header: %x %x %x %x", + i, mpt->mpt_dev_page1[i].Header.PageVersion, + mpt->mpt_dev_page1[i].Header.PageLength, + mpt->mpt_dev_page1[i].Header.PageNumber, + mpt->mpt_dev_page1[i].Header.PageType); + } + } + + /* + * At this point, we don't *have* to fail. As long as we have + * valid config header information, we can (barely) lurch + * along. + */ + + rv = mpt_read_cfg_page(mpt, 0, &mpt->mpt_port_page0.Header); + if (rv) { + mpt_prt(mpt, "failed to read SPI Port Page 0"); + } else if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Port Page 0: Capabilities %x PhysicalInterface %x", + mpt->mpt_port_page0.Capabilities, + mpt->mpt_port_page0.PhysicalInterface); + } + + rv = mpt_read_cfg_page(mpt, 0, &mpt->mpt_port_page1.Header); + if (rv) { + mpt_prt(mpt, "failed to read SPI Port Page 1"); + } else if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Port Page 1: Configuration %x OnBusTimerValue %x", + mpt->mpt_port_page1.Configuration, + mpt->mpt_port_page1.OnBusTimerValue); + } + + rv = mpt_read_cfg_page(mpt, 0, &mpt->mpt_port_page2.Header); + if (rv) { + mpt_prt(mpt, "failed to read SPI Port Page 2"); + } else if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Port Page 2: Flags %x Settings %x", + mpt->mpt_port_page2.PortFlags, + mpt->mpt_port_page2.PortSettings); + for (i = 0; i < 16; i++) { + mpt_prt(mpt, + "SPI Port Page 2 Tgt %d: timo %x SF %x Flags %x", + i, mpt->mpt_port_page2.DeviceSettings[i].Timeout, + mpt->mpt_port_page2.DeviceSettings[i].SyncFactor, + mpt->mpt_port_page2.DeviceSettings[i].DeviceFlags); + } + } + + for (i = 0; i < 16; i++) { + rv = mpt_read_cfg_page(mpt, i, &mpt->mpt_dev_page0[i].Header); + if (rv) { + mpt_prt(mpt, "cannot read SPI Tgt %d Device Page 0", i); + continue; + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 0: NParms %x Information %x", + i, mpt->mpt_dev_page0[i].NegotiatedParameters, + mpt->mpt_dev_page0[i].Information); + } + rv = mpt_read_cfg_page(mpt, i, &mpt->mpt_dev_page1[i].Header); + if (rv) { + mpt_prt(mpt, "cannot read SPI Tgt %d Device Page 1", i); + continue; + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 1: RParms %x Configuration %x", + i, mpt->mpt_dev_page1[i].RequestedParameters, + mpt->mpt_dev_page1[i].Configuration); + } + } + return (0); +} + +/* + * Validate SPI configuration information. + * + * In particular, validate SPI Port Page 1. + */ +static int +mpt_set_initial_config_spi(mpt_softc_t *mpt) +{ + int i, pp1val = ((1 << mpt->mpt_ini_id) << 16) | mpt->mpt_ini_id; + + mpt->mpt_disc_enable = 0xff; + mpt->mpt_tag_enable = 0; + + if (mpt->mpt_port_page1.Configuration != pp1val) { + fCONFIG_PAGE_SCSI_PORT_1 tmp; + mpt_prt(mpt, + "SPI Port Page 1 Config value bad (%x)- should be %x", + mpt->mpt_port_page1.Configuration, pp1val); + tmp = mpt->mpt_port_page1; + tmp.Configuration = pp1val; + if (mpt_write_cfg_page(mpt, 0, &tmp.Header)) { + return (-1); + } + if (mpt_read_cfg_page(mpt, 0, &tmp.Header)) { + return (-1); + } + if (tmp.Configuration != pp1val) { + mpt_prt(mpt, + "failed to reset SPI Port Page 1 Config value"); + return (-1); + } + mpt->mpt_port_page1 = tmp; + } + + for (i = 0; i < 16; i++) { + fCONFIG_PAGE_SCSI_DEVICE_1 tmp; + tmp = mpt->mpt_dev_page1[i]; + tmp.RequestedParameters = 0; + tmp.Configuration = 0; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "Set Tgt %d SPI DevicePage 1 values to %x 0 %x", + i, tmp.RequestedParameters, tmp.Configuration); + } + if (mpt_write_cfg_page(mpt, i, &tmp.Header)) { + return (-1); + } + if (mpt_read_cfg_page(mpt, i, &tmp.Header)) { + return (-1); + } + mpt->mpt_dev_page1[i] = tmp; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 1: RParm %x Configuration %x", i, + mpt->mpt_dev_page1[i].RequestedParameters, + mpt->mpt_dev_page1[i].Configuration); + } + } + return (0); +} + +/* + * Enable IOC port + */ +static int +mpt_send_port_enable(mpt_softc_t *mpt, int port) +{ + int count; + request_t *req; + MSG_PORT_ENABLE *enable_req; + + req = mpt_get_request(mpt); + + enable_req = req->req_vbuf; + bzero(enable_req, sizeof *enable_req); + + enable_req->Function = MPI_FUNCTION_PORT_ENABLE; + enable_req->MsgContext = req->index | 0x80000000; + enable_req->PortNumber = port; + + mpt_check_doorbell(mpt); + if (mpt->verbose > 1) { + mpt_prt(mpt, "enabling port %d", port); + } + mpt_send_cmd(mpt, req); + + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 100000) { + mpt_prt(mpt, "port enable timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + mpt_free_request(mpt, req); + return (0); +} + +/* + * Enable/Disable asynchronous event reporting. + * + * NB: this is the first command we send via shared memory + * instead of the handshake register. + */ +static int +mpt_send_event_request(mpt_softc_t *mpt, int onoff) +{ + request_t *req; + MSG_EVENT_NOTIFY *enable_req; + + req = mpt_get_request(mpt); + + enable_req = req->req_vbuf; + bzero(enable_req, sizeof *enable_req); + + enable_req->Function = MPI_FUNCTION_EVENT_NOTIFICATION; + enable_req->MsgContext = req->index | 0x80000000; + enable_req->Switch = onoff; + + mpt_check_doorbell(mpt); + if (mpt->verbose > 1) { + mpt_prt(mpt, "%sabling async events", onoff? "en" : "dis"); + } + mpt_send_cmd(mpt, req); + + return (0); +} + +/* + * Un-mask the interrupts on the chip. + */ +void +mpt_enable_ints(mpt_softc_t *mpt) +{ + /* Unmask every thing except door bell int */ + mpt_write(mpt, MPT_OFFSET_INTR_MASK, MPT_INTR_DB_MASK); +} + +/* + * Mask the interrupts on the chip. + */ +void +mpt_disable_ints(mpt_softc_t *mpt) +{ + /* Mask all interrupts */ + mpt_write(mpt, MPT_OFFSET_INTR_MASK, + MPT_INTR_REPLY_MASK | MPT_INTR_DB_MASK); +} + +/* (Re)Initialize the chip for use */ +int +mpt_init(mpt_softc_t *mpt, u_int32_t who) +{ + int try; + MSG_IOC_FACTS_REPLY facts; + MSG_PORT_FACTS_REPLY pfp; + u_int32_t pptr; + int val; + + /* Put all request buffers (back) on the free list */ + SLIST_INIT(&mpt->request_free_list); + for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { + mpt_init_request(mpt, &mpt->request_pool[val]); + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "doorbell req = %s", + mpt_ioc_diag(mpt_read(mpt, MPT_OFFSET_DOORBELL))); + } + + /* + * Start by making sure we're not at FAULT or RESET state + */ + switch (mpt_rd_db(mpt) & MPT_DB_STATE_MASK) { + case MPT_DB_STATE_RESET: + case MPT_DB_STATE_FAULT: + if (mpt_reset(mpt) != MPT_OK) { + return (EIO); + } + default: + break; + } + + for (try = 0; try < MPT_MAX_TRYS; try++) { + /* + * No need to reset if the IOC is already in the READY state. + * + * Force reset if initialization failed previously. + * Note that a hard_reset of the second channel of a '929 + * will stop operation of the first channel. Hopefully, if the + * first channel is ok, the second will not require a hard + * reset. + */ + if ((mpt_rd_db(mpt) & MPT_DB_STATE_MASK) != + MPT_DB_STATE_READY) { + if (mpt_reset(mpt) != MPT_OK) { + DELAY(10000); + continue; + } + } + + if (mpt_get_iocfacts(mpt, &facts) != MPT_OK) { + mpt_prt(mpt, "mpt_get_iocfacts failed"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, + "IOCFACTS: GlobalCredits=%d BlockSize=%u " + "Request Frame Size %u\n", facts.GlobalCredits, + facts.BlockSize, facts.RequestFrameSize); + } + mpt->mpt_global_credits = facts.GlobalCredits; + mpt->request_frame_size = facts.RequestFrameSize; + + if (mpt_get_portfacts(mpt, &pfp) != MPT_OK) { + mpt_prt(mpt, "mpt_get_portfacts failed"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, + "PORTFACTS: Type %x PFlags %x IID %d MaxDev %d\n", + pfp.PortType, pfp.ProtocolFlags, pfp.PortSCSIID, + pfp.MaxDevices); + } + + if (pfp.PortType != MPI_PORTFACTS_PORTTYPE_SCSI && + pfp.PortType != MPI_PORTFACTS_PORTTYPE_FC) { + mpt_prt(mpt, "Unsupported Port Type (%x)", + pfp.PortType); + return (ENXIO); + } + if (!(pfp.ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR)) { + mpt_prt(mpt, "initiator role unsupported"); + return (ENXIO); + } + if (pfp.PortType == MPI_PORTFACTS_PORTTYPE_FC) { + mpt->is_fc = 1; + } else { + mpt->is_fc = 0; + } + mpt->mpt_ini_id = pfp.PortSCSIID; + + if (mpt_send_ioc_init(mpt, who) != MPT_OK) { + mpt_prt(mpt, "mpt_send_ioc_init failed"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "mpt_send_ioc_init ok"); + } + + if (mpt_wait_state(mpt, MPT_DB_STATE_RUNNING) != MPT_OK) { + mpt_prt(mpt, "IOC failed to go to run state"); + continue; + } + if (mpt->verbose > 1) { + mpt_prt(mpt, "IOC now at RUNSTATE"); + } + + /* + * Give it reply buffers + * + * Do *not* except global credits. + */ + for (val = 0, pptr = mpt->reply_phys; + (pptr + MPT_REPLY_SIZE) < (mpt->reply_phys + PAGE_SIZE); + pptr += MPT_REPLY_SIZE) { + mpt_free_reply(mpt, pptr); + if (++val == mpt->mpt_global_credits - 1) + break; + } + + /* + * Enable asynchronous event reporting + */ + mpt_send_event_request(mpt, 1); + + + /* + * Read set up initial configuration information + * (SPI only for now) + */ + + if (mpt->is_fc == 0) { + if (mpt_read_config_info_spi(mpt)) { + return (EIO); + } + if (mpt_set_initial_config_spi(mpt)) { + return (EIO); + } + } + + /* + * Now enable the port + */ + if (mpt_send_port_enable(mpt, 0) != MPT_OK) { + mpt_prt(mpt, "failed to enable port 0"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "enabled port 0"); + } + + /* Everything worked */ + break; + } + + if (try >= MPT_MAX_TRYS) { + mpt_prt(mpt, "failed to initialize IOC"); + return (EIO); + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "enabling interrupts"); + } + + mpt_enable_ints(mpt); + return (0); +} diff --git a/sys/dev/ic/mpt.c.orig b/sys/dev/ic/mpt.c.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/ic/mpt.c.orig diff --git a/sys/dev/ic/mpt.h b/sys/dev/ic/mpt.h new file mode 100644 index 00000000000..89c629800c5 --- /dev/null +++ b/sys/dev/ic/mpt.h @@ -0,0 +1,191 @@ +/* $OpenBSD: mpt.h,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt.h,v 1.2 2003/07/08 10:06:31 itojun Exp $ */ + +/* + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +/* + * mpt.h: + * + * Generic definitions for LSI Fusion adapters. + * + * Adapted from the FreeBSD "mpt" driver by Jason R. Thorpe for + * Wasabi Systems, Inc. + */ + +#ifndef _DEV_IC_MPT_H_ +#define _DEV_IC_MPT_H_ + +#include <dev/ic/mpt_openbsd.h> + +#define MPT_OK (0) +#define MPT_FAIL (0x10000) + +/* Register Offset to chip registers */ +#define MPT_OFFSET_DOORBELL 0x00 +#define MPT_OFFSET_SEQUENCE 0x04 +#define MPT_OFFSET_DIAGNOSTIC 0x08 +#define MPT_OFFSET_TEST 0x0C +#define MPT_OFFSET_INTR_STATUS 0x30 +#define MPT_OFFSET_INTR_MASK 0x34 +#define MPT_OFFSET_REQUEST_Q 0x40 +#define MPT_OFFSET_REPLY_Q 0x44 +#define MPT_OFFSET_HOST_INDEX 0x50 +#define MPT_OFFSET_FUBAR 0x90 + +#define MPT_DIAG_SEQUENCE_1 0x04 +#define MPT_DIAG_SEQUENCE_2 0x0b +#define MPT_DIAG_SEQUENCE_3 0x02 +#define MPT_DIAG_SEQUENCE_4 0x07 +#define MPT_DIAG_SEQUENCE_5 0x0d + +/* Bit Maps for DOORBELL register */ +enum DB_STATE_BITS { + MPT_DB_STATE_RESET = 0x00000000, + MPT_DB_STATE_READY = 0x10000000, + MPT_DB_STATE_RUNNING = 0x20000000, + MPT_DB_STATE_FAULT = 0x40000000, + MPT_DB_STATE_MASK = 0xf0000000 +}; + +#define MPT_STATE(v) ((enum DB_STATE_BITS)((v) & MPT_DB_STATE_MASK)) + +#define MPT_DB_LENGTH_SHIFT (16) +#define MPT_DB_DATA_MASK (0xffff) + +#define MPT_DB_DB_USED 0x08000000 +#define MPT_DB_IS_IN_USE(v) (((v) & MPT_DB_DB_USED) != 0) + +/* + * "Whom" initializor values + */ +#define MPT_DB_INIT_NOONE 0x00 +#define MPT_DB_INIT_BIOS 0x01 +#define MPT_DB_INIT_ROMBIOS 0x02 +#define MPT_DB_INIT_PCIPEER 0x03 +#define MPT_DB_INIT_HOST 0x04 +#define MPT_DB_INIT_MANUFACTURE 0x05 + +#define MPT_WHO(v) \ + ((v & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT) + +/* Function Maps for DOORBELL register */ +enum DB_FUNCTION_BITS { + MPT_FUNC_IOC_RESET = 0x40000000, + MPT_FUNC_UNIT_RESET = 0x41000000, + MPT_FUNC_HANDSHAKE = 0x42000000, + MPT_FUNC_REPLY_REMOVE = 0x43000000, + MPT_FUNC_MASK = 0xff000000 +}; + +/* Function Maps for INTERRUPT request register */ +enum _MPT_INTR_REQ_BITS { + MPT_INTR_DB_BUSY = 0x80000000, + MPT_INTR_REPLY_READY = 0x00000008, + MPT_INTR_DB_READY = 0x00000001 +}; + +#define MPT_DB_IS_BUSY(v) (((v) & MPT_INTR_DB_BUSY) != 0) +#define MPT_DB_INTR(v) (((v) & MPT_INTR_DB_READY) != 0) +#define MPT_REPLY_INTR(v) (((v) & MPT_INTR_REPLY_READY) != 0) + +/* Function Maps for INTERRUPT make register */ +enum _MPT_INTR_MASK_BITS { + MPT_INTR_REPLY_MASK = 0x00000008, + MPT_INTR_DB_MASK = 0x00000001 +}; + +/* Function Maps for DIAGNOSTIC make register */ +enum _MPT_DIAG_BITS { + MPT_DIAG_ENABLED = 0x00000080, + MPT_DIAG_FLASHBAD = 0x00000040, + MPT_DIAG_RESET_HIST = 0x00000020, + MPT_DIAG_TTLI = 0x00000008, + MPT_DIAG_RESET_IOC = 0x00000004, + MPT_DIAG_ARM_DISABLE = 0x00000002, + MPT_DIAG_DME = 0x00000001 +}; + +/* Magic addresses in diagnostic memory space */ +#define MPT_DIAG_IOP_BASE (0x00000000) +#define MPT_DIAG_IOP_SIZE (0x00002000) +#define MPT_DIAG_GPIO (0x00030010) +#define MPT_DIAG_IOPQ_REG_BASE0 (0x00050004) +#define MPT_DIAG_IOPQ_REG_BASE1 (0x00051004) +#define MPT_DIAG_MEM_CFG_BASE (0x00040000) +#define MPT_DIAG_CTX0_BASE (0x000E0000) +#define MPT_DIAG_CTX0_SIZE (0x00002000) +#define MPT_DIAG_CTX1_BASE (0x001E0000) +#define MPT_DIAG_CTX1_SIZE (0x00002000) +#define MPT_DIAG_FLASH_BASE (0x00800000) +#define MPT_DIAG_RAM_BASE (0x01000000) +#define MPT_DIAG_RAM_SIZE (0x00400000) + +/* GPIO bit assignments */ +#define MPT_DIAG_GPIO_SCL (0x00010000) +#define MPT_DIAG_GPIO_SDA_OUT (0x00008000) +#define MPT_DIAG_GPIO_SDA_IN (0x00004000) + +#define MPT_REPLY_EMPTY (0xffffffff) /* Reply Queue Empty Symbol */ +#define MPT_CONTEXT_REPLY (0x80000000) +#define MPT_CONTEXT_MASK (~0xE0000000) + +#ifdef _KERNEL +int mpt_soft_reset(mpt_softc_t *); +void mpt_hard_reset(mpt_softc_t *); +int mpt_recv_handshake_reply(mpt_softc_t *, size_t, void *); + +void mpt_send_cmd(mpt_softc_t *, request_t *); +void mpt_free_reply(mpt_softc_t *, u_int32_t); +void mpt_enable_ints(mpt_softc_t *); +void mpt_disable_ints(mpt_softc_t *); +u_int32_t mpt_pop_reply_queue(mpt_softc_t *); +int mpt_init(mpt_softc_t *, u_int32_t); +int mpt_reset(mpt_softc_t *); +int mpt_send_handshake_cmd(mpt_softc_t *, size_t, void *); +request_t * mpt_get_request(mpt_softc_t *); +void mpt_free_request(mpt_softc_t *, request_t *); +void mpt_init_request(mpt_softc_t *, request_t *); +int mpt_intr(void *); +void mpt_check_doorbell(mpt_softc_t *); + +int mpt_read_cfg_page(mpt_softc_t *, int, fCONFIG_PAGE_HEADER *); +int mpt_write_cfg_page(mpt_softc_t *, int, fCONFIG_PAGE_HEADER *); + +/* mpt_debug.c functions */ +void mpt_print_reply(void *); +void mpt_print_db(u_int32_t); +void mpt_print_config_reply(void *); +char *mpt_ioc_diag(u_int32_t); +char *mpt_req_state(enum mpt_req_state); +void mpt_print_scsi_io_request(MSG_SCSI_IO_REQUEST *); +void mpt_print_config_request(void *); +void mpt_print_request(void *); +#endif /* _KERNEL */ + +#endif /* _DEV_IC_MPT_H_ */ diff --git a/sys/dev/ic/mpt.h.orig b/sys/dev/ic/mpt.h.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/ic/mpt.h.orig diff --git a/sys/dev/ic/mpt_debug.c b/sys/dev/ic/mpt_debug.c new file mode 100644 index 00000000000..644c82f2924 --- /dev/null +++ b/sys/dev/ic/mpt_debug.c @@ -0,0 +1,608 @@ +/* $OpenBSD: mpt_debug.c,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt_debug.c,v 1.2 2003/07/14 15:47:11 lukem Exp $ */ + +/* + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +/* + * mpt_debug.c: + * + * Debug routines for LSI Fusion adapters. + */ + +#include <sys/cdefs.h> +/* __KERNEL_RCSID(0, "$NetBSD: mpt_debug.c,v 1.2 2003/07/14 15:47:11 lukem Exp $"); */ + +#include <dev/ic/mpt.h> + +struct Error_Map { + int Error_Code; + char *Error_String; +}; + +static const struct Error_Map IOC_Status[] = { +{ MPI_IOCSTATUS_SUCCESS, "Success" }, +{ MPI_IOCSTATUS_INVALID_FUNCTION, "IOC: Invalid Function" }, +{ MPI_IOCSTATUS_BUSY, "IOC: Busy" }, +{ MPI_IOCSTATUS_INVALID_SGL, "IOC: Invalid SGL" }, +{ MPI_IOCSTATUS_INTERNAL_ERROR, "IOC: Internal Error" }, +{ MPI_IOCSTATUS_RESERVED, "IOC: Reserved" }, +{ MPI_IOCSTATUS_INSUFFICIENT_RESOURCES, "IOC: Insufficient Resources" }, +{ MPI_IOCSTATUS_INVALID_FIELD, "IOC: Invalid Field" }, +{ MPI_IOCSTATUS_INVALID_STATE, "IOC: Invalid State" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_ACTION, "Invalid Action" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_TYPE, "Invalid Type" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_PAGE, "Invalid Page" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_DATA, "Invalid Data" }, +{ MPI_IOCSTATUS_CONFIG_NO_DEFAULTS, "No Defaults" }, +{ MPI_IOCSTATUS_CONFIG_CANT_COMMIT, "Can't Commit" }, +{ MPI_IOCSTATUS_SCSI_RECOVERED_ERROR, "SCSI: Recoverd Error" }, +{ MPI_IOCSTATUS_SCSI_INVALID_BUS, "SCSI: Invalid Bus" }, +{ MPI_IOCSTATUS_SCSI_INVALID_TARGETID, "SCSI: Invalid Target ID" }, +{ MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE, "SCSI: Device Not There" }, +{ MPI_IOCSTATUS_SCSI_DATA_OVERRUN, "SCSI: Data Overrun" }, +{ MPI_IOCSTATUS_SCSI_DATA_UNDERRUN, "SCSI: Data Underrun" }, +{ MPI_IOCSTATUS_SCSI_IO_DATA_ERROR, "SCSI: Data Error" }, +{ MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR, "SCSI: Protocol Error" }, +{ MPI_IOCSTATUS_SCSI_TASK_TERMINATED, "SCSI: Task Terminated" }, +{ MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH, "SCSI: Residual Mismatch" }, +{ MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED, "SCSI: Task Management Failed" }, +{ MPI_IOCSTATUS_SCSI_IOC_TERMINATED, "SCSI: IOC Bus Reset" }, +{ MPI_IOCSTATUS_SCSI_EXT_TERMINATED, "SCSI: External Bus Reset" }, +{ MPI_IOCSTATUS_TARGET_PRIORITY_IO, "SCSI Target: Priority I/O" }, +{ MPI_IOCSTATUS_TARGET_INVALID_PORT, "SCSI Target: Invalid Port" }, +{ MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX, "SCSI Target: Invalid IOC Index" }, +{ MPI_IOCSTATUS_TARGET_ABORTED, "SCSI Target: Aborted" }, +{ MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE, "SCSI Target: No Connection (Retryable)" }, +{ MPI_IOCSTATUS_TARGET_NO_CONNECTION, "SCSI Target: No Connection" }, +{ MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH,"SCSI Target: Transfer Count Mismatch" }, +{ MPI_IOCSTATUS_TARGET_FC_ABORTED, "FC: Aborted" }, +{ MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID, "FC: Recieve ID Invalid" }, +{ MPI_IOCSTATUS_TARGET_FC_DID_INVALID, "FC: Recieve DID Invalid" }, +{ MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT,"FC: Node Logged Out" }, +{ MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND, "LAN: Device Not Found" }, +{ MPI_IOCSTATUS_LAN_DEVICE_FAILURE, "LAN: Device Not Failure" }, +{ MPI_IOCSTATUS_LAN_TRANSMIT_ERROR, "LAN: Transmit Error" }, +{ MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED, "LAN: Transmit Aborted" }, +{ MPI_IOCSTATUS_LAN_RECEIVE_ERROR, "LAN: Recieve Error" }, +{ MPI_IOCSTATUS_LAN_RECEIVE_ABORTED, "LAN: Recieve Aborted" }, +{ MPI_IOCSTATUS_LAN_PARTIAL_PACKET, "LAN: Partial Packet" }, +{ MPI_IOCSTATUS_LAN_CANCELED, "LAN: Canceled" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_Func[] = { +{ MPI_FUNCTION_SCSI_IO_REQUEST, "SCSI IO Request" }, +{ MPI_FUNCTION_SCSI_TASK_MGMT, "SCSI Task Management" }, +{ MPI_FUNCTION_IOC_INIT, "IOC Init" }, +{ MPI_FUNCTION_IOC_FACTS, "IOC Facts" }, +{ MPI_FUNCTION_CONFIG, "Config" }, +{ MPI_FUNCTION_PORT_FACTS, "Port Facts" }, +{ MPI_FUNCTION_PORT_ENABLE, "Port Enable" }, +{ MPI_FUNCTION_EVENT_NOTIFICATION, "Event Notification" }, +{ MPI_FUNCTION_FW_DOWNLOAD, "FW Download" }, +{ MPI_FUNCTION_TARGET_CMD_BUFFER_POST, "SCSI Target Command Buffer" }, +{ MPI_FUNCTION_TARGET_ASSIST, "Target Assist" }, +{ MPI_FUNCTION_TARGET_STATUS_SEND, "Target Status Send" }, +{ MPI_FUNCTION_TARGET_MODE_ABORT, "Target Mode Abort" }, +{ MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC, "FC: Link Service Buffers" }, +{ MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC, "FC: Link Service Response" }, +{ MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC, "FC: Send Extended Link Service" }, +{ MPI_FUNCTION_TARGET_FC_ABORT, "FC: Abort" }, +{ MPI_FUNCTION_LAN_SEND, "LAN Send" }, +{ MPI_FUNCTION_LAN_RECEIVE, "LAN Recieve" }, +{ MPI_FUNCTION_LAN_RESET, "LAN Reset" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_Event[] = { +{ MPI_EVENT_NONE, "None" }, +{ MPI_EVENT_LOG_DATA, "LogData" }, +{ MPI_EVENT_STATE_CHANGE, "State Change" }, +{ MPI_EVENT_UNIT_ATTENTION, "Unit Attention" }, +{ MPI_EVENT_IOC_BUS_RESET, "IOC Bus Reset" }, +{ MPI_EVENT_EXT_BUS_RESET, "External Bus Reset" }, +{ MPI_EVENT_RESCAN, "Rescan" }, +{ MPI_EVENT_LINK_STATUS_CHANGE, "Link Status Change" }, +{ MPI_EVENT_LOOP_STATE_CHANGE, "Loop State Change" }, +{ MPI_EVENT_LOGOUT, "Logout" }, +{ MPI_EVENT_EVENT_CHANGE, "EventChange" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_SCSIState[] = { +{ MPI_SCSI_STATE_AUTOSENSE_VALID, "AutoSense_Valid" }, +{ MPI_SCSI_STATE_AUTOSENSE_FAILED, "AutoSense_Failed" }, +{ MPI_SCSI_STATE_NO_SCSI_STATUS, "No_SCSI_Status" }, +{ MPI_SCSI_STATE_TERMINATED, "State_Terminated" }, +{ MPI_SCSI_STATE_RESPONSE_INFO_VALID, "Repsonse_Info_Valid" }, +{ MPI_SCSI_STATE_QUEUE_TAG_REJECTED, "Queue Tag Rejected" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_SCSIStatus[] = { +{ SCSI_OK, "OK" }, +{ SCSI_CHECK, "Check Condition" }, +#if 0 +{ SCSI_STATUS_COND_MET, "Check Condition Met" }, +#endif +{ SCSI_BUSY, "Busy" }, +{ SCSI_INTERM, "Intermidiate Condition" }, +#if 0 +{ SCSI_STATUS_INTERMED_COND_MET, "Intermidiate Condition Met" }, +#endif +{ SCSI_RESV_CONFLICT, "Reservation Conflict" }, +#if 0 +{ SCSI_STATUS_CMD_TERMINATED, "Command Terminated" }, +#endif +{ SCSI_QUEUE_FULL, "Queue Full" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_Diag[] = { +{ MPT_DIAG_ENABLED, "DWE" }, +{ MPT_DIAG_FLASHBAD, "FLASH_Bad" }, +{ MPT_DIAG_TTLI, "TTLI" }, +{ MPT_DIAG_RESET_IOC, "Reset" }, +{ MPT_DIAG_ARM_DISABLE, "DisARM" }, +{ MPT_DIAG_DME, "DME" }, +{ -1, 0 }, +}; + + +static void mpt_dump_sgl(SGE_IO_UNION *sgl); + +static char * +mpt_ioc_status(int code) +{ + const struct Error_Map *status = IOC_Status; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == (code & MPI_IOCSTATUS_MASK)) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} + +char * +mpt_ioc_diag(u_int32_t code) +{ + const struct Error_Map *status = IOC_Diag; + static char buf[128]; + char *ptr = buf; + char *end = &buf[128]; + buf[0] = '\0'; + ptr += snprintf(buf, sizeof buf, "(0x%08x)", code); + while (status->Error_Code >= 0) { + if ((status->Error_Code & code) != 0) + ptr += snprintf(ptr, (size_t)(end-ptr), "%s ", + status->Error_String); + status++; + } + return buf; +} + +static char * +mpt_ioc_function(int code) +{ + const struct Error_Map *status = IOC_Func; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == code) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} +static char * +mpt_ioc_event(int code) +{ + const struct Error_Map *status = IOC_Event; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == code) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} +static char * +mpt_scsi_state(int code) +{ + const struct Error_Map *status = IOC_SCSIState; + static char buf[128]; + char *ptr = buf; + char *end = &buf[128]; + buf[0] = '\0'; + ptr += snprintf(buf, sizeof buf, "(0x%08x)", code); + while (status->Error_Code >= 0) { + if ((status->Error_Code & code) != 0) + ptr += snprintf(ptr, (size_t)(end-ptr), "%s ", + status->Error_String); + status++; + } + return buf; +} +static char * +mpt_scsi_status(int code) +{ + const struct Error_Map *status = IOC_SCSIStatus; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == code) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} +static char * +mpt_who(int who_init) +{ + char *who; + + switch (who_init) { + case MPT_DB_INIT_NOONE: who = "No One"; break; + case MPT_DB_INIT_BIOS: who = "BIOS"; break; + case MPT_DB_INIT_ROMBIOS: who = "ROM BIOS"; break; + case MPT_DB_INIT_PCIPEER: who = "PCI Peer"; break; + case MPT_DB_INIT_HOST: who = "Host Driver"; break; + case MPT_DB_INIT_MANUFACTURE: who = "Manufacturing"; break; + default: who = "Unknown"; break; + } + return who; +} + +static char * +mpt_state(u_int32_t mb) +{ + char *text; + + switch (MPT_STATE(mb)) { + case MPT_DB_STATE_RESET: text = "Reset"; break; + case MPT_DB_STATE_READY: text = "Ready"; break; + case MPT_DB_STATE_RUNNING:text = "Running"; break; + case MPT_DB_STATE_FAULT: text = "Fault"; break; + default: text = "Unknown"; break; + } + return text; +}; + +void +mpt_print_db(u_int32_t mb) +{ + printf("mpt mailbox: (0x%x) State %s WhoInit %s\n", + mb, mpt_state(mb), mpt_who(MPT_WHO(mb))); +} + +/*****************************************************************************/ +/* Reply functions */ +/*****************************************************************************/ +static void +mpt_print_reply_hdr(MSG_DEFAULT_REPLY *msg) +{ + printf("%s Reply @ %p\n", mpt_ioc_function(msg->Function), msg); + printf("\tIOC Status %s\n", mpt_ioc_status(msg->IOCStatus)); + printf("\tIOCLogInfo 0x%08x\n", msg->IOCLogInfo); + printf("\tMsgLength 0x%02x\n", msg->MsgLength); + printf("\tMsgFlags 0x%02x\n", msg->MsgFlags); + printf("\tMsgContext 0x%08x\n", msg->MsgContext); +} + +static void +mpt_print_init_reply(MSG_IOC_INIT_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tWhoInit %s\n", mpt_who(msg->WhoInit)); + printf("\tMaxDevices 0x%02x\n", msg->MaxDevices); + printf("\tMaxBuses 0x%02x\n", msg->MaxBuses); +} + +static void +mpt_print_ioc_facts(MSG_IOC_FACTS_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tIOCNumber %d\n", msg->IOCNumber); + printf("\tMaxChainDepth %d\n", msg->MaxChainDepth); + printf("\tWhoInit %s\n", mpt_who(msg->WhoInit)); + printf("\tBlockSize %d\n", msg->BlockSize); + printf("\tFlags %d\n", msg->Flags); + printf("\tReplyQueueDepth %d\n", msg->ReplyQueueDepth); + printf("\tReqFrameSize 0x%04x\n", msg->RequestFrameSize); + printf("\tFW Version 0x%08x\n", msg->FWVersion.Word); + printf("\tProduct ID 0x%04x\n", msg->ProductID); + printf("\tCredits 0x%04x\n", msg->GlobalCredits); + printf("\tPorts %d\n", msg->NumberOfPorts); + printf("\tEventState 0x%02x\n", msg->EventState); + printf("\tHostMFA_HA 0x%08x\n", msg->CurrentHostMfaHighAddr); + printf("\tSenseBuf_HA 0x%08x\n", + msg->CurrentSenseBufferHighAddr); + printf("\tRepFrameSize 0x%04x\n", msg->CurReplyFrameSize); + printf("\tMaxDevices 0x%02x\n", msg->MaxDevices); + printf("\tMaxBuses 0x%02x\n", msg->MaxBuses); + printf("\tFWImageSize 0x%04x\n", msg->FWImageSize); +} + +static void +mpt_print_enable_reply(MSG_PORT_ENABLE_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tPort: %d\n", msg->PortNumber); +} + +static void +mpt_print_scsi_io_reply(MSG_SCSI_IO_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tBus: %d\n", msg->Bus); + printf("\tTargetID %d\n", msg->TargetID); + printf("\tCDBLength %d\n", msg->CDBLength); + printf("\tSCSI Status: %s\n", mpt_scsi_status(msg->SCSIStatus)); + printf("\tSCSI State: %s\n", mpt_scsi_state(msg->SCSIState)); + printf("\tTransferCnt 0x%04x\n", msg->TransferCount); + printf("\tSenseCnt 0x%04x\n", msg->SenseCount); + printf("\tResponseInfo 0x%08x\n", msg->ResponseInfo); +} + + + +static void +mpt_print_event_notice(MSG_EVENT_NOTIFY_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tEvent: %s\n", mpt_ioc_event(msg->Event)); + printf("\tEventContext 0x%04x\n", msg->EventContext); + printf("\tAckRequired %d\n", msg->AckRequired); + printf("\tEventDataLength %d\n", msg->EventDataLength); + printf("\tContinuation %d\n", msg->MsgFlags & 0x80); + switch(msg->Event) { + case MPI_EVENT_LOG_DATA: + printf("\tEvtLogData: 0x%04x\n", msg->Data[0]); + break; + + case MPI_EVENT_UNIT_ATTENTION: + printf("\tTargetID: 0x%04x\n", + msg->Data[0] & 0xff); + printf("\tBus: 0x%04x\n", + (msg->Data[0] >> 8) & 0xff); + break; + + case MPI_EVENT_IOC_BUS_RESET: + case MPI_EVENT_EXT_BUS_RESET: + case MPI_EVENT_RESCAN: + printf("\tPort: %d\n", + (msg->Data[0] >> 8) & 0xff); + break; + + case MPI_EVENT_LINK_STATUS_CHANGE: + printf("\tLinkState: %d\n", + msg->Data[0] & 0xff); + printf("\tPort: %d\n", + (msg->Data[1] >> 8) & 0xff); + break; + + case MPI_EVENT_LOOP_STATE_CHANGE: + printf("\tType: %d\n", + (msg->Data[0] >> 16) & 0xff); + printf("\tChar3: 0x%02x\n", + (msg->Data[0] >> 8) & 0xff); + printf("\tChar4: 0x%02x\n", + (msg->Data[0] ) & 0xff); + printf("\tPort: %d\n", + (msg->Data[1] >> 8) & 0xff); + break; + + case MPI_EVENT_LOGOUT: + printf("\tN_PortId: 0x%04x\n", msg->Data[0]); + printf("\tPort: %d\n", + (msg->Data[1] >> 8) & 0xff); + break; + } + +} + +void +mpt_print_reply(void *vmsg) +{ + MSG_DEFAULT_REPLY *msg = vmsg; + + switch (msg->Function) { + case MPI_FUNCTION_EVENT_NOTIFICATION: + mpt_print_event_notice((MSG_EVENT_NOTIFY_REPLY *)msg); + break; + case MPI_FUNCTION_PORT_ENABLE: + mpt_print_enable_reply((MSG_PORT_ENABLE_REPLY *)msg); + break; + case MPI_FUNCTION_IOC_FACTS: + mpt_print_ioc_facts((MSG_IOC_FACTS_REPLY *)msg); + break; + case MPI_FUNCTION_IOC_INIT: + mpt_print_init_reply((MSG_IOC_INIT_REPLY *)msg); + break; + case MPI_FUNCTION_SCSI_IO_REQUEST: + mpt_print_scsi_io_reply((MSG_SCSI_IO_REPLY *)msg); + break; + default: + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + break; + } +} + +/*****************************************************************************/ +/* Request functions */ +/*****************************************************************************/ +static void +mpt_print_request_hdr(MSG_REQUEST_HEADER *req) +{ + printf("%s @ %p\n", mpt_ioc_function(req->Function), req); + printf("\tChain Offset 0x%02x\n", req->ChainOffset); + printf("\tMsgFlags 0x%02x\n", req->MsgFlags); + printf("\tMsgContext 0x%08x\n", req->MsgContext); +} + +void +mpt_print_scsi_io_request(MSG_SCSI_IO_REQUEST *orig_msg) +{ + MSG_SCSI_IO_REQUEST local, *msg = &local; + int i; + + bcopy(orig_msg, msg, sizeof (MSG_SCSI_IO_REQUEST)); + mpt_print_request_hdr((MSG_REQUEST_HEADER *)msg); + printf("\tBus: %d\n", msg->Bus); + printf("\tTargetID %d\n", msg->TargetID); + printf("\tSenseBufferLength %d\n", msg->SenseBufferLength); + printf("\tLUN: 0x%0x\n", msg->LUN[1]); + printf("\tControl 0x%08x ", msg->Control); +#define MPI_PRINT_FIELD(x) \ + case MPI_SCSIIO_CONTROL_ ## x : \ + printf(" " #x " "); \ + break + + switch (msg->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { + MPI_PRINT_FIELD(NODATATRANSFER); + MPI_PRINT_FIELD(WRITE); + MPI_PRINT_FIELD(READ); + default: + printf(" Invalid DIR! "); + break; + } + switch (msg->Control & MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK) { + MPI_PRINT_FIELD(SIMPLEQ); + MPI_PRINT_FIELD(HEADOFQ); + MPI_PRINT_FIELD(ORDEREDQ); + MPI_PRINT_FIELD(ACAQ); + MPI_PRINT_FIELD(UNTAGGED); + MPI_PRINT_FIELD(NO_DISCONNECT); + default: + printf(" Unknown attribute! "); + break; + } + + printf("\n"); +#undef MPI_PRINT_FIELD + + printf("\tDataLength\t0x%08x\n", msg->DataLength); + printf("\tSenseBufAddr\t0x%08x\n", msg->SenseBufferLowAddr); + printf("\tCDB[0:%d]\t", msg->CDBLength); + for (i = 0; i < msg->CDBLength; i++) + printf("%02x ", msg->CDB[i]); + printf("\n"); + mpt_dump_sgl(&orig_msg->SGL); +} + +void +mpt_print_request(void *vreq) +{ + MSG_REQUEST_HEADER *req = vreq; + + switch (req->Function) { + case MPI_FUNCTION_SCSI_IO_REQUEST: + mpt_print_scsi_io_request((MSG_SCSI_IO_REQUEST *)req); + break; + default: + mpt_print_request_hdr(req); + break; + } +} + +char * +mpt_req_state(enum mpt_req_state state) +{ + char *text; + + switch (state) { + case REQ_FREE: text = "Free"; break; + case REQ_IN_PROGRESS: text = "In Progress"; break; + case REQ_ON_CHIP: text = "On Chip"; break; + case REQ_TIMEOUT: text = "Timeout"; break; + default: text = "Unknown"; break; + } + return text; +}; + +static void +mpt_dump_sgl(SGE_IO_UNION *su) +{ + SGE_SIMPLE32 *se = (SGE_SIMPLE32 *) su; + int iCount, flags; + + iCount = MPT_SGL_MAX; + do { + int iprt; + + printf("\t"); + flags = MPI_SGE_GET_FLAGS(se->FlagsLength); + switch (flags & MPI_SGE_FLAGS_ELEMENT_MASK) { + case MPI_SGE_FLAGS_SIMPLE_ELEMENT: + { + printf("SE32 %p: Addr=0x%0x FlagsLength=0x%0x\n", + se, se->Address, se->FlagsLength); + printf(" "); + break; + } + case MPI_SGE_FLAGS_CHAIN_ELEMENT: + { + SGE_CHAIN32 *ce = (SGE_CHAIN32 *) se; + printf("CE32 %p: Addr=0x%0x NxtChnO=0x%x Flgs=0x%x " + "Len=0x%0x\n", ce, ce->Address, ce->NextChainOffset, + ce->Flags, ce->Length); + flags = 0; + break; + } + case MPI_SGE_FLAGS_TRANSACTION_ELEMENT: + printf("TE32 @ %p\n", se); + flags = 0; + break; + } + iprt = 0; +#define MPT_PRINT_FLAG(x) \ + if (flags & MPI_SGE_FLAGS_ ## x ) { \ + if (iprt == 0) { \ + printf("\t"); \ + } \ + printf(" "); \ + printf( #x ); \ + iprt++; \ + } + MPT_PRINT_FLAG(LOCAL_ADDRESS); + MPT_PRINT_FLAG(HOST_TO_IOC); + MPT_PRINT_FLAG(64_BIT_ADDRESSING); + MPT_PRINT_FLAG(LAST_ELEMENT); + MPT_PRINT_FLAG(END_OF_BUFFER); + MPT_PRINT_FLAG(END_OF_LIST); +#undef MPT_PRINT_FLAG + if (iprt) + printf("\n"); + se++; + iCount -= 1; + } while ((flags & MPI_SGE_FLAGS_END_OF_LIST) == 0 && iCount != 0); +} diff --git a/sys/dev/ic/mpt_debug.c.orig b/sys/dev/ic/mpt_debug.c.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/ic/mpt_debug.c.orig diff --git a/sys/dev/ic/mpt_mpilib.h b/sys/dev/ic/mpt_mpilib.h new file mode 100644 index 00000000000..d34e3f996f5 --- /dev/null +++ b/sys/dev/ic/mpt_mpilib.h @@ -0,0 +1,4259 @@ +/* $OpenBSD: mpt_mpilib.h,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt_mpilib.h,v 1.2 2003/04/16 23:24:01 thorpej Exp $ */ + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_TYPE.H + * Title: MPI Basic type definitions + * Creation Date: June 6, 2000 + * + * MPI Version: 01.02.01 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 11-02-00 01.01.01 Original release for post 1.0 work + * 02-20-01 01.01.02 Added define and ifdef for MPI_POINTER. + * 08-08-01 01.02.01 Original release for v1.2 work. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_TYPE_H +#define MPI_TYPE_H + + +/******************************************************************************* + * Define MPI_POINTER if it hasn't already been defined. By default MPI_POINTER + * is defined to be a near pointer. MPI_POINTER can be defined as a far pointer + * by defining MPI_POINTER as "far *" before this header file is included. + */ +#ifndef MPI_POINTER +#define MPI_POINTER * +#endif + + +/***************************************************************************** +* +* B a s i c T y p e s +* +*****************************************************************************/ + +#ifdef __NetBSD__ +typedef int8_t S8; +typedef uint8_t U8; +typedef int16_t S16; +typedef uint16_t U16; +typedef int32_t S32; +typedef uint32_t U32; +#else /* ! __NetBSD__ */ +typedef signed char S8; +typedef unsigned char U8; +typedef signed short S16; +typedef unsigned short U16; + +#if defined(unix) || defined(__arm) || defined(ALPHA) || defined(__GNUC__) + + typedef signed int S32; + typedef unsigned int U32; + +#else + + typedef signed long S32; + typedef unsigned long U32; + +#endif +#endif /* __NetBSD__ */ + + +typedef struct _S64 +{ + U32 Low; + S32 High; +} S64; + +typedef struct _U64 +{ + U32 Low; + U32 High; +} U64; + + +/****************************************************************************/ +/* Pointers */ +/****************************************************************************/ + +typedef S8 *PS8; +typedef U8 *PU8; +typedef S16 *PS16; +typedef U16 *PU16; +typedef S32 *PS32; +typedef U32 *PU32; +typedef S64 *PS64; +typedef U64 *PU64; + + +#endif + + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI.H + * Title: MPI Message independent structures and definitions + * Creation Date: July 27, 2000 + * + * MPI Version: 01.02.03 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition. + * 06-06-00 01.00.01 Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR. + * 06-22-00 01.00.02 Added MPI_IOCSTATUS_LAN_ definitions. + * Removed LAN_SUSPEND function definition. + * Added MPI_MSGFLAGS_CONTINUATION_REPLY definition. + * 06-30-00 01.00.03 Added MPI_CONTEXT_REPLY_TYPE_LAN definition. + * Added MPI_GET/SET_CONTEXT_REPLY_TYPE macros. + * 07-27-00 01.00.04 Added MPI_FAULT_ definitions. + * Removed MPI_IOCSTATUS_MSG/DATA_XFER_ERROR definitions. + * Added MPI_IOCSTATUS_INTERNAL_ERROR definition. + * Added MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH. + * 11-02-00 01.01.01 Original release for post 1.0 work. + * 12-04-00 01.01.02 Added new function codes. + * 01-09-01 01.01.03 Added more definitions to the system interface section + * Added MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT. + * 01-25-01 01.01.04 Changed MPI_VERSION_MINOR from 0x00 to 0x01. + * 02-20-01 01.01.05 Started using MPI_POINTER. + * Fixed value for MPI_DIAG_RW_ENABLE. + * Added defines for MPI_DIAG_PREVENT_IOC_BOOT and + * MPI_DIAG_CLEAR_FLASH_BAD_SIG. + * Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines. + * 02-27-01 01.01.06 Removed MPI_HOST_INDEX_REGISTER define. + * Added function codes for RAID. + * 04-09-01 01.01.07 Added alternate define for MPI_DOORBELL_ACTIVE, + * MPI_DOORBELL_USED, to better match the spec. + * 08-08-01 01.02.01 Original release for v1.2 work. + * Changed MPI_VERSION_MINOR from 0x01 to 0x02. + * Added define MPI_FUNCTION_TOOLBOX. + * 09-28-01 01.02.02 New function code MPI_SCSI_ENCLOSURE_PROCESSOR. + * 11-01-01 01.02.03 Changed name to MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_H +#define MPI_H + + +/***************************************************************************** +* +* M P I V e r s i o n D e f i n i t i o n s +* +*****************************************************************************/ + +#define MPI_VERSION_MAJOR (0x01) +#define MPI_VERSION_MINOR (0x02) +#define MPI_VERSION ((MPI_VERSION_MAJOR << 8) | MPI_VERSION_MINOR) + +/* Note: The major versions of 0xe0 through 0xff are reserved */ + +/***************************************************************************** +* +* I O C S t a t e D e f i n i t i o n s +* +*****************************************************************************/ + +#define MPI_IOC_STATE_RESET (0x00000000) +#define MPI_IOC_STATE_READY (0x10000000) +#define MPI_IOC_STATE_OPERATIONAL (0x20000000) +#define MPI_IOC_STATE_FAULT (0x40000000) + +#define MPI_IOC_STATE_MASK (0xF0000000) +#define MPI_IOC_STATE_SHIFT (28) + +/* Fault state codes (product independent range 0x8000-0xFFFF) */ + +#define MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR (0x8111) +#define MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT (0x8112) +#define MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR (0x8113) +#define MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT (0x8114) +#define MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR (0x8115) +#define MPI_FAULT_DATA_SEND_PCI_BUS_FAULT (0x8116) +#define MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR (0x8117) +#define MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT (0x8118) + + +/***************************************************************************** +* +* P C I S y s t e m I n t e r f a c e R e g i s t e r s +* +*****************************************************************************/ + +/* S y s t e m D o o r b e l l */ +#define MPI_DOORBELL_OFFSET (0x00000000) +#define MPI_DOORBELL_ACTIVE (0x08000000) /* DoorbellUsed */ +#define MPI_DOORBELL_USED (MPI_DOORBELL_ACTIVE) +#define MPI_DOORBELL_ACTIVE_SHIFT (27) +#define MPI_DOORBELL_WHO_INIT_MASK (0x07000000) +#define MPI_DOORBELL_WHO_INIT_SHIFT (24) +#define MPI_DOORBELL_FUNCTION_MASK (0xFF000000) +#define MPI_DOORBELL_FUNCTION_SHIFT (24) +#define MPI_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) +#define MPI_DOORBELL_ADD_DWORDS_SHIFT (16) +#define MPI_DOORBELL_DATA_MASK (0x0000FFFF) + + +#define MPI_WRITE_SEQUENCE_OFFSET (0x00000004) +#define MPI_WRSEQ_KEY_VALUE_MASK (0x0000000F) +#define MPI_WRSEQ_1ST_KEY_VALUE (0x04) +#define MPI_WRSEQ_2ND_KEY_VALUE (0x0B) +#define MPI_WRSEQ_3RD_KEY_VALUE (0x02) +#define MPI_WRSEQ_4TH_KEY_VALUE (0x07) +#define MPI_WRSEQ_5TH_KEY_VALUE (0x0D) + +#define MPI_DIAGNOSTIC_OFFSET (0x00000008) +#define MPI_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) +#define MPI_DIAG_PREVENT_IOC_BOOT (0x00000200) +#define MPI_DIAG_DRWE (0x00000080) +#define MPI_DIAG_FLASH_BAD_SIG (0x00000040) +#define MPI_DIAG_RESET_HISTORY (0x00000020) +#define MPI_DIAG_RW_ENABLE (0x00000010) +#define MPI_DIAG_RESET_ADAPTER (0x00000004) +#define MPI_DIAG_DISABLE_ARM (0x00000002) +#define MPI_DIAG_MEM_ENABLE (0x00000001) + +#define MPI_TEST_BASE_ADDRESS_OFFSET (0x0000000C) + +#define MPI_DIAG_RW_DATA_OFFSET (0x00000010) + +#define MPI_DIAG_RW_ADDRESS_OFFSET (0x00000014) + +#define MPI_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) +#define MPI_HIS_IOP_DOORBELL_STATUS (0x80000000) +#define MPI_HIS_REPLY_MESSAGE_INTERRUPT (0x00000008) +#define MPI_HIS_DOORBELL_INTERRUPT (0x00000001) + +#define MPI_HOST_INTERRUPT_MASK_OFFSET (0x00000034) +#define MPI_HIM_RIM (0x00000008) +#define MPI_HIM_DIM (0x00000001) + +#define MPI_REQUEST_QUEUE_OFFSET (0x00000040) +#define MPI_REQUEST_POST_FIFO_OFFSET (0x00000040) + +#define MPI_REPLY_QUEUE_OFFSET (0x00000044) +#define MPI_REPLY_POST_FIFO_OFFSET (0x00000044) +#define MPI_REPLY_FREE_FIFO_OFFSET (0x00000044) + + + +/***************************************************************************** +* +* M e s s a g e F r a m e D e s c r i p t o r s +* +*****************************************************************************/ + +#define MPI_REQ_MF_DESCRIPTOR_NB_MASK (0x00000003) +#define MPI_REQ_MF_DESCRIPTOR_F_BIT (0x00000004) +#define MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK (0xFFFFFFF8) + +#define MPI_ADDRESS_REPLY_A_BIT (0x80000000) +#define MPI_ADDRESS_REPLY_ADDRESS_MASK (0x7FFFFFFF) + +#define MPI_CONTEXT_REPLY_A_BIT (0x80000000) +#define MPI_CONTEXT_REPLY_TYPE_MASK (0x60000000) +#define MPI_CONTEXT_REPLY_TYPE_SCSI_INIT (0x00) +#define MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET (0x01) +#define MPI_CONTEXT_REPLY_TYPE_LAN (0x02) +#define MPI_CONTEXT_REPLY_TYPE_SHIFT (29) +#define MPI_CONTEXT_REPLY_CONTEXT_MASK (0x1FFFFFFF) + + +/****************************************************************************/ +/* Context Reply macros */ +/****************************************************************************/ + +#define MPI_GET_CONTEXT_REPLY_TYPE(x) (((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \ + >> MPI_CONTEXT_REPLY_TYPE_SHIFT) + +#define MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \ + ((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) | \ + (((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) & \ + MPI_CONTEXT_REPLY_TYPE_MASK)) + + +/***************************************************************************** +* +* M e s s a g e F u n c t i o n s +* 0x80 -> 0x8F reserved for private message use per product +* +* +*****************************************************************************/ + +#define MPI_FUNCTION_SCSI_IO_REQUEST (0x00) +#define MPI_FUNCTION_SCSI_TASK_MGMT (0x01) +#define MPI_FUNCTION_IOC_INIT (0x02) +#define MPI_FUNCTION_IOC_FACTS (0x03) +#define MPI_FUNCTION_CONFIG (0x04) +#define MPI_FUNCTION_PORT_FACTS (0x05) +#define MPI_FUNCTION_PORT_ENABLE (0x06) +#define MPI_FUNCTION_EVENT_NOTIFICATION (0x07) +#define MPI_FUNCTION_EVENT_ACK (0x08) +#define MPI_FUNCTION_FW_DOWNLOAD (0x09) +#define MPI_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A) +#define MPI_FUNCTION_TARGET_ASSIST (0x0B) +#define MPI_FUNCTION_TARGET_STATUS_SEND (0x0C) +#define MPI_FUNCTION_TARGET_MODE_ABORT (0x0D) +#define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC (0x0E) /* obsolete name */ +#define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC (0x0F) /* obsolete name */ +#define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC (0x10) /* obsolete name */ +#define MPI_FUNCTION_TARGET_FC_ABORT (0x11) /* obsolete name */ +#define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST (0x0E) +#define MPI_FUNCTION_FC_LINK_SRVC_RSP (0x0F) +#define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND (0x10) +#define MPI_FUNCTION_FC_ABORT (0x11) +#define MPI_FUNCTION_FW_UPLOAD (0x12) +#define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND (0x13) +#define MPI_FUNCTION_FC_PRIMITIVE_SEND (0x14) + +#define MPI_FUNCTION_RAID_ACTION (0x15) +#define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) + +#define MPI_FUNCTION_TOOLBOX (0x17) + +#define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) + +#define MPI_FUNCTION_LAN_SEND (0x20) +#define MPI_FUNCTION_LAN_RECEIVE (0x21) +#define MPI_FUNCTION_LAN_RESET (0x22) + +#define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) +#define MPI_FUNCTION_IO_UNIT_RESET (0x41) +#define MPI_FUNCTION_HANDSHAKE (0x42) +#define MPI_FUNCTION_REPLY_FRAME_REMOVAL (0x43) + + + +/***************************************************************************** +* +* S c a t t e r G a t h e r E l e m e n t s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Simple element structures */ +/****************************************************************************/ + +typedef struct _SGE_SIMPLE32 +{ + U32 FlagsLength; + U32 Address; +} SGE_SIMPLE32, MPI_POINTER PTR_SGE_SIMPLE32, + SGESimple32_t, MPI_POINTER pSGESimple32_t; + +typedef struct _SGE_SIMPLE64 +{ + U32 FlagsLength; + U64 Address; +} SGE_SIMPLE64, MPI_POINTER PTR_SGE_SIMPLE64, + SGESimple64_t, MPI_POINTER pSGESimple64_t; + +typedef struct _SGE_SIMPLE_UNION +{ + U32 FlagsLength; + union + { + U32 Address32; + U64 Address64; + } _u; +} SGESimpleUnion_t, MPI_POINTER pSGESimpleUnion_t, + SGE_SIMPLE_UNION, MPI_POINTER PTR_SGE_SIMPLE_UNION; + +/****************************************************************************/ +/* Chain element structures */ +/****************************************************************************/ + +typedef struct _SGE_CHAIN32 +{ + U16 Length; + U8 NextChainOffset; + U8 Flags; + U32 Address; +} SGE_CHAIN32, MPI_POINTER PTR_SGE_CHAIN32, + SGEChain32_t, MPI_POINTER pSGEChain32_t; + +typedef struct _SGE_CHAIN64 +{ + U16 Length; + U8 NextChainOffset; + U8 Flags; + U64 Address; +} SGE_CHAIN64, MPI_POINTER PTR_SGE_CHAIN64, + SGEChain64_t, MPI_POINTER pSGEChain64_t; + +typedef struct _SGE_CHAIN_UNION +{ + U16 Length; + U8 NextChainOffset; + U8 Flags; + union + { + U32 Address32; + U64 Address64; + } _u; +} SGE_CHAIN_UNION, MPI_POINTER PTR_SGE_CHAIN_UNION, + SGEChainUnion_t, MPI_POINTER pSGEChainUnion_t; + +/****************************************************************************/ +/* Transaction Context element */ +/****************************************************************************/ + +typedef struct _SGE_TRANSACTION32 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[1]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION32, MPI_POINTER PTR_SGE_TRANSACTION32, + SGETransaction32_t, MPI_POINTER pSGETransaction32_t; + +typedef struct _SGE_TRANSACTION64 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[2]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION64, MPI_POINTER PTR_SGE_TRANSACTION64, + SGETransaction64_t, MPI_POINTER pSGETransaction64_t; + +typedef struct _SGE_TRANSACTION96 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[3]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION96, MPI_POINTER PTR_SGE_TRANSACTION96, + SGETransaction96_t, MPI_POINTER pSGETransaction96_t; + +typedef struct _SGE_TRANSACTION128 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[4]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION128, MPI_POINTER PTR_SGE_TRANSACTION128, + SGETransaction_t128, MPI_POINTER pSGETransaction_t128; + +typedef struct _SGE_TRANSACTION_UNION +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + union + { + U32 TransactionContext32[1]; + U32 TransactionContext64[2]; + U32 TransactionContext96[3]; + U32 TransactionContext128[4]; + } _u; + U32 TransactionDetails[1]; +} SGE_TRANSACTION_UNION, MPI_POINTER PTR_SGE_TRANSACTION_UNION, + SGETransactionUnion_t, MPI_POINTER pSGETransactionUnion_t; + + +/****************************************************************************/ +/* SGE IO types union for IO SGL's */ +/****************************************************************************/ + +typedef struct _SGE_IO_UNION +{ + union + { + SGE_SIMPLE_UNION Simple; + SGE_CHAIN_UNION Chain; + } _u; +} SGE_IO_UNION, MPI_POINTER PTR_SGE_IO_UNION, + SGEIOUnion_t, MPI_POINTER pSGEIOUnion_t; + +/****************************************************************************/ +/* SGE union for SGL's with Simple and Transaction elements */ +/****************************************************************************/ + +typedef struct _SGE_TRANS_SIMPLE_UNION +{ + union + { + SGE_SIMPLE_UNION Simple; + SGE_TRANSACTION_UNION Transaction; + } _u; +} SGE_TRANS_SIMPLE_UNION, MPI_POINTER PTR_SGE_TRANS_SIMPLE_UNION, + SGETransSimpleUnion_t, MPI_POINTER pSGETransSimpleUnion_t; + +/****************************************************************************/ +/* All SGE types union */ +/****************************************************************************/ + +typedef struct _SGE_MPI_UNION +{ + union + { + SGE_SIMPLE_UNION Simple; + SGE_CHAIN_UNION Chain; + SGE_TRANSACTION_UNION Transaction; + } _u; +} SGE_MPI_UNION, MPI_POINTER PTR_SGE_MPI_UNION, + MPI_SGE_UNION_t, MPI_POINTER pMPI_SGE_UNION_t, + SGEAllUnion_t, MPI_POINTER pSGEAllUnion_t; + + +/****************************************************************************/ +/* SGE field definition and masks */ +/****************************************************************************/ + +/* Flags field bit definitions */ + +#define MPI_SGE_FLAGS_LAST_ELEMENT (0x80) +#define MPI_SGE_FLAGS_END_OF_BUFFER (0x40) +#define MPI_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) +#define MPI_SGE_FLAGS_LOCAL_ADDRESS (0x08) +#define MPI_SGE_FLAGS_DIRECTION (0x04) +#define MPI_SGE_FLAGS_ADDRESS_SIZE (0x02) +#define MPI_SGE_FLAGS_END_OF_LIST (0x01) + +#define MPI_SGE_FLAGS_SHIFT (24) + +#define MPI_SGE_LENGTH_MASK (0x00FFFFFF) +#define MPI_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) + +/* Element Type */ + +#define MPI_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) +#define MPI_SGE_FLAGS_SIMPLE_ELEMENT (0x10) +#define MPI_SGE_FLAGS_CHAIN_ELEMENT (0x30) +#define MPI_SGE_FLAGS_ELEMENT_MASK (0x30) + +/* Address location */ + +#define MPI_SGE_FLAGS_SYSTEM_ADDRESS (0x00) + +/* Direction */ + +#define MPI_SGE_FLAGS_IOC_TO_HOST (0x00) +#define MPI_SGE_FLAGS_HOST_TO_IOC (0x04) + +/* Address Size */ + +#define MPI_SGE_FLAGS_32_BIT_ADDRESSING (0x00) +#define MPI_SGE_FLAGS_64_BIT_ADDRESSING (0x02) + +/* Context Size */ + +#define MPI_SGE_FLAGS_32_BIT_CONTEXT (0x00) +#define MPI_SGE_FLAGS_64_BIT_CONTEXT (0x02) +#define MPI_SGE_FLAGS_96_BIT_CONTEXT (0x04) +#define MPI_SGE_FLAGS_128_BIT_CONTEXT (0x06) + +#define MPI_SGE_CHAIN_OFFSET_MASK (0x00FF0000) +#define MPI_SGE_CHAIN_OFFSET_SHIFT (16) + + +/****************************************************************************/ +/* SGE operation Macros */ +/****************************************************************************/ + + /* SIMPLE FlagsLength manipulations... */ +#define MPI_SGE_SET_FLAGS(f) ((U32)(f) << MPI_SGE_FLAGS_SHIFT) +#define MPI_SGE_GET_FLAGS(fl) (((fl) & ~MPI_SGE_LENGTH_MASK) >> MPI_SGE_FLAGS_SHIFT) +#define MPI_SGE_LENGTH(fl) ((fl) & MPI_SGE_LENGTH_MASK) +#define MPI_SGE_CHAIN_LENGTH(fl) ((fl) & MPI_SGE_CHAIN_LENGTH_MASK) + +#define MPI_SGE_SET_FLAGS_LENGTH(f,l) (MPI_SGE_SET_FLAGS(f) | MPI_SGE_LENGTH(l)) + +#define MPI_pSGE_GET_FLAGS(psg) MPI_SGE_GET_FLAGS((psg)->FlagsLength) +#define MPI_pSGE_GET_LENGTH(psg) MPI_SGE_LENGTH((psg)->FlagsLength) +#define MPI_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f,l) + /* CAUTION - The following are READ-MODIFY-WRITE! */ +#define MPI_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI_SGE_SET_FLAGS(f) +#define MPI_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI_SGE_LENGTH(l) + +#define MPI_GET_CHAIN_OFFSET(x) ((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT) + + + +/***************************************************************************** +* +* S t a n d a r d M e s s a g e S t r u c t u r e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Standard message request header for all request messages */ +/****************************************************************************/ + +typedef struct _MSG_REQUEST_HEADER +{ + U8 Reserved[2]; /* function specific */ + U8 ChainOffset; + U8 Function; + U8 Reserved1[3]; /* function specific */ + U8 MsgFlags; + U32 MsgContext; +} MSG_REQUEST_HEADER, MPI_POINTER PTR_MSG_REQUEST_HEADER, + MPIHeader_t, MPI_POINTER pMPIHeader_t; + + +/****************************************************************************/ +/* Default Reply */ +/****************************************************************************/ + +typedef struct _MSG_DEFAULT_REPLY +{ + U8 Reserved[2]; /* function specific */ + U8 MsgLength; + U8 Function; + U8 Reserved1[3]; /* function specific */ + U8 MsgFlags; + U32 MsgContext; + U8 Reserved2[2]; /* function specific */ + U16 IOCStatus; + U32 IOCLogInfo; +} MSG_DEFAULT_REPLY, MPI_POINTER PTR_MSG_DEFAULT_REPLY, + MPIDefaultReply_t, MPI_POINTER pMPIDefaultReply_t; + + +/* MsgFlags definition for all replies */ + +#define MPI_MSGFLAGS_CONTINUATION_REPLY (0x80) + + +/***************************************************************************** +* +* I O C S t a t u s V a l u e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Common IOCStatus values for all replies */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_SUCCESS (0x0000) +#define MPI_IOCSTATUS_INVALID_FUNCTION (0x0001) +#define MPI_IOCSTATUS_BUSY (0x0002) +#define MPI_IOCSTATUS_INVALID_SGL (0x0003) +#define MPI_IOCSTATUS_INTERNAL_ERROR (0x0004) +#define MPI_IOCSTATUS_RESERVED (0x0005) +#define MPI_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) +#define MPI_IOCSTATUS_INVALID_FIELD (0x0007) +#define MPI_IOCSTATUS_INVALID_STATE (0x0008) + +/****************************************************************************/ +/* Config IOCStatus values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) +#define MPI_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) +#define MPI_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) +#define MPI_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) +#define MPI_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) +#define MPI_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) + +/****************************************************************************/ +/* SCSIIO Reply (SPI & FCP) initiator values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) +#define MPI_IOCSTATUS_SCSI_INVALID_BUS (0x0041) +#define MPI_IOCSTATUS_SCSI_INVALID_TARGETID (0x0042) +#define MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) +#define MPI_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) +#define MPI_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) +#define MPI_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) +#define MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) +#define MPI_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) +#define MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) +#define MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) +#define MPI_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) +#define MPI_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) + +/****************************************************************************/ +/* SCSI (SPI & FCP) target values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_TARGET_PRIORITY_IO (0x0060) +#define MPI_IOCSTATUS_TARGET_INVALID_PORT (0x0061) +#define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX (0x0062) +#define MPI_IOCSTATUS_TARGET_ABORTED (0x0063) +#define MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) +#define MPI_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) +#define MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) +#define MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT (0x006B) + +/****************************************************************************/ +/* Additional FCP target values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_TARGET_FC_ABORTED (0x0066) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID (0x0067) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_FC_DID_INVALID (0x0068) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT (0x0069) /* obsolete */ + +/****************************************************************************/ +/* Fibre Channel Direct Access values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_FC_ABORTED (0x0066) +#define MPI_IOCSTATUS_FC_RX_ID_INVALID (0x0067) +#define MPI_IOCSTATUS_FC_DID_INVALID (0x0068) +#define MPI_IOCSTATUS_FC_NODE_LOGGED_OUT (0x0069) + +/****************************************************************************/ +/* LAN values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND (0x0080) +#define MPI_IOCSTATUS_LAN_DEVICE_FAILURE (0x0081) +#define MPI_IOCSTATUS_LAN_TRANSMIT_ERROR (0x0082) +#define MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED (0x0083) +#define MPI_IOCSTATUS_LAN_RECEIVE_ERROR (0x0084) +#define MPI_IOCSTATUS_LAN_RECEIVE_ABORTED (0x0085) +#define MPI_IOCSTATUS_LAN_PARTIAL_PACKET (0x0086) +#define MPI_IOCSTATUS_LAN_CANCELED (0x0087) + + +/****************************************************************************/ +/* IOCStatus flag to indicate that log info is available */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) +#define MPI_IOCSTATUS_MASK (0x7FFF) + +/****************************************************************************/ +/* LogInfo Types */ +/****************************************************************************/ + +#define MPI_IOCLOGINFO_TYPE_MASK (0xF0000000) +#define MPI_IOCLOGINFO_TYPE_NONE (0x0) +#define MPI_IOCLOGINFO_TYPE_SCSI (0x1) +#define MPI_IOCLOGINFO_TYPE_FC (0x2) +#define MPI_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) + + +#endif + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_CNFG.H + * Title: MPI Config message, structures, and Pages + * Creation Date: July 27, 2000 + * + * MPI Version: 01.02.05 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. + * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 + * fields to FC_DEVICE_0 page, updated the page version. + * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in + * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages + * and updated the page versions. + * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 + * page and updated the page version. + * Added Information field and _INFO_PARAMS_NEGOTIATED + * definitionto SCSI_DEVICE_0 page. + * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the + * page version. + * Added BucketsRemaining to LAN_1 page, redefined the + * state values, and updated the page version. + * Revised bus width definitions in SCSI_PORT_0, + * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. + * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page + * version. + * Moved FC_DEVICE_0 PageAddress description to spec. + * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field + * widths in IOC_0 page and updated the page version. + * 11-02-00 01.01.01 Original release for post 1.0 work + * Added Manufacturing pages, IO Unit Page 2, SCSI SPI + * Port Page 2, FC Port Page 4, FC Port Page 5 + * 11-15-00 01.01.02 Interim changes to match proposals + * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. + * 12-05-00 01.01.04 Modified config page actions. + * 01-09-01 01.01.05 Added defines for page address formats. + * Data size for Manufacturing pages 2 and 3 no longer + * defined here. + * Io Unit Page 2 size is fixed at 4 adapters and some + * flags were changed. + * SCSI Port Page 2 Device Settings modified. + * New fields added to FC Port Page 0 and some flags + * cleaned up. + * Removed impedance flash from FC Port Page 1. + * Added FC Port pages 6 and 7. + * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. + * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. + * Added some LinkType defines for FcPortPage0. + * 02-20-01 01.01.08 Started using MPI_POINTER. + * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with + * MPI_CONFIG_PAGETYPE_RAID_VOLUME. + * Added definitions and structures for IOC Page 2 and + * RAID Volume Page 2. + * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. + * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. + * Added VendorId and ProductRevLevel fields to + * RAIDVOL2_IM_PHYS_ID struct. + * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ + * defines to make them compatible to MPI version 1.0. + * Added structure offset comments. + * 04-09-01 01.01.11 Added some new defines for the PageAddress field and + * removed some obsolete ones. + * Added IO Unit Page 3. + * Modified defines for Scsi Port Page 2. + * Modified RAID Volume Pages. + * 08-08-01 01.02.01 Original release for v1.2 work. + * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. + * Added defines for the SEP bits in RVP2 VolumeSettings. + * Modified the DeviceSettings field in RVP2 to use the + * proper structure. + * Added defines for SES, SAF-TE, and cross channel for + * IOCPage2 CapabilitiesFlags. + * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. + * Removed define for + * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. + * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. + * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. + * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY + * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. + * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, + * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and + * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and + * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. + * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED + * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. + * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. + * Added rejected bits to SCSI Device Page 0 Information. + * Increased size of ALPA array in FC Port Page 2 by one + * and removed a one byte reserved field. + * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in + * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. + * Added structures for Manufacturing Page 4, IO Unit + * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and + * RAID PhysDisk Page 0. + * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. + * Modified some of the new defines to make them 32 + * character unique. + * Modified how variable length pages (arrays) are defined. + * Added generic defines for hot spare pools and RAID + * volume types. + * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_CNFG_H +#define MPI_CNFG_H + + +/***************************************************************************** +* +* C o n f i g M e s s a g e a n d S t r u c t u r e s +* +*****************************************************************************/ + +typedef struct _CONFIG_PAGE_HEADER +{ + U8 PageVersion; /* 00h */ + U8 PageLength; /* 01h */ + U8 PageNumber; /* 02h */ + U8 PageType; /* 03h */ +} fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, + ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; + +typedef union _CONFIG_PAGE_HEADER_UNION +{ + ConfigPageHeader_t Struct; + U8 Bytes[4]; + U16 Word16[2]; + U32 Word32; +} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, + fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; + + +/**************************************************************************** +* PageType field values +****************************************************************************/ +#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) +#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) +#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) +#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) +#define MPI_CONFIG_PAGEATTR_MASK (0xF0) + +#define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) +#define MPI_CONFIG_PAGETYPE_IOC (0x01) +#define MPI_CONFIG_PAGETYPE_BIOS (0x02) +#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) +#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) +#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) +#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) +#define MPI_CONFIG_PAGETYPE_LAN (0x07) +#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) +#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) +#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) +#define MPI_CONFIG_PAGETYPE_MASK (0x0F) + +#define MPI_CONFIG_TYPENUM_MASK (0x0FFF) + + +/**************************************************************************** +* PageAddress field values +****************************************************************************/ +#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) + +#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) +#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) +#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) +#define MPI_SCSI_DEVICE_BUS_SHIFT (8) + +#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) +#define MPI_FC_PORT_PGAD_PORT_SHIFT (28) +#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) +#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) +#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) +#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) + +#define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) +#define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) +#define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) +#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) +#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) +#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) +#define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) +#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) +#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) +#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) +#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) +#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) +#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) + +#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) +#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) + + + +/**************************************************************************** +* Config Request Message +****************************************************************************/ +typedef struct _MSG_CONFIG +{ + U8 Action; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[8]; /* 0Ch */ + fCONFIG_PAGE_HEADER Header; /* 14h */ + U32 PageAddress; /* 18h */ + SGE_IO_UNION PageBufferSGE; /* 1Ch */ +} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, + Config_t, MPI_POINTER pConfig_t; + + +/**************************************************************************** +* Action field values +****************************************************************************/ +#define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) +#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) +#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) +#define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) +#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) +#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) +#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) + + +/* Config Reply Message */ +typedef struct _MSG_CONFIG_REPLY +{ + U8 Action; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[2]; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + fCONFIG_PAGE_HEADER Header; /* 14h */ +} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, + ConfigReply_t, MPI_POINTER pConfigReply_t; + + + +/***************************************************************************** +* +* C o n f i g u r a t i o n P a g e s +* +*****************************************************************************/ + +/**************************************************************************** +* Manufacturing Config pages +****************************************************************************/ +#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) +#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) +#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) +#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) +#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) +#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) +#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) +#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) +#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) +#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) +#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) + +typedef struct _CONFIG_PAGE_MANUFACTURING_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 ChipName[16]; /* 04h */ + U8 ChipRevision[8]; /* 14h */ + U8 BoardName[16]; /* 1Ch */ + U8 BoardAssembly[16]; /* 2Ch */ + U8 BoardTracerNumber[16]; /* 3Ch */ + +} fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, + ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; + +#define MPI_MANUFACTURING0_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_MANUFACTURING_1 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 VPD[256]; /* 04h */ +} fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, + ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; + +#define MPI_MANUFACTURING1_PAGEVERSION (0x00) + + +typedef struct _MPI_CHIP_REVISION_ID +{ + U16 DeviceID; /* 00h */ + U8 PCIRevisionID; /* 02h */ + U8 Reserved; /* 03h */ +} MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, + MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS +#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) +#endif + +typedef struct _CONFIG_PAGE_MANUFACTURING_2 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + MPI_CHIP_REVISION_ID ChipId; /* 04h */ + U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ +} fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, + ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; + +#define MPI_MANUFACTURING2_PAGEVERSION (0x00) + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_MAN_PAGE_3_INFO_WORDS +#define MPI_MAN_PAGE_3_INFO_WORDS (1) +#endif + +typedef struct _CONFIG_PAGE_MANUFACTURING_3 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + MPI_CHIP_REVISION_ID ChipId; /* 04h */ + U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ +} fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, + ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; + +#define MPI_MANUFACTURING3_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_MANUFACTURING_4 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved1; /* 04h */ + U8 InfoOffset0; /* 08h */ + U8 InfoSize0; /* 09h */ + U8 InfoOffset1; /* 0Ah */ + U8 InfoSize1; /* 0Bh */ + U8 InquirySize; /* 0Ch */ + U8 Reserved2; /* 0Dh */ + U16 Reserved3; /* 0Eh */ + U8 InquiryData[56]; /* 10h */ + U32 ISVolumeSettings; /* 48h */ + U32 IMEVolumeSettings; /* 4Ch */ + U32 IMVolumeSettings; /* 50h */ +} fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, + ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; + +#define MPI_MANUFACTURING4_PAGEVERSION (0x00) + + +/**************************************************************************** +* IO Unit Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_IO_UNIT_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U64 UniqueValue; /* 04h */ +} fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, + IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; + +#define MPI_IOUNITPAGE0_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_IO_UNIT_1 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ +} fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, + IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; + +#define MPI_IOUNITPAGE1_PAGEVERSION (0x00) + +/* IO Unit Page 1 Flags defines */ + +#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) +#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) +#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) +#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) +#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) +#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) + + +typedef struct _MPI_ADAPTER_INFO +{ + U8 PciBusNumber; /* 00h */ + U8 PciDeviceAndFunctionNumber; /* 01h */ + U16 AdapterFlags; /* 02h */ +} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, + MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; + +#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) +#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) + +typedef struct _CONFIG_PAGE_IO_UNIT_2 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U32 BiosVersion; /* 08h */ + MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ +} fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, + IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; + +#define MPI_IOUNITPAGE2_PAGEVERSION (0x00) + +#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) +#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) +#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) +#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX +#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IO_UNIT_3 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 GPIOCount; /* 04h */ + U8 Reserved1; /* 05h */ + U16 Reserved2; /* 06h */ + U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ +} fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, + IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; + +#define MPI_IOUNITPAGE3_PAGEVERSION (0x01) + +#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) +#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) +#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) +#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) + + +/**************************************************************************** +* IOC Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_IOC_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 TotalNVStore; /* 04h */ + U32 FreeNVStore; /* 08h */ + U16 VendorID; /* 0Ch */ + U16 DeviceID; /* 0Eh */ + U8 RevisionID; /* 10h */ + U8 Reserved[3]; /* 11h */ + U32 ClassCode; /* 14h */ + U16 SubsystemVendorID; /* 18h */ + U16 SubsystemID; /* 1Ah */ +} fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, + IOCPage0_t, MPI_POINTER pIOCPage0_t; + +#define MPI_IOCPAGE0_PAGEVERSION (0x01) + + +typedef struct _CONFIG_PAGE_IOC_1 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U32 CoalescingTimeout; /* 08h */ + U8 CoalescingDepth; /* 0Ch */ + U8 Reserved[3]; /* 0Dh */ +} fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, + IOCPage1_t, MPI_POINTER pIOCPage1_t; + +#define MPI_IOCPAGE1_PAGEVERSION (0x00) + +#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) + + +typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL +{ + U8 VolumeID; /* 00h */ + U8 VolumeBus; /* 01h */ + U8 VolumeIOC; /* 02h */ + U8 VolumePageNumber; /* 03h */ + U8 VolumeType; /* 04h */ + U8 Reserved2; /* 05h */ + U16 Reserved3; /* 06h */ +} fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, + ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX +#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_2 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 CapabilitiesFlags; /* 04h */ + U8 NumActiveVolumes; /* 08h */ + U8 MaxVolumes; /* 09h */ + U8 NumActivePhysDisks; /* 0Ah */ + U8 MaxPhysDisks; /* 0Bh */ + fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ +} fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, + IOCPage2_t, MPI_POINTER pIOCPage2_t; + +#define MPI_IOCPAGE2_PAGEVERSION (0x01) + +/* IOC Page 2 Capabilities flags */ + +#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) +#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) +#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) +#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) +#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) +#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) + +/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ + +#define MPI_RAID_VOL_TYPE_IS (0x00) +#define MPI_RAID_VOL_TYPE_IME (0x01) +#define MPI_RAID_VOL_TYPE_IM (0x02) + + +typedef struct _IOC_3_PHYS_DISK +{ + U8 PhysDiskID; /* 00h */ + U8 PhysDiskBus; /* 01h */ + U8 PhysDiskIOC; /* 02h */ + U8 PhysDiskNum; /* 03h */ +} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, + Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX +#define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_3 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 NumPhysDisks; /* 04h */ + U8 Reserved1; /* 05h */ + U16 Reserved2; /* 06h */ + IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ +} fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, + IOCPage3_t, MPI_POINTER pIOCPage3_t; + +#define MPI_IOCPAGE3_PAGEVERSION (0x00) + + +typedef struct _IOC_4_SEP +{ + U8 SEPTargetID; /* 00h */ + U8 SEPBus; /* 01h */ + U16 Reserved; /* 02h */ +} IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, + Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_4_SEP_MAX +#define MPI_IOC_PAGE_4_SEP_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_4 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 ActiveSEP; /* 04h */ + U8 MaxSEP; /* 05h */ + U16 Reserved1; /* 06h */ + IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ +} fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, + IOCPage4_t, MPI_POINTER pIOCPage4_t; + +#define MPI_IOCPAGE4_PAGEVERSION (0x00) + + +/**************************************************************************** +* SCSI Port Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_SCSI_PORT_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Capabilities; /* 04h */ + U32 PhysicalInterface; /* 08h */ +} fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, + SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; + +#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) + +#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) +#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) +#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) +#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) +#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) +#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) +#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) + +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) + + +typedef struct _CONFIG_PAGE_SCSI_PORT_1 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Configuration; /* 04h */ + U32 OnBusTimerValue; /* 08h */ +} fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, + SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; + +#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) + +#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) +#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) + + +typedef struct _MPI_DEVICE_INFO +{ + U8 Timeout; /* 00h */ + U8 SyncFactor; /* 01h */ + U16 DeviceFlags; /* 02h */ +} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, + MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; + +typedef struct _CONFIG_PAGE_SCSI_PORT_2 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 PortFlags; /* 04h */ + U32 PortSettings; /* 08h */ + MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ +} fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, + SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; + +#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) + +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) + +#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) +#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) +#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) +#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) +#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) +#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) +#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) +#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) +#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) +#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) +#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) +#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) + +#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) +#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) +#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) +#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) +#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) +#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) + + +/**************************************************************************** +* SCSI Target Device Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 NegotiatedParameters; /* 04h */ + U32 Information; /* 08h */ +} fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, + SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; + +#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02) + +#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) +#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) +#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) +#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) +#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) +#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) +#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) + +#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) +#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) +#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) +#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) + + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 RequestedParameters; /* 04h */ + U32 Reserved; /* 08h */ + U32 Configuration; /* 0Ch */ +} fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, + SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; + +#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03) + +#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) +#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) +#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) +#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) +#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) +#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) +#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) + +#define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003) +#define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300) + +#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) +#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) + + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 DomainValidation; /* 04h */ + U32 ParityPipeSelect; /* 08h */ + U32 DataPipeSelect; /* 0Ch */ +} fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, + SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; + +#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00) + +#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) +#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) +#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) +#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) +#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) +#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) +#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) +#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) +#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) + +#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) + +#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) +#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) +#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) +#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) +#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) +#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) +#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) + + +/**************************************************************************** +* FC Port Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_FC_PORT_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U8 MPIPortNumber; /* 08h */ + U8 LinkType; /* 09h */ + U8 PortState; /* 0Ah */ + U8 Reserved; /* 0Bh */ + U32 PortIdentifier; /* 0Ch */ + U64 WWNN; /* 10h */ + U64 WWPN; /* 18h */ + U32 SupportedServiceClass; /* 20h */ + U32 SupportedSpeeds; /* 24h */ + U32 CurrentSpeed; /* 28h */ + U32 MaxFrameSize; /* 2Ch */ + U64 FabricWWNN; /* 30h */ + U64 FabricWWPN; /* 38h */ + U32 DiscoveredPortsCount; /* 40h */ + U32 MaxInitiators; /* 44h */ +} fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, + FCPortPage0_t, MPI_POINTER pFCPortPage0_t; + +#define MPI_FCPORTPAGE0_PAGEVERSION (0x01) + +#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) +#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) +#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) +#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) +#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) + +#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) +#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) +#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030) + +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) + +#define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) +#define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) +#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) +#define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) +#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) +#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) +#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) +#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) +#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) +#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) +#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) +#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) +#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) +#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) +#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) +#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) + +#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ +#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ +#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ +#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ +#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ +#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ +#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ +#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ + +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) + +#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ +#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ +#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ + +#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED +#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED +#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED + + +typedef struct _CONFIG_PAGE_FC_PORT_1 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U64 NoSEEPROMWWNN; /* 08h */ + U64 NoSEEPROMWWPN; /* 10h */ + U8 HardALPA; /* 18h */ + U8 LinkConfig; /* 19h */ + U8 TopologyConfig; /* 1Ah */ + U8 Reserved; /* 1Bh */ +} fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, + FCPortPage1_t, MPI_POINTER pFCPortPage1_t; + +#define MPI_FCPORTPAGE1_PAGEVERSION (0x02) + +#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) +#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) +#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) +#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) + +#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) +#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) +#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) +#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) +#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) +#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) + +#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) + +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) + +#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) +#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) +#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) +#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) + + +typedef struct _CONFIG_PAGE_FC_PORT_2 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 NumberActive; /* 04h */ + U8 ALPA[127]; /* 05h */ +} fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, + FCPortPage2_t, MPI_POINTER pFCPortPage2_t; + +#define MPI_FCPORTPAGE2_PAGEVERSION (0x01) + + +typedef struct _WWN_FORMAT +{ + U64 WWNN; /* 00h */ + U64 WWPN; /* 08h */ +} WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, + WWNFormat, MPI_POINTER pWWNFormat; + +typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID +{ + WWN_FORMAT WWN; + U32 Did; +} FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, + PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; + +typedef struct _FC_PORT_PERSISTENT +{ + FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ + U8 TargetID; /* 10h */ + U8 Bus; /* 11h */ + U16 Flags; /* 12h */ +} FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, + PersistentData_t, MPI_POINTER pPersistentData_t; + +#define MPI_PERSISTENT_FLAGS_SHIFT (16) +#define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) +#define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) +#define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) +#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) +#define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX +#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_FC_PORT_3 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ +} fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, + FCPortPage3_t, MPI_POINTER pFCPortPage3_t; + +#define MPI_FCPORTPAGE3_PAGEVERSION (0x01) + + +typedef struct _CONFIG_PAGE_FC_PORT_4 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 PortFlags; /* 04h */ + U32 PortSettings; /* 08h */ +} fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, + FCPortPage4_t, MPI_POINTER pFCPortPage4_t; + +#define MPI_FCPORTPAGE4_PAGEVERSION (0x00) + +#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) + +#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) +#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) +#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) +#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) +#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) +#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) +#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) + + +typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO +{ + U8 Flags; /* 00h */ + U8 AliasAlpa; /* 01h */ + U16 Reserved; /* 02h */ + U64 AliasWWNN; /* 04h */ + U64 AliasWWPN; /* 0Ch */ +} fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, + MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, + FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX +#define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_FC_PORT_5 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */ +} fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, + FCPortPage5_t, MPI_POINTER pFCPortPage5_t; + +#define MPI_FCPORTPAGE5_PAGEVERSION (0x00) + +#define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01) +#define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02) + + +typedef struct _CONFIG_PAGE_FC_PORT_6 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved; /* 04h */ + U64 TimeSinceReset; /* 08h */ + U64 TxFrames; /* 10h */ + U64 RxFrames; /* 18h */ + U64 TxWords; /* 20h */ + U64 RxWords; /* 28h */ + U64 LipCount; /* 30h */ + U64 NosCount; /* 38h */ + U64 ErrorFrames; /* 40h */ + U64 DumpedFrames; /* 48h */ + U64 LinkFailureCount; /* 50h */ + U64 LossOfSyncCount; /* 58h */ + U64 LossOfSignalCount; /* 60h */ + U64 PrimativeSeqErrCount; /* 68h */ + U64 InvalidTxWordCount; /* 70h */ + U64 InvalidCrcCount; /* 78h */ + U64 FcpInitiatorIoCount; /* 80h */ +} fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, + FCPortPage6_t, MPI_POINTER pFCPortPage6_t; + +#define MPI_FCPORTPAGE6_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_7 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved; /* 04h */ + U8 PortSymbolicName[256]; /* 08h */ +} fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, + FCPortPage7_t, MPI_POINTER pFCPortPage7_t; + +#define MPI_FCPORTPAGE7_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_8 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 BitVector[8]; /* 04h */ +} fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, + FCPortPage8_t, MPI_POINTER pFCPortPage8_t; + +#define MPI_FCPORTPAGE8_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_9 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved; /* 04h */ + U64 GlobalWWPN; /* 08h */ + U64 GlobalWWNN; /* 10h */ + U32 UnitType; /* 18h */ + U32 PhysicalPortNumber; /* 1Ch */ + U32 NumAttachedNodes; /* 20h */ + U16 IPVersion; /* 24h */ + U16 UDPPortNumber; /* 26h */ + U8 IPAddress[16]; /* 28h */ + U16 Reserved1; /* 38h */ + U16 TopologyDiscoveryFlags; /* 3Ah */ +} fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, + FCPortPage9_t, MPI_POINTER pFCPortPage9_t; + +#define MPI_FCPORTPAGE9_PAGEVERSION (0x00) + + +/**************************************************************************** +* FC Device Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_FC_DEVICE_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U64 WWNN; /* 04h */ + U64 WWPN; /* 0Ch */ + U32 PortIdentifier; /* 14h */ + U8 Protocol; /* 18h */ + U8 Flags; /* 19h */ + U16 BBCredit; /* 1Ah */ + U16 MaxRxFrameSize; /* 1Ch */ + U8 Reserved1; /* 1Eh */ + U8 PortNumber; /* 1Fh */ + U8 FcPhLowestVersion; /* 20h */ + U8 FcPhHighestVersion; /* 21h */ + U8 CurrentTargetID; /* 22h */ + U8 CurrentBus; /* 23h */ +} fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, + FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; + +#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) + +#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) + +#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) + +#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) +#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) +#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) + + +/**************************************************************************** +* RAID Volume Config Pages +****************************************************************************/ + +typedef struct _RAID_VOL0_PHYS_DISK +{ + U16 Reserved; /* 00h */ + U8 PhysDiskMap; /* 02h */ + U8 PhysDiskNum; /* 03h */ +} RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, + RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; + +#define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) +#define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) + +typedef struct _RAID_VOL0_STATUS +{ + U8 Flags; /* 00h */ + U8 State; /* 01h */ + U16 Reserved; /* 02h */ +} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, + RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; + +/* RAID Volume Page 0 VolumeStatus defines */ + +#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) +#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) +#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) + +#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) +#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) +#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) + +typedef struct _RAID_VOL0_SETTINGS +{ + U16 Settings; /* 00h */ + U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ + U8 Reserved; /* 02h */ +} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, + RaidVol0Settings, MPI_POINTER pRaidVol0Settings; + +/* RAID Volume Page 0 VolumeSettings defines */ + +#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) +#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) +#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) +#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) +#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) +#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) + +/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ +#define MPI_RAID_HOT_SPARE_POOL_0 (0x01) +#define MPI_RAID_HOT_SPARE_POOL_1 (0x02) +#define MPI_RAID_HOT_SPARE_POOL_2 (0x04) +#define MPI_RAID_HOT_SPARE_POOL_3 (0x08) +#define MPI_RAID_HOT_SPARE_POOL_4 (0x10) +#define MPI_RAID_HOT_SPARE_POOL_5 (0x20) +#define MPI_RAID_HOT_SPARE_POOL_6 (0x40) +#define MPI_RAID_HOT_SPARE_POOL_7 (0x80) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX +#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_RAID_VOL_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 VolumeID; /* 04h */ + U8 VolumeBus; /* 05h */ + U8 VolumeIOC; /* 06h */ + U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ + RAID_VOL0_STATUS VolumeStatus; /* 08h */ + RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ + U32 MaxLBA; /* 10h */ + U32 Reserved1; /* 14h */ + U32 StripeSize; /* 18h */ + U32 Reserved2; /* 1Ch */ + U32 Reserved3; /* 20h */ + U8 NumPhysDisks; /* 24h */ + U8 Reserved4; /* 25h */ + U16 Reserved5; /* 26h */ + RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ +} fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, + RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; + +#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00) + + +/**************************************************************************** +* RAID Physical Disk Config Pages +****************************************************************************/ + +typedef struct _RAID_PHYS_DISK0_ERROR_DATA +{ + U8 ErrorCdbByte; /* 00h */ + U8 ErrorSenseKey; /* 01h */ + U16 Reserved; /* 02h */ + U16 ErrorCount; /* 04h */ + U8 ErrorASC; /* 06h */ + U8 ErrorASCQ; /* 07h */ + U16 SmartCount; /* 08h */ + U8 SmartASC; /* 0Ah */ + U8 SmartASCQ; /* 0Bh */ +} RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, + RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; + +typedef struct _RAID_PHYS_DISK_INQUIRY_DATA +{ + U8 VendorID[8]; /* 00h */ + U8 ProductID[16]; /* 08h */ + U8 ProductRevLevel[4]; /* 18h */ + U8 Info[32]; /* 1Ch */ +} RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, + RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; + +typedef struct _RAID_PHYS_DISK0_SETTINGS +{ + U8 SepID; /* 00h */ + U8 SepBus; /* 01h */ + U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ + U8 PhysDiskSettings; /* 03h */ +} RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, + RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; + +typedef struct _RAID_PHYS_DISK0_STATUS +{ + U8 Flags; /* 00h */ + U8 State; /* 01h */ + U16 Reserved; /* 02h */ +} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, + RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; + +/* RAID Volume 2 IM Physical Disk DiskStatus flags */ + +#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) +#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) + +#define MPI_PHYSDISK0_STATUS_ONLINE (0x00) +#define MPI_PHYSDISK0_STATUS_MISSING (0x01) +#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) +#define MPI_PHYSDISK0_STATUS_FAILED (0x03) +#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) +#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) +#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) +#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) + +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 +{ + fCONFIG_PAGE_HEADER Header; /* 00h */ + U8 PhysDiskID; /* 04h */ + U8 PhysDiskBus; /* 05h */ + U8 PhysDiskIOC; /* 06h */ + U8 PhysDiskNum; /* 07h */ + RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ + U32 Reserved1; /* 0Ch */ + U32 Reserved2; /* 10h */ + U32 Reserved3; /* 14h */ + U8 DiskIdentifier[16]; /* 18h */ + RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ + RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ + U32 MaxLBA; /* 68h */ + RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ +} fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, + RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; + +#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) + + +/**************************************************************************** +* LAN Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_LAN_0 +{ + ConfigPageHeader_t Header; /* 00h */ + U16 TxRxModes; /* 04h */ + U16 Reserved; /* 06h */ + U32 PacketPrePad; /* 08h */ +} fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, + LANPage0_t, MPI_POINTER pLANPage0_t; + +#define MPI_LAN_PAGE0_PAGEVERSION (0x01) + +#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) +#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) +#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) + +typedef struct _CONFIG_PAGE_LAN_1 +{ + ConfigPageHeader_t Header; /* 00h */ + U16 Reserved; /* 04h */ + U8 CurrentDeviceState; /* 06h */ + U8 Reserved1; /* 07h */ + U32 MinPacketSize; /* 08h */ + U32 MaxPacketSize; /* 0Ch */ + U32 HardwareAddressLow; /* 10h */ + U32 HardwareAddressHigh; /* 14h */ + U32 MaxWireSpeedLow; /* 18h */ + U32 MaxWireSpeedHigh; /* 1Ch */ + U32 BucketsRemaining; /* 20h */ + U32 MaxReplySize; /* 24h */ + U32 NegWireSpeedLow; /* 28h */ + U32 NegWireSpeedHigh; /* 2Ch */ +} fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, + LANPage1_t, MPI_POINTER pLANPage1_t; + +#define MPI_LAN_PAGE1_PAGEVERSION (0x03) + +#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) +#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) + +#endif + + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_FC.H + * Title: MPI Fibre Channel messages and structures + * Creation Date: June 12, 2000 + * + * MPI Version: 01.02.02 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-12-00 01.00.02 Added _MSG_FC_ABORT_REPLY structure. + * 11-02-00 01.01.01 Original release for post 1.0 work + * 12-04-00 01.01.02 Added messages for Common Transport Send and + * Primitive Send. + * 01-09-01 01.01.03 Modifed some of the new flags to have an MPI prefix + * and modified the FcPrimitiveSend flags. + * 01-25-01 01.01.04 Move InitiatorIndex in LinkServiceRsp reply to a larger + * field. + * Added FC_ABORT_TYPE_CT_SEND_REQUEST and + * FC_ABORT_TYPE_EXLINKSEND_REQUEST for FcAbort request. + * Added MPI_FC_PRIM_SEND_FLAGS_STOP_SEND. + * 02-20-01 01.01.05 Started using MPI_POINTER. + * 03-27-01 01.01.06 Added Flags field to MSG_LINK_SERVICE_BUFFER_POST_REPLY + * and defined MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED. + * Added MPI_FC_PRIM_SEND_FLAGS_RESET_LINK define. + * Added structure offset comments. + * 04-09-01 01.01.07 Added RspLength field to MSG_LINK_SERVICE_RSP_REQUEST. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 09-28-01 01.02.02 Change name of reserved field in + * MSG_LINK_SERVICE_RSP_REPLY. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_FC_H +#define MPI_FC_H + + +/***************************************************************************** +* +* F C T a r g e t M o d e M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Link Service Buffer Post messages */ +/****************************************************************************/ + +typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REQUEST +{ + U8 BufferPostFlags; /* 00h */ + U8 BufferCount; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved; /* 04h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_TRANS_SIMPLE_UNION SGL; +} MSG_LINK_SERVICE_BUFFER_POST_REQUEST, + MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REQUEST, + LinkServiceBufferPostRequest_t, MPI_POINTER pLinkServiceBufferPostRequest_t; + +#define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01) + +typedef struct _WWNFORMAT +{ + U32 PortNameHigh; /* 00h */ + U32 PortNameLow; /* 04h */ + U32 NodeNameHigh; /* 08h */ + U32 NodeNameLow; /* 0Ch */ +} WWNFORMAT, + WwnFormat_t; + +/* Link Service Buffer Post Reply */ +typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REPLY +{ + U8 Flags; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TransferLength; /* 14h */ + U32 TransactionContext; /* 18h */ + U32 Rctl_Did; /* 1Ch */ + U32 Csctl_Sid; /* 20h */ + U32 Type_Fctl; /* 24h */ + U16 SeqCnt; /* 28h */ + U8 Dfctl; /* 2Ah */ + U8 SeqId; /* 2Bh */ + U16 Rxid; /* 2Ch */ + U16 Oxid; /* 2Eh */ + U32 Parameter; /* 30h */ + WWNFORMAT Wwn; /* 34h */ +} MSG_LINK_SERVICE_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REPLY, + LinkServiceBufferPostReply_t, MPI_POINTER pLinkServiceBufferPostReply_t; + +#define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80) + +#define MPI_FC_DID_MASK (0x00FFFFFF) +#define MPI_FC_DID_SHIFT (0) +#define MPI_FC_RCTL_MASK (0xFF000000) +#define MPI_FC_RCTL_SHIFT (24) +#define MPI_FC_SID_MASK (0x00FFFFFF) +#define MPI_FC_SID_SHIFT (0) +#define MPI_FC_CSCTL_MASK (0xFF000000) +#define MPI_FC_CSCTL_SHIFT (24) +#define MPI_FC_FCTL_MASK (0x00FFFFFF) +#define MPI_FC_FCTL_SHIFT (0) +#define MPI_FC_TYPE_MASK (0xFF000000) +#define MPI_FC_TYPE_SHIFT (24) + +/* obsolete name for the above */ +#define FCP_TARGET_DID_MASK (0x00FFFFFF) +#define FCP_TARGET_DID_SHIFT (0) +#define FCP_TARGET_RCTL_MASK (0xFF000000) +#define FCP_TARGET_RCTL_SHIFT (24) +#define FCP_TARGET_SID_MASK (0x00FFFFFF) +#define FCP_TARGET_SID_SHIFT (0) +#define FCP_TARGET_CSCTL_MASK (0xFF000000) +#define FCP_TARGET_CSCTL_SHIFT (24) +#define FCP_TARGET_FCTL_MASK (0x00FFFFFF) +#define FCP_TARGET_FCTL_SHIFT (0) +#define FCP_TARGET_TYPE_MASK (0xFF000000) +#define FCP_TARGET_TYPE_SHIFT (24) + + +/****************************************************************************/ +/* Link Service Response messages */ +/****************************************************************************/ + +typedef struct _MSG_LINK_SERVICE_RSP_REQUEST +{ + U8 RspFlags; /* 00h */ + U8 RspLength; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 Rctl_Did; /* 0Ch */ + U32 Csctl_Sid; /* 10h */ + U32 Type_Fctl; /* 14h */ + U16 SeqCnt; /* 18h */ + U8 Dfctl; /* 1Ah */ + U8 SeqId; /* 1Bh */ + U16 Rxid; /* 1Ch */ + U16 Oxid; /* 1Eh */ + U32 Parameter; /* 20h */ + SGE_SIMPLE_UNION SGL; /* 24h */ +} MSG_LINK_SERVICE_RSP_REQUEST, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REQUEST, + LinkServiceRspRequest_t, MPI_POINTER pLinkServiceRspRequest_t; + +#define LINK_SERVICE_RSP_FLAGS_IMMEDIATE (0x80) +#define LINK_SERVICE_RSP_FLAGS_PORT_MASK (0x01) + + +/* Link Service Response Reply */ +typedef struct _MSG_LINK_SERVICE_RSP_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved_0100_InitiatorIndex; /* 06h */ /* obsolete InitiatorIndex */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 InitiatorIndex; /* 14h */ +} MSG_LINK_SERVICE_RSP_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REPLY, + LinkServiceRspReply_t, MPI_POINTER pLinkServiceRspReply_t; + + +/****************************************************************************/ +/* Extended Link Service Send messages */ +/****************************************************************************/ + +typedef struct _MSG_EXLINK_SERVICE_SEND_REQUEST +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U32 MsgFlags_Did; /* 04h */ + U32 MsgContext; /* 08h */ + U32 ElsCommandCode; /* 0Ch */ + SGE_SIMPLE_UNION SGL; /* 10h */ +} MSG_EXLINK_SERVICE_SEND_REQUEST, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REQUEST, + ExLinkServiceSendRequest_t, MPI_POINTER pExLinkServiceSendRequest_t; + +#define EX_LINK_SERVICE_SEND_DID_MASK (0x00FFFFFF) +#define EX_LINK_SERVICE_SEND_DID_SHIFT (0) +#define EX_LINK_SERVICE_SEND_MSGFLAGS_MASK (0xFF000000) +#define EX_LINK_SERVICE_SEND_MSGFLAGS_SHIFT (24) + + +/* Extended Link Service Send Reply */ +typedef struct _MSG_EXLINK_SERVICE_SEND_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ResponseLength; /* 14h */ +} MSG_EXLINK_SERVICE_SEND_REPLY, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REPLY, + ExLinkServiceSendReply_t, MPI_POINTER pExLinkServiceSendReply_t; + +/****************************************************************************/ +/* FC Abort messages */ +/****************************************************************************/ + +typedef struct _MSG_FC_ABORT_REQUEST +{ + U8 AbortFlags; /* 00h */ + U8 AbortType; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 TransactionContextToAbort; /* 0Ch */ +} MSG_FC_ABORT_REQUEST, MPI_POINTER PTR_MSG_FC_ABORT_REQUEST, + FcAbortRequest_t, MPI_POINTER pFcAbortRequest_t; + +#define FC_ABORT_FLAG_PORT_MASK (0x01) + +#define FC_ABORT_TYPE_ALL_FC_BUFFERS (0x00) +#define FC_ABORT_TYPE_EXACT_FC_BUFFER (0x01) +#define FC_ABORT_TYPE_CT_SEND_REQUEST (0x02) +#define FC_ABORT_TYPE_EXLINKSEND_REQUEST (0x03) + +/* FC Abort Reply */ +typedef struct _MSG_FC_ABORT_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_FC_ABORT_REPLY, MPI_POINTER PTR_MSG_FC_ABORT_REPLY, + FcAbortReply_t, MPI_POINTER pFcAbortReply_t; + + +/****************************************************************************/ +/* FC Common Transport Send messages */ +/****************************************************************************/ + +typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REQUEST +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U32 MsgFlags_Did; /* 04h */ + U32 MsgContext; /* 08h */ + U16 CTCommandCode; /* 0Ch */ + U8 FsType; /* 0Eh */ + U8 Reserved1; /* 0Fh */ + SGE_SIMPLE_UNION SGL; /* 10h */ +} MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, + MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, + FcCommonTransportSendRequest_t, MPI_POINTER pFcCommonTransportSendRequest_t; + +#define MPI_FC_CT_SEND_DID_MASK (0x00FFFFFF) +#define MPI_FC_CT_SEND_DID_SHIFT (0) +#define MPI_FC_CT_SEND_MSGFLAGS_MASK (0xFF000000) +#define MPI_FC_CT_SEND_MSGFLAGS_SHIFT (24) + + +/* FC Common Transport Send Reply */ +typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ResponseLength; /* 14h */ +} MSG_FC_COMMON_TRANSPORT_SEND_REPLY, MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REPLY, + FcCommonTransportSendReply_t, MPI_POINTER pFcCommonTransportSendReply_t; + + +/****************************************************************************/ +/* FC Primitive Send messages */ +/****************************************************************************/ + +typedef struct _MSG_FC_PRIMITIVE_SEND_REQUEST +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 FcPrimitive[4]; /* 0Ch */ +} MSG_FC_PRIMITIVE_SEND_REQUEST, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REQUEST, + FcPrimitiveSendRequest_t, MPI_POINTER pFcPrimitiveSendRequest_t; + +#define MPI_FC_PRIM_SEND_FLAGS_PORT_MASK (0x01) +#define MPI_FC_PRIM_SEND_FLAGS_RESET_LINK (0x04) +#define MPI_FC_PRIM_SEND_FLAGS_STOP_SEND (0x08) +#define MPI_FC_PRIM_SEND_FLAGS_SEND_ONCE (0x10) +#define MPI_FC_PRIM_SEND_FLAGS_SEND_AROUND (0x20) +#define MPI_FC_PRIM_SEND_FLAGS_UNTIL_FULL (0x40) +#define MPI_FC_PRIM_SEND_FLAGS_FOREVER (0x80) + +/* FC Primitive Send Reply */ +typedef struct _MSG_FC_PRIMITIVE_SEND_REPLY +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_FC_PRIMITIVE_SEND_REPLY, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REPLY, + FcPrimitiveSendReply_t, MPI_POINTER pFcPrimitiveSendReply_t; + +#endif + + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_INIT.H + * Title: MPI initiator mode messages and structures + * Creation Date: June 8, 2000 + * + * MPI Version: 01.02.04 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. + * 11-02-00 01.01.01 Original release for post 1.0 work. + * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. + * 02-20-01 01.01.03 Started using MPI_POINTER. + * 03-27-01 01.01.04 Added structure offset comments. + * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. + * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for + * MSG_SCSI_IO_REPLY. + * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure + * Processor messages. + * 10-04-01 01.02.04 Added defines for SEP request Action field. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_INIT_H +#define MPI_INIT_H + + +/***************************************************************************** +* +* S C S I I n i t i a t o r M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* SCSI IO messages and assocaited structures */ +/****************************************************************************/ + +typedef struct _MSG_SCSI_IO_REQUEST +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 CDBLength; /* 04h */ + U8 SenseBufferLength; /* 05h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 LUN[8]; /* 0Ch */ + U32 Control; /* 14h */ + U8 CDB[16]; /* 18h */ + U32 DataLength; /* 28h */ + U32 SenseBufferLowAddr; /* 2Ch */ + SGE_IO_UNION SGL; /* 30h */ +} MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, + SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; + + +/* SCSIO MsgFlags bits */ + +#define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) +#define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) +#define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) +#define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) +#define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) +#define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) + +/* SCSIIO LUN fields */ + +#define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) +#define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) +#define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) +#define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) +#define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) +#define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) + +/* SCSIO Control bits */ + +#define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) +#define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) +#define MPI_SCSIIO_CONTROL_WRITE (0x01000000) +#define MPI_SCSIIO_CONTROL_READ (0x02000000) + +#define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) +#define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) + +#define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) +#define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) +#define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) +#define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) +#define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) +#define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) +#define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) + +#define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) +#define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) +#define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) +#define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) +#define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) +#define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) +#define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) +#define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) +#define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) + + +/* SCSIIO reply structure */ +typedef struct _MSG_SCSI_IO_REPLY +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 CDBLength; /* 04h */ + U8 SenseBufferLength; /* 05h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 SCSIStatus; /* 0Ch */ + U8 SCSIState; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TransferCount; /* 14h */ + U32 SenseCount; /* 18h */ + U32 ResponseInfo; /* 1Ch */ +} MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, + SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; + + +/* SCSIIO Reply SCSIStatus values (SAM-2 status codes) */ + +#define MPI_SCSI_STATUS_SUCCESS (0x00) +#define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) +#define MPI_SCSI_STATUS_CONDITION_MET (0x04) +#define MPI_SCSI_STATUS_BUSY (0x08) +#define MPI_SCSI_STATUS_INTERMEDIATE (0x10) +#define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) +#define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) +#define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) +#define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) +#define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) + + +/* SCSIIO Reply SCSIState values */ + +#define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) +#define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) +#define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) +#define MPI_SCSI_STATE_TERMINATED (0x08) +#define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) +#define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) + +/* SCSIIO Reply ResponseInfo values */ +/* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ + +#define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) +#define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) +#define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) +#define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) +#define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) +#define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) +#define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) + + +/****************************************************************************/ +/* SCSI Task Management messages */ +/****************************************************************************/ + +typedef struct _MSG_SCSI_TASK_MGMT +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved; /* 04h */ + U8 TaskType; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 LUN[8]; /* 0Ch */ + U32 Reserved2[7]; /* 14h */ + U32 TaskMsgContext; /* 30h */ +} MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, + SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; + +/* TaskType values */ + +#define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) +#define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) +#define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) +#define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) +#define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) + +/* MsgFlags bits */ +#define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) +#define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) +#define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) + +/* SCSI Task Management Reply */ +typedef struct _MSG_SCSI_TASK_MGMT_REPLY +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved; /* 04h */ + U8 TaskType; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[2]; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TerminationCount; /* 14h */ +} MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, + SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; + + +/****************************************************************************/ +/* SCSI Enclosure Processor messages */ +/****************************************************************************/ + +typedef struct _MSG_SEP_REQUEST +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Action; /* 04h */ + U8 Reserved1; /* 05h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 SlotStatus; /* 0Ch */ +} MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, + SEPRequest_t, MPI_POINTER pSEPRequest_t; + +/* Action defines */ +#define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) +#define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) + +/* SlotStatus bits for MSG_SEP_REQUEST */ +#define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) +#define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) +#define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) +#define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) +#define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) +#define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) +#define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) +#define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) +#define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) +#define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) +#define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) +#define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) +#define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) +#define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) +#define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) +#define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) +#define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) +#define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) + + +typedef struct _MSG_SEP_REPLY +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Action; /* 04h */ + U8 Reserved1; /* 05h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 SlotStatus; /* 14h */ +} MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, + SEPReply_t, MPI_POINTER pSEPReply_t; + +/* SlotStatus bits for MSG_SEP_REPLY */ +#define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) +#define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) +#define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) +#define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) +#define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) +#define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) +#define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) +#define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) +#define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) +#define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) +#define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) +#define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) +#define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) +#define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) +#define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) +#define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) +#define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) +#define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) +#define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) +#define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) +#define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) +#define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) + +#endif + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_IOC.H + * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages + * Creation Date: August 11, 2000 + * + * MPI Version: 01.02.04 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. + * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. + * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. + * Added _MSG_EVENT_ACK_REPLY structure. + * Added _MSG_FW_DOWNLOAD_REPLY structure. + * Added _MSG_TOOLBOX_REPLY structure. + * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. + * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, + * _LINK_STATUS, _LOOP_STATE and _LOGOUT. + * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in + * _MSG_EVENT_ACK_REPLY structure to match specification. + * 11-02-00 01.01.01 Original release for post 1.0 work. + * Added a value for Manufacturer to WhoInit. + * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and + * removed toolbox message. + * 01-09-01 01.01.03 Added event enabled and disabled defines. + * Added structures for FwHeader and DataHeader. + * Added ImageType to FwUpload reply. + * 02-20-01 01.01.04 Started using MPI_POINTER. + * 02-27-01 01.01.05 Added event for RAID status change and its event data. + * Added IocNumber field to MSG_IOC_FACTS_REPLY. + * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. + * Added structure offset comments. + * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. + * 08-08-01 01.02.01 Original release for v1.2 work. + * New format for FWVersion and ProductId in + * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. + * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and + * related structure and defines. + * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. + * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. + * Replaced a reserved field in MSG_IOC_FACTS_REPLY with + * IOCExceptions and changed DataImageSize to reserved. + * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and + * MPI_FW_UPLOAD_ITYPE_NVDATA. + * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. + * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_IOC_H +#define MPI_IOC_H + + +/***************************************************************************** +* +* I O C M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* IOCInit message */ +/****************************************************************************/ + +typedef struct _MSG_IOC_INIT +{ + U8 WhoInit; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Flags; /* 04h */ + U8 MaxDevices; /* 05h */ + U8 MaxBuses; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 ReplyFrameSize; /* 0Ch */ + U8 Reserved1[2]; /* 0Eh */ + U32 HostMfaHighAddr; /* 10h */ + U32 SenseBufferHighAddr; /* 14h */ +} MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, + IOCInit_t, MPI_POINTER pIOCInit_t; + +/* WhoInit values */ +#define MPI_WHOINIT_NO_ONE (0x00) +#define MPI_WHOINIT_SYSTEM_BIOS (0x01) +#define MPI_WHOINIT_ROM_BIOS (0x02) +#define MPI_WHOINIT_PCI_PEER (0x03) +#define MPI_WHOINIT_HOST_DRIVER (0x04) +#define MPI_WHOINIT_MANUFACTURER (0x05) + +/* Flags values */ +#define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) + +typedef struct _MSG_IOC_INIT_REPLY +{ + U8 WhoInit; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Flags; /* 04h */ + U8 MaxDevices; /* 05h */ + U8 MaxBuses; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, + IOCInitReply_t, MPI_POINTER pIOCInitReply_t; + + + +/****************************************************************************/ +/* IOC Facts message */ +/****************************************************************************/ + +typedef struct _MSG_IOC_FACTS +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 01h */ + U8 Function; /* 02h */ + U8 Reserved1[3]; /* 03h */ + U8 MsgFlags; /* 04h */ + U32 MsgContext; /* 08h */ +} MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, + IOCFacts_t, MPI_POINTER pIOCFacts_t; + +typedef struct _MPI_FW_VERSION_STRUCT +{ + U8 Dev; /* 00h */ + U8 Unit; /* 01h */ + U8 Minor; /* 02h */ + U8 Major; /* 03h */ +} MPI_FW_VERSION_STRUCT; + +typedef union _MPI_FW_VERSION +{ + MPI_FW_VERSION_STRUCT Struct; + U32 Word; +} MPI_FW_VERSION; + +/* IOC Facts Reply */ +typedef struct _MSG_IOC_FACTS_REPLY +{ + U16 MsgVersion; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved; /* 04h */ + U8 IOCNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 IOCExceptions; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U8 MaxChainDepth; /* 14h */ + U8 WhoInit; /* 15h */ + U8 BlockSize; /* 16h */ + U8 Flags; /* 17h */ + U16 ReplyQueueDepth; /* 18h */ + U16 RequestFrameSize; /* 1Ah */ + U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ + U16 ProductID; /* 1Eh */ + U32 CurrentHostMfaHighAddr; /* 20h */ + U16 GlobalCredits; /* 24h */ + U8 NumberOfPorts; /* 26h */ + U8 EventState; /* 27h */ + U32 CurrentSenseBufferHighAddr; /* 28h */ + U16 CurReplyFrameSize; /* 2Ch */ + U8 MaxDevices; /* 2Eh */ + U8 MaxBuses; /* 2Fh */ + U32 FWImageSize; /* 30h */ + U32 Reserved4; /* 34h */ + MPI_FW_VERSION FWVersion; /* 38h */ +} MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, + IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; + +#define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) +#define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) + +#define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) + +#define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) + +#define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) +#define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) + + + +/***************************************************************************** +* +* P o r t M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Port Facts message and Reply */ +/****************************************************************************/ + +typedef struct _MSG_PORT_FACTS +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, + PortFacts_t, MPI_POINTER pPortFacts_t; + +typedef struct _MSG_PORT_FACTS_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U8 Reserved3; /* 14h */ + U8 PortType; /* 15h */ + U16 MaxDevices; /* 16h */ + U16 PortSCSIID; /* 18h */ + U16 ProtocolFlags; /* 1Ah */ + U16 MaxPostedCmdBuffers; /* 1Ch */ + U16 MaxPersistentIDs; /* 1Eh */ + U16 MaxLanBuckets; /* 20h */ + U16 Reserved4; /* 22h */ + U32 Reserved5; /* 24h */ +} MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, + PortFactsReply_t, MPI_POINTER pPortFactsReply_t; + + +/* PortTypes values */ + +#define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) +#define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) +#define MPI_PORTFACTS_PORTTYPE_FC (0x10) + +/* ProtocolFlags values */ + +#define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) +#define MPI_PORTFACTS_PROTOCOL_LAN (0x02) +#define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) +#define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) + + +/****************************************************************************/ +/* Port Enable Message */ +/****************************************************************************/ + +typedef struct _MSG_PORT_ENABLE +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, + PortEnable_t, MPI_POINTER pPortEnable_t; + +typedef struct _MSG_PORT_ENABLE_REPLY +{ + U8 Reserved[2]; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 PortNumber; /* 05h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, + PortEnableReply_t, MPI_POINTER pPortEnableReply_t; + + +/***************************************************************************** +* +* E v e n t M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Event Notification messages */ +/****************************************************************************/ + +typedef struct _MSG_EVENT_NOTIFY +{ + U8 Switch; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, + EventNotification_t, MPI_POINTER pEventNotification_t; + +/* Event Notification Reply */ + +typedef struct _MSG_EVENT_NOTIFY_REPLY +{ + U16 EventDataLength; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 AckRequired; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[2]; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 Event; /* 14h */ + U32 EventContext; /* 18h */ + U32 Data[1]; /* 1Ch */ +} MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, + EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; + +/* Event Acknowledge */ + +typedef struct _MSG_EVENT_ACK +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 Event; /* 0Ch */ + U32 EventContext; /* 10h */ +} MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, + EventAck_t, MPI_POINTER pEventAck_t; + +typedef struct _MSG_EVENT_ACK_REPLY +{ + U8 Reserved[2]; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, + EventAckReply_t, MPI_POINTER pEventAckReply_t; + +/* Switch */ + +#define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) +#define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) + +/* Event */ + +#define MPI_EVENT_NONE (0x00000000) +#define MPI_EVENT_LOG_DATA (0x00000001) +#define MPI_EVENT_STATE_CHANGE (0x00000002) +#define MPI_EVENT_UNIT_ATTENTION (0x00000003) +#define MPI_EVENT_IOC_BUS_RESET (0x00000004) +#define MPI_EVENT_EXT_BUS_RESET (0x00000005) +#define MPI_EVENT_RESCAN (0x00000006) +#define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) +#define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) +#define MPI_EVENT_LOGOUT (0x00000009) +#define MPI_EVENT_EVENT_CHANGE (0x0000000A) +#define MPI_EVENT_INTEGRATED_RAID (0x0000000B) +#define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) +#define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) + +/* AckRequired field values */ + +#define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) +#define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) + +/* EventChange Event data */ + +typedef struct _EVENT_DATA_EVENT_CHANGE +{ + U8 EventState; /* 00h */ + U8 Reserved; /* 01h */ + U16 Reserved1; /* 02h */ +} EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, + EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; + +/* SCSI Event data for Port, Bus and Device forms */ + +typedef struct _EVENT_DATA_SCSI +{ + U8 TargetID; /* 00h */ + U8 BusPort; /* 01h */ + U16 Reserved; /* 02h */ +} EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, + EventDataScsi_t, MPI_POINTER pEventDataScsi_t; + +/* SCSI Device Status Change Event data */ + +typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ReasonCode; /* 02h */ + U8 LUN; /* 03h */ + U8 ASC; /* 04h */ + U8 ASCQ; /* 05h */ + U16 Reserved; /* 06h */ +} EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, + MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, + MpiEventDataScsiDeviceStatusChange_t, + MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; + +/* MPI SCSI Device Status Change Event data ReasonCode values */ +#define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) +#define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) +#define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) + +/* MPI Link Status Change Event data */ + +typedef struct _EVENT_DATA_LINK_STATUS +{ + U8 State; /* 00h */ + U8 Reserved; /* 01h */ + U16 Reserved1; /* 02h */ + U8 Reserved2; /* 04h */ + U8 Port; /* 05h */ + U16 Reserved3; /* 06h */ +} EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, + EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; + +#define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) +#define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) + +/* MPI Loop State Change Event data */ + +typedef struct _EVENT_DATA_LOOP_STATE +{ + U8 Character4; /* 00h */ + U8 Character3; /* 01h */ + U8 Type; /* 02h */ + U8 Reserved; /* 03h */ + U8 Reserved1; /* 04h */ + U8 Port; /* 05h */ + U16 Reserved2; /* 06h */ +} EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, + EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; + +#define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) +#define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) +#define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) + +/* MPI LOGOUT Event data */ + +typedef struct _EVENT_DATA_LOGOUT +{ + U32 NPortID; /* 00h */ + U8 Reserved; /* 04h */ + U8 Port; /* 05h */ + U16 Reserved1; /* 06h */ +} EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, + EventDataLogout_t, MPI_POINTER pEventDataLogout_t; + +/* MPI Integrated RAID Event data */ + +typedef struct _EVENT_DATA_RAID +{ + U8 VolumeID; /* 00h */ + U8 VolumeBus; /* 01h */ + U8 ReasonCode; /* 02h */ + U8 PhysDiskNum; /* 03h */ + U8 ASC; /* 04h */ + U8 ASCQ; /* 05h */ + U16 Reserved; /* 06h */ + U32 SettingsStatus; /* 08h */ +} EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, + MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; + +/* MPI Integrated RAID Event data ReasonCode values */ +#define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) +#define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) +#define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) +#define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) +#define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) +#define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) +#define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) +#define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) +#define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) +#define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) +#define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) +#define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) + + +/***************************************************************************** +* +* F i r m w a r e L o a d M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Firmware Download message and associated structures */ +/****************************************************************************/ + +typedef struct _MSG_FW_DOWNLOAD +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_MPI_UNION SGL; /* 0Ch */ +} MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, + FWDownload_t, MPI_POINTER pFWDownload_t; + +#define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) +#define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) +#define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) +#define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) + + +typedef struct _FWDownloadTCSGE +{ + U8 Reserved; /* 00h */ + U8 ContextSize; /* 01h */ + U8 DetailsLength; /* 02h */ + U8 Flags; /* 03h */ + U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ + U32 ImageOffset; /* 08h */ + U32 ImageSize; /* 0Ch */ +} FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, + FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; + +/* Firmware Download reply */ +typedef struct _MSG_FW_DOWNLOAD_REPLY +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, + FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; + + +/****************************************************************************/ +/* Firmware Upload message and associated structures */ +/****************************************************************************/ + +typedef struct _MSG_FW_UPLOAD +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_MPI_UNION SGL; /* 0Ch */ +} MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, + FWUpload_t, MPI_POINTER pFWUpload_t; + +#define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) +#define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) +#define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) +#define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) + +typedef struct _FWUploadTCSGE +{ + U8 Reserved; /* 00h */ + U8 ContextSize; /* 01h */ + U8 DetailsLength; /* 02h */ + U8 Flags; /* 03h */ + U32 Reserved1; /* 04h */ + U32 ImageOffset; /* 08h */ + U32 ImageSize; /* 0Ch */ +} FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, + FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; + +/* Firmware Upload reply */ +typedef struct _MSG_FW_UPLOAD_REPLY +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ActualImageSize; /* 14h */ +} MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, + FWUploadReply_t, MPI_POINTER pFWUploadReply_t; + + +typedef struct _MPI_FW_HEADER +{ + U32 ArmBranchInstruction0; /* 00h */ + U32 Signature0; /* 04h */ + U32 Signature1; /* 08h */ + U32 Signature2; /* 0Ch */ + U32 ArmBranchInstruction1; /* 10h */ + U32 ArmBranchInstruction2; /* 14h */ + U32 Reserved; /* 18h */ + U32 Checksum; /* 1Ch */ + U16 VendorId; /* 20h */ + U16 ProductId; /* 22h */ + MPI_FW_VERSION FWVersion; /* 24h */ + U32 SeqCodeVersion; /* 28h */ + U32 ImageSize; /* 2Ch */ + U32 NextImageHeaderOffset; /* 30h */ + U32 LoadStartAddress; /* 34h */ + U32 IopResetVectorValue; /* 38h */ + U32 IopResetRegAddr; /* 3Ch */ + U32 VersionNameWhat; /* 40h */ + U8 VersionName[32]; /* 44h */ + U32 VendorNameWhat; /* 64h */ + U8 VendorName[32]; /* 68h */ +} MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, + MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; + +#define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) + +/* defines for using the ProductId field */ +#define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) +#define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) +#define MPI_FW_HEADER_PID_TYPE_FC (0x1000) + +#define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) +#define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) +#define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) +#define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) +#define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) +#define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) +#define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) + +#define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) +#define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) +#define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) +#define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) +#define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) +#define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) +#define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) +#define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) +#define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) +#define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) +#define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) +#define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) +#define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) +#define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) + +typedef struct _MPI_EXT_IMAGE_HEADER +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U16 Reserved1; /* 02h */ + U32 Checksum; /* 04h */ + U32 ImageSize; /* 08h */ + U32 NextImageHeaderOffset; /* 0Ch */ + U32 LoadStartAddress; /* 10h */ + U32 Reserved2; /* 14h */ +} MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, + MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; + +/* defines for the ImageType field */ +#define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) +#define MPI_EXT_IMAGE_TYPE_FW (0x01) +#define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) + +#endif + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_LAN.H + * Title: MPI LAN messages and structures + * Creation Date: June 30, 2000 + * + * MPI Version: 01.02.01 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added LANStatus field to _MSG_LAN_SEND_REPLY. + * Added LANStatus field to _MSG_LAN_RECEIVE_POST_REPLY. + * Moved ListCount field in _MSG_LAN_RECEIVE_POST_REPLY. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-12-00 01.00.02 Added MPI_ to BUCKETSTATUS_ definitions. + * 06-22-00 01.00.03 Major changes to match new LAN definition in 1.0 spec. + * 06-30-00 01.00.04 Added Context Reply definitions per revised proposal. + * Changed transaction context usage to bucket/buffer. + * 07-05-00 01.00.05 Removed LAN_RECEIVE_POST_BUCKET_CONTEXT_MASK definition + * to lan private header file + * 11-02-00 01.01.01 Original release for post 1.0 work + * 02-20-01 01.01.02 Started using MPI_POINTER. + * 03-27-01 01.01.03 Added structure offset comments. + * 08-08-01 01.02.01 Original release for v1.2 work. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_LAN_H +#define MPI_LAN_H + + +/****************************************************************************** +* +* L A N M e s s a g e s +* +*******************************************************************************/ + +/* LANSend messages */ + +typedef struct _MSG_LAN_SEND_REQUEST +{ + U16 Reserved; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_MPI_UNION SG_List[1]; /* 0Ch */ +} MSG_LAN_SEND_REQUEST, MPI_POINTER PTR_MSG_LAN_SEND_REQUEST, + LANSendRequest_t, MPI_POINTER pLANSendRequest_t; + + +typedef struct _MSG_LAN_SEND_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved2; /* 04h */ + U8 NumberOfContexts; /* 05h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 BufferContext; /* 14h */ +} MSG_LAN_SEND_REPLY, MPI_POINTER PTR_MSG_LAN_SEND_REPLY, + LANSendReply_t, MPI_POINTER pLANSendReply_t; + + +/* LANReceivePost */ + +typedef struct _MSG_LAN_RECEIVE_POST_REQUEST +{ + U16 Reserved; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 BucketCount; /* 0Ch */ + SGE_MPI_UNION SG_List[1]; /* 10h */ +} MSG_LAN_RECEIVE_POST_REQUEST, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REQUEST, + LANReceivePostRequest_t, MPI_POINTER pLANReceivePostRequest_t; + + +typedef struct _MSG_LAN_RECEIVE_POST_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved2; /* 04h */ + U8 NumberOfContexts; /* 05h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 BucketsRemaining; /* 14h */ + U32 PacketOffset; /* 18h */ + U32 PacketLength; /* 1Ch */ + U32 BucketContext[1]; /* 20h */ +} MSG_LAN_RECEIVE_POST_REPLY, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REPLY, + LANReceivePostReply_t, MPI_POINTER pLANReceivePostReply_t; + + +/* LANReset */ + +typedef struct _MSG_LAN_RESET_REQUEST +{ + U16 Reserved; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 05h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_LAN_RESET_REQUEST, MPI_POINTER PTR_MSG_LAN_RESET_REQUEST, + LANResetRequest_t, MPI_POINTER pLANResetRequest_t; + + +typedef struct _MSG_LAN_RESET_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_LAN_RESET_REPLY, MPI_POINTER PTR_MSG_LAN_RESET_REPLY, + LANResetReply_t, MPI_POINTER pLANResetReply_t; + + +/****************************************************************************/ +/* LAN Context Reply defines and macros */ +/****************************************************************************/ + +#define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF) +#define LAN_REPLY_PACKET_LENGTH_SHIFT (0) +#define LAN_REPLY_BUCKET_CONTEXT_MASK (0x07FF0000) +#define LAN_REPLY_BUCKET_CONTEXT_SHIFT (16) +#define LAN_REPLY_BUFFER_CONTEXT_MASK (0x07FFFFFF) +#define LAN_REPLY_BUFFER_CONTEXT_SHIFT (0) +#define LAN_REPLY_FORM_MASK (0x18000000) +#define LAN_REPLY_FORM_RECEIVE_SINGLE (0x00) +#define LAN_REPLY_FORM_RECEIVE_MULTIPLE (0x01) +#define LAN_REPLY_FORM_SEND_SINGLE (0x02) +#define LAN_REPLY_FORM_MESSAGE_CONTEXT (0x03) +#define LAN_REPLY_FORM_SHIFT (27) + +#define GET_LAN_PACKET_LENGTH(x) (((x) & LAN_REPLY_PACKET_LENGTH_MASK) \ + >> LAN_REPLY_PACKET_LENGTH_SHIFT) + +#define SET_LAN_PACKET_LENGTH(x, lth) \ + ((x) = ((x) & ~LAN_REPLY_PACKET_LENGTH_MASK) | \ + (((lth) << LAN_REPLY_PACKET_LENGTH_SHIFT) & \ + LAN_REPLY_PACKET_LENGTH_MASK)) + +#define GET_LAN_BUCKET_CONTEXT(x) (((x) & LAN_REPLY_BUCKET_CONTEXT_MASK) \ + >> LAN_REPLY_BUCKET_CONTEXT_SHIFT) + +#define SET_LAN_BUCKET_CONTEXT(x, ctx) \ + ((x) = ((x) & ~LAN_REPLY_BUCKET_CONTEXT_MASK) | \ + (((ctx) << LAN_REPLY_BUCKET_CONTEXT_SHIFT) & \ + LAN_REPLY_BUCKET_CONTEXT_MASK)) + +#define GET_LAN_BUFFER_CONTEXT(x) (((x) & LAN_REPLY_BUFFER_CONTEXT_MASK) \ + >> LAN_REPLY_BUFFER_CONTEXT_SHIFT) + +#define SET_LAN_BUFFER_CONTEXT(x, ctx) \ + ((x) = ((x) & ~LAN_REPLY_BUFFER_CONTEXT_MASK) | \ + (((ctx) << LAN_REPLY_BUFFER_CONTEXT_SHIFT) & \ + LAN_REPLY_BUFFER_CONTEXT_MASK)) + +#define GET_LAN_FORM(x) (((x) & LAN_REPLY_FORM_MASK) \ + >> LAN_REPLY_FORM_SHIFT) + +#define SET_LAN_FORM(x, frm) \ + ((x) = ((x) & ~LAN_REPLY_FORM_MASK) | \ + (((frm) << LAN_REPLY_FORM_SHIFT) & \ + LAN_REPLY_FORM_MASK)) + + +/****************************************************************************/ +/* LAN Current Device State defines */ +/****************************************************************************/ + +#define MPI_LAN_DEVICE_STATE_RESET (0x00) +#define MPI_LAN_DEVICE_STATE_OPERATIONAL (0x01) + + +/****************************************************************************/ +/* LAN Loopback defines */ +/****************************************************************************/ + +#define MPI_LAN_TX_MODES_ENABLE_LOOPBACK_SUPPRESSION (0x01) + +#endif + + +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_TARG.H + * Title: MPI Target mode messages and structures + * Creation Date: June 22, 2000 + * + * MPI Version: 01.02.04 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-22-00 01.00.02 Added _MSG_TARGET_CMD_BUFFER_POST_REPLY structure. + * Corrected DECSRIPTOR typo to DESCRIPTOR. + * 11-02-00 01.01.01 Original release for post 1.0 work + * Modified target mode to use IoIndex instead of + * HostIndex and IocIndex. Added Alias. + * 01-09-01 01.01.02 Added defines for TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER + * and TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER. + * 02-20-01 01.01.03 Started using MPI_POINTER. + * Added structures for MPI_TARGET_SCSI_SPI_CMD_BUFFER and + * MPI_TARGET_FCP_CMD_BUFFER. + * 03-27-01 01.01.04 Added structure offset comments. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 09-28-01 01.02.02 Added structure for MPI_TARGET_SCSI_SPI_STATUS_IU. + * Added PriorityReason field to some replies and + * defined more PriorityReason codes. + * Added some defines for to support previous version + * of MPI. + * 10-04-01 01.02.03 Added PriorityReason to MSG_TARGET_ERROR_REPLY. + * 11-01-01 01.02.04 Added define for TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_TARG_H +#define MPI_TARG_H + + +/****************************************************************************** +* +* S C S I T a r g e t M e s s a g e s +* +*******************************************************************************/ + +typedef struct _CMD_BUFFER_DESCRIPTOR +{ + U16 IoIndex; /* 00h */ + U16 Reserved; /* 02h */ + union /* 04h */ + { + U32 PhysicalAddress32; + U64 PhysicalAddress64; + } _u; +} CMD_BUFFER_DESCRIPTOR, MPI_POINTER PTR_CMD_BUFFER_DESCRIPTOR, + CmdBufferDescriptor_t, MPI_POINTER pCmdBufferDescriptor_t; + + +/****************************************************************************/ +/* Target Command Buffer Post Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_CMD_BUFFER_POST_REQUEST +{ + U8 BufferPostFlags; /* 00h */ + U8 BufferCount; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 BufferLength; /* 04h */ + U8 Reserved; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */ +} MSG_TARGET_CMD_BUFFER_POST_REQUEST, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST, + TargetCmdBufferPostRequest_t, MPI_POINTER pTargetCmdBufferPostRequest_t; + +#define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01) +#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80) +#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0) +#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_64 (1) +#define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80) + +#define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF) +#define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */ + + +typedef struct _MSG_TARGET_CMD_BUFFER_POST_REPLY +{ + U8 BufferPostFlags; /* 00h */ + U8 BufferCount; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 BufferLength; /* 04h */ + U8 Reserved; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_TARGET_CMD_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY, + TargetCmdBufferPostReply_t, MPI_POINTER pTargetCmdBufferPostReply_t; + +/* the following structure is obsolete as of MPI v1.2 */ +typedef struct _MSG_PRIORITY_CMD_RECEIVED_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 PriorityReason; /* 0Ch */ + U8 Reserved3; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ReplyWord; /* 14h */ +} MSG_PRIORITY_CMD_RECEIVED_REPLY, MPI_POINTER PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY, + PriorityCommandReceivedReply_t, MPI_POINTER pPriorityCommandReceivedReply_t; + +#define PRIORITY_REASON_NO_DISCONNECT (0x00) +#define PRIORITY_REASON_SCSI_TASK_MANAGEMENT (0x01) +#define PRIORITY_REASON_CMD_PARITY_ERR (0x02) +#define PRIORITY_REASON_MSG_OUT_PARITY_ERR (0x03) +#define PRIORITY_REASON_LQ_CRC_ERR (0x04) +#define PRIORITY_REASON_CMD_CRC_ERR (0x05) +#define PRIORITY_REASON_PROTOCOL_ERR (0x06) +#define PRIORITY_REASON_DATA_OUT_PARITY_ERR (0x07) +#define PRIORITY_REASON_DATA_OUT_CRC_ERR (0x08) +#define PRIORITY_REASON_UNKNOWN (0xFF) + + +typedef struct _MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 PriorityReason; /* 0Ch */ + U8 Reserved3; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ReplyWord; /* 14h */ +} MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, + MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, + TargetCmdBufferPostErrorReply_t, MPI_POINTER pTargetCmdBufferPostErrorReply_t; + + +typedef struct _MPI_TARGET_FCP_CMD_BUFFER +{ + U8 FcpLun[8]; /* 00h */ + U8 FcpCntl[4]; /* 08h */ + U8 FcpCdb[16]; /* 0Ch */ + U32 FcpDl; /* 1Ch */ +} MPI_TARGET_FCP_CMD_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_CMD_BUFFER, + MpiTargetFcpCmdBuffer, MPI_POINTER pMpiTargetFcpCmdBuffer; + + +typedef struct _MPI_TARGET_SCSI_SPI_CMD_BUFFER +{ + /* SPI L_Q information unit */ + U8 L_QType; /* 00h */ + U8 Reserved; /* 01h */ + U16 Tag; /* 02h */ + U8 LogicalUnitNumber[8]; /* 04h */ + U32 DataLength; /* 0Ch */ + /* SPI command information unit */ + U8 ReservedFirstByteOfCommandIU; /* 10h */ + U8 TaskAttribute; /* 11h */ + U8 TaskManagementFlags; /* 12h */ + U8 AdditionalCDBLength; /* 13h */ + U8 CDB[16]; /* 14h */ +} MPI_TARGET_SCSI_SPI_CMD_BUFFER, + MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER, + MpiTargetScsiSpiCmdBuffer, MPI_POINTER pMpiTargetScsiSpiCmdBuffer; + + +/****************************************************************************/ +/* Target Assist Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_ASSIST_REQUEST +{ + U8 StatusCode; /* 00h */ + U8 TargetAssistFlags; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 QueueTag; /* 04h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 ReplyWord; /* 0Ch */ + U8 LUN[8]; /* 10h */ + U32 RelativeOffset; /* 18h */ + U32 DataLength; /* 1Ch */ + SGE_IO_UNION SGL[1]; /* 20h */ +} MSG_TARGET_ASSIST_REQUEST, MPI_POINTER PTR_MSG_TARGET_ASSIST_REQUEST, + TargetAssistRequest_t, MPI_POINTER pTargetAssistRequest_t; + +#define TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01) +#define TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02) +#define TARGET_ASSIST_FLAGS_HIGH_PRIORITY (0x04) +#define TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80) + + +typedef struct _MSG_TARGET_ERROR_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 PriorityReason; /* 0Ch */ + U8 Reserved3; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ReplyWord; /* 14h */ + U32 TransferCount; /* 18h */ +} MSG_TARGET_ERROR_REPLY, MPI_POINTER PTR_MSG_TARGET_ERROR_REPLY, + TargetErrorReply_t, MPI_POINTER pTargetErrorReply_t; + + +/****************************************************************************/ +/* Target Status Send Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_STATUS_SEND_REQUEST +{ + U8 StatusCode; /* 00h */ + U8 StatusFlags; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 QueueTag; /* 04h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 ReplyWord; /* 0Ch */ + U8 LUN[8]; /* 10h */ + SGE_SIMPLE_UNION StatusDataSGE; /* 18h */ +} MSG_TARGET_STATUS_SEND_REQUEST, MPI_POINTER PTR_MSG_TARGET_STATUS_SEND_REQUEST, + TargetStatusSendRequest_t, MPI_POINTER pTargetStatusSendRequest_t; + +#define TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS (0x01) +#define TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY (0x04) +#define TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER (0x80) + +typedef struct _MPI_TARGET_FCP_RSP_BUFFER +{ + U8 Reserved0[8]; /* 00h */ + U8 FcpStatus; /* 08h */ + U8 FcpFlags; /* 09h */ + U8 Reserved1[2]; /* 0Ah */ + U32 FcpResid; /* 0Ch */ + U32 FcpSenseLength; /* 10h */ + U32 FcpResponseLength; /* 14h */ + U8 FcpResponseData[8]; /* 18h */ + U8 FcpSenseData[32]; /* Pad to 64 bytes */ /* 20h */ +} MPI_TARGET_FCP_RSP_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_RSP_BUFFER, + MpiTargetFcpRspBuffer, MPI_POINTER pMpiTargetFcpRspBuffer; + +typedef struct _MPI_TARGET_SCSI_SPI_STATUS_IU +{ + U8 Reserved0; /* 00h */ + U8 Reserved1; /* 01h */ + U8 Valid; /* 02h */ + U8 Status; /* 03h */ + U32 SenseDataListLength; /* 04h */ + U32 PktFailuresListLength; /* 08h */ + U8 SenseData[52]; /* Pad the IU to 64 bytes */ /* 0Ch */ +} MPI_TARGET_SCSI_SPI_STATUS_IU, MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_STATUS_IU, + TargetScsiSpiStatusIU_t, MPI_POINTER pTargetScsiSpiStatusIU_t; + +/****************************************************************************/ +/* Target Mode Abort Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_MODE_ABORT_REQUEST +{ + U8 AbortType; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 ReplyWord; /* 0Ch */ + U32 MsgContextToAbort; /* 10h */ +} MSG_TARGET_MODE_ABORT, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT, + TargetModeAbort_t, MPI_POINTER pTargetModeAbort_t; + +#define TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS (0x00) +#define TARGET_MODE_ABORT_TYPE_ALL_IO (0x01) +#define TARGET_MODE_ABORT_TYPE_EXACT_IO (0x02) +#define TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST (0x03) + +/* Target Mode Abort Reply */ + +typedef struct _MSG_TARGET_MODE_ABORT_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 AbortCount; /* 14h */ +} MSG_TARGET_MODE_ABORT_REPLY, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT_REPLY, + TargetModeAbortReply_t, MPI_POINTER pTargetModeAbortReply_t; + + +/****************************************************************************/ +/* Target Mode Context Reply */ +/****************************************************************************/ + +#define TARGET_MODE_REPLY_IO_INDEX_MASK (0x00003FFF) +#define TARGET_MODE_REPLY_IO_INDEX_SHIFT (0) +#define TARGET_MODE_REPLY_INITIATOR_INDEX_MASK (0x03FFC000) +#define TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT (14) +#define TARGET_MODE_REPLY_ALIAS_MASK (0x0C000000) +#define TARGET_MODE_REPLY_ALIAS_SHIFT (26) +#define TARGET_MODE_REPLY_PORT_MASK (0x10000000) +#define TARGET_MODE_REPLY_PORT_SHIFT (28) + + +#define GET_IO_INDEX(x) (((x) & TARGET_MODE_REPLY_IO_INDEX_MASK) \ + >> TARGET_MODE_REPLY_IO_INDEX_SHIFT) + +#define SET_IO_INDEX(t, i) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_IO_INDEX_MASK) | \ + (((i) << TARGET_MODE_REPLY_IO_INDEX_SHIFT) & \ + TARGET_MODE_REPLY_IO_INDEX_MASK)) + +#define GET_INITIATOR_INDEX(x) (((x) & TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) \ + >> TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) + +#define SET_INITIATOR_INDEX(t, ii) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) | \ + (((ii) << TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) & \ + TARGET_MODE_REPLY_INITIATOR_INDEX_MASK)) + +#define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \ + >> TARGET_MODE_REPLY_ALIAS_SHIFT) + +#define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \ + (((a) << TARGET_MODE_REPLY_ALIAS_SHIFT) & \ + TARGET_MODE_REPLY_ALIAS_MASK)) + +#define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \ + >> TARGET_MODE_REPLY_PORT_SHIFT) + +#define SET_PORT(t, p) ((t) = ((t) & ~TARGET_MODE_REPLY_PORT_MASK) | \ + (((p) << TARGET_MODE_REPLY_PORT_SHIFT) & \ + TARGET_MODE_REPLY_PORT_MASK)) + +/* the following obsolete values are for MPI v1.0 support */ +#define TARGET_MODE_REPLY_0100_MASK_HOST_INDEX (0x000003FF) +#define TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX (0) +#define TARGET_MODE_REPLY_0100_MASK_IOC_INDEX (0x001FF800) +#define TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX (11) +#define TARGET_MODE_REPLY_0100_PORT_MASK (0x00400000) +#define TARGET_MODE_REPLY_0100_PORT_SHIFT (22) +#define TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX (0x1F800000) +#define TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX (23) + +#define GET_HOST_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) \ + >> TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) + +#define SET_HOST_INDEX_0100(t, hi) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) | \ + (((hi) << TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) & \ + TARGET_MODE_REPLY_0100_MASK_HOST_INDEX)) + +#define GET_IOC_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) \ + >> TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) + +#define SET_IOC_INDEX_0100(t, ii) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) | \ + (((ii) << TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) & \ + TARGET_MODE_REPLY_0100_MASK_IOC_INDEX)) + +#define GET_INITIATOR_INDEX_0100(x) \ + (((x) & TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) \ + >> TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) + +#define SET_INITIATOR_INDEX_0100(t, ii) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) | \ + (((ii) << TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) & \ + TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX)) + + +#endif + diff --git a/sys/dev/ic/mpt_mpilib.h.orig b/sys/dev/ic/mpt_mpilib.h.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/ic/mpt_mpilib.h.orig diff --git a/sys/dev/ic/mpt_openbsd.c b/sys/dev/ic/mpt_openbsd.c new file mode 100644 index 00000000000..46d1da4609d --- /dev/null +++ b/sys/dev/ic/mpt_openbsd.c @@ -0,0 +1,1388 @@ +/* $OpenBSD: mpt_openbsd.c,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt_netbsd.c,v 1.7 2003/07/14 15:47:11 lukem Exp $ */ + +/* + * Copyright (c) 2004 Milos Urbanek + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 2000, 2001 by Greg Ansley + * Partially derived from Matt Jacob's ISP driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +/* + * mpt_openbsd.c: + * + * OpenBSD-specific routines for LSI Fusion adapters. Includes some + * bus_dma glue, and SCSI glue. + * + * Adapted from the NetBSD "mpt" driver by Milos Urbanek for + * ZOOM International, s.r.o. + */ + +#include <sys/cdefs.h> +/* __KERNEL_RCSID(0, "$NetBSD: mpt_netbsd.c,v 1.7 2003/07/14 15:47:11 lukem Exp $"); */ + +#include <dev/ic/mpt.h> /* pulls in all headers */ + +#include <machine/stdarg.h> /* for mpt_prt() */ + +static int mpt_poll(mpt_softc_t *, struct scsi_xfer *, int); +static void mpt_timeout(void *); +static void mpt_done(mpt_softc_t *, uint32_t); +static int mpt_run_xfer(mpt_softc_t *, struct scsi_xfer *); +static void mpt_check_xfer_settings(mpt_softc_t *, struct scsi_xfer *, MSG_SCSI_IO_REQUEST *); +static void mpt_set_xfer_mode(mpt_softc_t *, struct scsi_xfer *); +#if 0 +static void mpt_get_xfer_mode(mpt_softc_t *, struct scsipi_periph *); +#endif +static void mpt_ctlop(mpt_softc_t *, void *vmsg, uint32_t); +static void mpt_event_notify_reply(mpt_softc_t *, MSG_EVENT_NOTIFY_REPLY *); + +static int mpt_action(struct scsi_xfer *); +static void mpt_minphys(struct buf *); + +struct cfdriver mpt_cd = { + NULL, "mpt", DV_DULL +}; + +/* the below structure is so we have a default dev struct for our link struct */ +static struct scsi_device mpt_dev = +{ + NULL, /* Use default error handler */ + NULL, /* have a queue, served by this */ + NULL, /* have no async handler */ + NULL, /* Use default 'done' routine */ +}; + +/* + * Complete attachment of hardware, include subdevices. + */ +void +mpt_attach(mpt_softc_t *mpt) +{ + struct scsi_link *lptr = &mpt->sc_link; + int maxq; + + mpt->bus = 0; /* XXX ?? */ + + maxq = (mpt->mpt_global_credits < MPT_MAX_REQUESTS(mpt)) ? + mpt->mpt_global_credits : MPT_MAX_REQUESTS(mpt); + + /* Fill in the scsi_adapter. */ + mpt->sc_adapter.scsi_cmd = mpt_action; + mpt->sc_adapter.scsi_minphys = mpt_minphys; + + /* Fill in the prototype scsi_link */ + lptr->adapter_softc = mpt; + lptr->device = &mpt_dev; + lptr->adapter = &mpt->sc_adapter; + lptr->openings = maxq; + lptr->flags = 0; + lptr->luns = 8; + + if (mpt->is_fc) { + lptr->adapter_buswidth = 256; + lptr->adapter_target = 256; + } else { + lptr->adapter_buswidth = 16; + lptr->adapter_target = mpt->mpt_ini_id; + } + +#ifdef MPT_DEBUG + mpt->verbose = 2; +#endif + (void) config_found(&mpt->mpt_dev, lptr, scsiprint); +} + +int +mpt_dma_mem_alloc(mpt_softc_t *mpt) +{ + bus_dma_segment_t reply_seg, request_seg; + int reply_rseg, request_rseg; + bus_addr_t pptr, end; + caddr_t vptr; + size_t len; + int error, i; + + /* Check if we have already allocated the reply memory. */ + if (mpt->reply != NULL) + return (0); + + /* + * Allocate the request pool. This isn't really DMA'd memory, + * but it's a convenient place to do it. + */ + len = sizeof(request_t) * MPT_MAX_REQUESTS(mpt); + mpt->request_pool = malloc(len, M_DEVBUF, M_WAITOK); + if (mpt->request_pool == NULL) { + printf("%s: unable to allocate request pool\n", + mpt->mpt_dev.dv_xname); + return (ENOMEM); + } + bzero(mpt->request_pool, len); + /* + * Allocate DMA resources for reply buffers. + */ + error = bus_dmamem_alloc(mpt->sc_dmat, PAGE_SIZE, PAGE_SIZE, 0, + &reply_seg, 1, &reply_rseg, 0); + if (error) { + printf("%s: unable to allocate reply area, error = %d\n", + mpt->mpt_dev.dv_xname, error); + goto fail_0; + } + + error = bus_dmamem_map(mpt->sc_dmat, &reply_seg, reply_rseg, PAGE_SIZE, + (caddr_t *) &mpt->reply, BUS_DMA_COHERENT/*XXX*/); + if (error) { + printf("%s: unable to map reply area, error = %d\n", + mpt->mpt_dev.dv_xname, error); + goto fail_1; + } + + error = bus_dmamap_create(mpt->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, + 0, 0, &mpt->reply_dmap); + if (error) { + printf("%s: unable to create reply DMA map, error = %d\n", + mpt->mpt_dev.dv_xname, error); + goto fail_2; + } + + error = bus_dmamap_load(mpt->sc_dmat, mpt->reply_dmap, mpt->reply, + PAGE_SIZE, NULL, 0); + if (error) { + printf("%s: unable to load reply DMA map, error = %d\n", + mpt->mpt_dev.dv_xname, error); + goto fail_3; + } + mpt->reply_phys = mpt->reply_dmap->dm_segs[0].ds_addr; + + /* + * Allocate DMA resources for request buffers. + */ + error = bus_dmamem_alloc(mpt->sc_dmat, MPT_REQ_MEM_SIZE(mpt), + PAGE_SIZE, 0, &request_seg, 1, &request_rseg, 0); + if (error) { + printf("%s: unable to allocate request area, " + "error = %d\n", mpt->mpt_dev.dv_xname, error); + goto fail_4; + } + + error = bus_dmamem_map(mpt->sc_dmat, &request_seg, request_rseg, + MPT_REQ_MEM_SIZE(mpt), (caddr_t *) &mpt->request, 0); + if (error) { + printf("%s: unable to map request area, error = %d\n", + mpt->mpt_dev.dv_xname, error); + goto fail_5; + } + + error = bus_dmamap_create(mpt->sc_dmat, MPT_REQ_MEM_SIZE(mpt), 1, + MPT_REQ_MEM_SIZE(mpt), 0, 0, &mpt->request_dmap); + if (error) { + printf("%s: unable to create request DMA map, " + "error = %d\n", mpt->mpt_dev.dv_xname, error); + goto fail_6; + } + + error = bus_dmamap_load(mpt->sc_dmat, mpt->request_dmap, mpt->request, + MPT_REQ_MEM_SIZE(mpt), NULL, 0); + if (error) { + printf("%s: unable to load request DMA map, error = %d\n", + mpt->mpt_dev.dv_xname, error); + goto fail_7; + } + mpt->request_phys = mpt->request_dmap->dm_segs[0].ds_addr; + + pptr = mpt->request_phys; + vptr = (caddr_t) mpt->request; + end = pptr + MPT_REQ_MEM_SIZE(mpt); + + for (i = 0; pptr < end; i++) { + request_t *req = &mpt->request_pool[i]; + req->index = i; + + /* Store location of Request Data */ + req->req_pbuf = pptr; + req->req_vbuf = vptr; + + pptr += MPT_REQUEST_AREA; + vptr += MPT_REQUEST_AREA; + + req->sense_pbuf = (pptr - MPT_SENSE_SIZE); + req->sense_vbuf = (vptr - MPT_SENSE_SIZE); + + error = bus_dmamap_create(mpt->sc_dmat, MAXPHYS, + MPT_SGL_MAX, MAXPHYS, 0, 0, &req->dmap); + if (error) { + printf("%s: unable to create req %d DMA map, " + "error = %d\n", mpt->mpt_dev.dv_xname, i, error); + goto fail_8; + } + } + + return (0); + + fail_8: + for (--i; i >= 0; i--) { + request_t *req = &mpt->request_pool[i]; + if (req->dmap != NULL) + bus_dmamap_destroy(mpt->sc_dmat, req->dmap); + } + bus_dmamap_unload(mpt->sc_dmat, mpt->request_dmap); + fail_7: + bus_dmamap_destroy(mpt->sc_dmat, mpt->request_dmap); + fail_6: + bus_dmamem_unmap(mpt->sc_dmat, (caddr_t)mpt->request, PAGE_SIZE); + fail_5: + bus_dmamem_free(mpt->sc_dmat, &request_seg, request_rseg); + fail_4: + bus_dmamap_unload(mpt->sc_dmat, mpt->reply_dmap); + fail_3: + bus_dmamap_destroy(mpt->sc_dmat, mpt->reply_dmap); + fail_2: + bus_dmamem_unmap(mpt->sc_dmat, (caddr_t)mpt->reply, PAGE_SIZE); + fail_1: + bus_dmamem_free(mpt->sc_dmat, &reply_seg, reply_rseg); + fail_0: + free(mpt->request_pool, M_DEVBUF); + + mpt->reply = NULL; + mpt->request = NULL; + mpt->request_pool = NULL; + + return (error); +} + +int +mpt_intr(void *arg) +{ + mpt_softc_t *mpt = arg; + int nrepl = 0; + uint32_t reply; + + if ((mpt_read(mpt, MPT_OFFSET_INTR_STATUS) & MPT_INTR_REPLY_READY) == 0) + return (0); + + reply = mpt_pop_reply_queue(mpt); + while (reply != MPT_REPLY_EMPTY) { + nrepl++; + if (mpt->verbose > 1) { + if ((reply & MPT_CONTEXT_REPLY) != 0) { + /* Address reply; IOC has something to say */ + mpt_print_reply(MPT_REPLY_PTOV(mpt, reply)); + } else { + /* Context reply; all went well */ + mpt_prt(mpt, "context %u reply OK", reply); + } + } + mpt_done(mpt, reply); + reply = mpt_pop_reply_queue(mpt); + } + return (nrepl != 0); +} + +void +mpt_prt(mpt_softc_t *mpt, const char *fmt, ...) +{ + va_list ap; + + printf("%s: ", mpt->mpt_dev.dv_xname); + va_start(ap, fmt); + vprintf(fmt, ap); + va_end(ap); + printf("\n"); +} + +static int +mpt_poll(mpt_softc_t *mpt, struct scsi_xfer *xs, int count) +{ + + /* Timeouts are in msec, so we loop in 1000usec cycles */ + while (count) { + mpt_intr(mpt); + if (xs->flags & ITSDONE) { + return (0); + } + delay(1000); /* only happens in boot, so ok */ + count--; + } + return (1); +} + +static void +mpt_timeout(void *arg) +{ + request_t *req = arg; + struct scsi_xfer *xs = req->xfer; + struct scsi_link *linkp = xs->sc_link; + mpt_softc_t *mpt = (void *) linkp->adapter_softc; + uint32_t oseq; + int s; + + mpt_prt(mpt, "command timeout\n"); + sc_print_addr(linkp); + + s = splbio(); + + oseq = req->sequence; + mpt->timeouts++; + if (mpt_intr(mpt)) { + if (req->sequence != oseq) { + mpt_prt(mpt, "recovered from command timeout"); + splx(s); + return; + } + } + mpt_prt(mpt, + "timeout on request index = 0x%x, seq = 0x%08x", + req->index, req->sequence); + mpt_check_doorbell(mpt); + mpt_prt(mpt, "Status 0x%08x, Mask 0x%08x, Doorbell 0x%08x", + mpt_read(mpt, MPT_OFFSET_INTR_STATUS), + mpt_read(mpt, MPT_OFFSET_INTR_MASK), + mpt_read(mpt, MPT_OFFSET_DOORBELL)); + mpt_prt(mpt, "request state: %s", mpt_req_state(req->debug)); + if (mpt->verbose > 1) + mpt_print_scsi_io_request((MSG_SCSI_IO_REQUEST *)req->req_vbuf); + + /* XXX WHAT IF THE IOC IS STILL USING IT?? */ + /* XXX MU we should delay the call to mpt_free_request */ + req->xfer = NULL; + mpt_free_request(mpt, req); + + xs->error = XS_TIMEOUT; + xs->flags |= ITSDONE; + scsi_done(xs); + + splx(s); +} + +static void +mpt_done(mpt_softc_t *mpt, uint32_t reply) +{ + struct scsi_xfer *xs = NULL; + struct scsi_link *linkp; + int index; + request_t *req; + MSG_REQUEST_HEADER *mpt_req; + MSG_SCSI_IO_REPLY *mpt_reply; + + + if ((reply & MPT_CONTEXT_REPLY) == 0) { + /* context reply (ok) */ + mpt_reply = NULL; + index = reply & MPT_CONTEXT_MASK; + } else { + /* address reply (error) */ + + /* XXX BUS_DMASYNC_POSTREAD XXX */ + mpt_reply = MPT_REPLY_PTOV(mpt, reply); + if (mpt->verbose > 1) { + uint32_t *pReply = (uint32_t *) mpt_reply; + + mpt_prt(mpt, "Address Reply (index %u):", + mpt_reply->MsgContext & 0xffff); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReply[0], pReply[1], pReply[2], pReply[3]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReply[4], pReply[5], pReply[6], pReply[7]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReply[8], pReply[9], pReply[10], pReply[11]); + } + index = mpt_reply->MsgContext; + } + + /* + * Address reply with MessageContext high bit set. + * This is most likely a notify message, so we try + * to process it, then free it. + */ + if ((index & 0x80000000) != 0) { + if (mpt_reply != NULL) + mpt_ctlop(mpt, mpt_reply, reply); + else + mpt_prt(mpt, "mpt_done: index 0x%x, NULL reply", index); + return; + } + + /* Did we end up with a valid index into the table? */ + if (index < 0 || index >= MPT_MAX_REQUESTS(mpt)) { + mpt_prt(mpt, "mpt_done: invalid index (0x%x) in reply", index); + return; + } + + req = &mpt->request_pool[index]; + + /* Make sure memory hasn't been trashed. */ + if (req->index != index) { + mpt_prt(mpt, "mpt_done: corrupted request_t (0x%x)", index); + return; + } + + MPT_SYNC_REQ(mpt, req, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); + mpt_req = req->req_vbuf; + + /* Short cut for task management replies; nothing more for us to do. */ + if (mpt_req->Function == MPI_FUNCTION_SCSI_TASK_MGMT) { + if (mpt->verbose > 1) + mpt_prt(mpt, "mpt_done: TASK MGMT"); + goto done; + } + + if (mpt_req->Function == MPI_FUNCTION_PORT_ENABLE) + goto done; + + /* + * At this point, it had better be a SCSI I/O command, but don't + * crash if it isn't. + */ + if (mpt_req->Function != MPI_FUNCTION_SCSI_IO_REQUEST) { + if (mpt->verbose > 1) + mpt_prt(mpt, "mpt_done: unknown Function 0x%x (0x%x)", + mpt_req->Function, index); + goto done; + } + + /* Recover scsi_xfer from the request structure. */ + xs = req->xfer; + + /* Can't have a SCSI command without a scsi_xfer. */ + if (xs == NULL) { + mpt_prt(mpt, + "mpt_done: no scsi_xfer, index = 0x%x, seq = 0x%08x", + req->index, req->sequence); + mpt_prt(mpt, "request state: %s", mpt_req_state(req->debug)); + mpt_prt(mpt, "mpt_request:"); + mpt_print_scsi_io_request((MSG_SCSI_IO_REQUEST *)req->req_vbuf); + + if (mpt_reply != NULL) { + mpt_prt(mpt, "mpt_reply:"); + mpt_print_reply(mpt_reply); + } else { + mpt_prt(mpt, "context reply: 0x%08x", reply); + } + goto done; + } + + timeout_del(&xs->stimeout); + + linkp = xs->sc_link; + + /* + * If we were a data transfer, unload the map that described + * the data buffer. + */ + if (xs->datalen != 0) { + bus_dmamap_sync(mpt->sc_dmat, req->dmap, 0, + req->dmap->dm_mapsize, + (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD + : BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(mpt->sc_dmat, req->dmap); + } + + if (mpt_reply == NULL) { + /* + * Context reply; report that the command was + * successful! + * + * Also report the xfer mode, if necessary. + */ +#if 0 /*XXX report xfer mode not impl */ + if (mpt->mpt_report_xfer_mode != 0) { + if ((mpt->mpt_report_xfer_mode & + (1 << periph->periph_target)) != 0) + mpt_get_xfer_mode(mpt, periph); + } +#endif + xs->error = XS_NOERROR; + xs->status = SCSI_OK; + xs->resid = 0; + mpt_free_request(mpt, req); + xs->flags |= ITSDONE; + scsi_done(xs); + return; + } + + xs->status = mpt_reply->SCSIStatus; + switch (mpt_reply->IOCStatus) { + case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: + xs->error = XS_DRIVER_STUFFUP; + break; + + case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: + /* + * Yikes! Tagged queue full comes through this path! + * + * So we'll change it to a status error and anything + * that returns status should probably be a status + * error as well. + */ + xs->resid = xs->datalen - mpt_reply->TransferCount; + if (mpt_reply->SCSIState & + MPI_SCSI_STATE_NO_SCSI_STATUS) { + xs->error = XS_DRIVER_STUFFUP; + break; + } + /* FALLTHROUGH */ + case MPI_IOCSTATUS_SUCCESS: + case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: + switch (xs->status) { + case SCSI_OK: +#if 0 /* XXX xfer mode */ + /* Report the xfer mode, if necessary. */ + if ((mpt->mpt_report_xfer_mode & + (1 << periph->periph_target)) != 0) + mpt_get_xfer_mode(mpt, periph); +#endif + xs->resid = 0; + break; + + case SCSI_CHECK: + xs->error = XS_SENSE; + break; + + case SCSI_BUSY: + xs->error = XS_BUSY; + break; + + case SCSI_QUEUE_FULL: + xs->error = XS_TIMEOUT; + xs->retries++; + break; + default: + sc_print_addr(linkp); + printf("invalid status code %d\n", xs->status); + xs->error = XS_DRIVER_STUFFUP; + break; + } + break; + +#if 0 /* XS_RESOURCE_SHORTAGE not impl */ + case MPI_IOCSTATUS_BUSY: + case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: + xs->error = XS_RESOURCE_SHORTAGE; + break; +#endif + case MPI_IOCSTATUS_SCSI_INVALID_BUS: + case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: + case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: + xs->error = XS_SELTIMEOUT; + break; + + case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: + xs->error = XS_DRIVER_STUFFUP; + break; + + case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: + /* XXX What should we do here? */ + break; + + case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: + /* XXX */ + xs->error = XS_DRIVER_STUFFUP; + break; + + case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: + /* XXX */ + xs->error = XS_DRIVER_STUFFUP; + break; + + case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: + /* XXX This is a bus-reset */ + xs->error = XS_DRIVER_STUFFUP; + break; + + default: + /* XXX unrecognized HBA error */ + xs->error = XS_DRIVER_STUFFUP; + break; + } + + if (mpt_reply->SCSIState & MPI_SCSI_STATE_AUTOSENSE_VALID) { + memcpy(&xs->sense, req->sense_vbuf, + sizeof(xs->sense)); + } else if (mpt_reply->SCSIState & MPI_SCSI_STATE_AUTOSENSE_FAILED) { + /* + * This will cause the scsi layer to issue + * a REQUEST SENSE. + */ + if (xs->status == SCSI_CHECK) + xs->error = XS_BUSY; + } + + done: + /* If IOC done with this requeset, free it up. */ + if (mpt_reply == NULL || (mpt_reply->MsgFlags & 0x80) == 0) + mpt_free_request(mpt, req); + + /* If address reply, give the buffer back to the IOC. */ + if (mpt_reply != NULL) + mpt_free_reply(mpt, (reply << 1)); + + if (xs != NULL) { + xs->flags |= ITSDONE; + scsi_done(xs); + } +} + +static int +mpt_run_xfer(mpt_softc_t *mpt, struct scsi_xfer *xs) +{ + struct scsi_link *linkp = xs->sc_link; + request_t *req; + MSG_SCSI_IO_REQUEST *mpt_req; + int error, s; + + s = splbio(); + req = mpt_get_request(mpt); + if (req == NULL) { + /* This should happen very infrequently. */ + xs->error = XS_DRIVER_STUFFUP; + /* + xs->error = XS_RESOURCE_SHORTAGE; + */ + xs->flags |= ITSDONE; + scsi_done(xs); + splx(s); + return (COMPLETE); + } + splx(s); + + /* Link the req and the scsi_xfer. */ + req->xfer = xs; + + /* Now we build the command for the IOC */ + mpt_req = req->req_vbuf; + bzero(mpt_req, sizeof(*mpt_req)); + + mpt_req->Function = MPI_FUNCTION_SCSI_IO_REQUEST; + mpt_req->Bus = mpt->bus; + + mpt_req->SenseBufferLength = + (sizeof(xs->sense) < MPT_SENSE_SIZE) ? + sizeof(xs->sense) : MPT_SENSE_SIZE; + + /* + * We use the message context to find the request structure when + * we get the command completion interrupt from the IOC. + */ + mpt_req->MsgContext = req->index; + + /* Which physical device to do the I/O on. */ + mpt_req->TargetID = linkp->target; + mpt_req->LUN[1] = linkp->lun; + + /* Set the direction of the transfer. */ + if (xs->flags & SCSI_DATA_IN) + mpt_req->Control = MPI_SCSIIO_CONTROL_READ; + else if (xs->flags & SCSI_DATA_OUT) + mpt_req->Control = MPI_SCSIIO_CONTROL_WRITE; + else + mpt_req->Control = MPI_SCSIIO_CONTROL_NODATATRANSFER; + + if (cold && !(xs->sc_link->quirks & SDEV_NOWIDE)) + mpt_set_xfer_mode(mpt, xs); + + mpt_check_xfer_settings(mpt, xs, mpt_req); + + /* Copy the SCSI command block into place. */ + memcpy(mpt_req->CDB, xs->cmd, xs->cmdlen); + + mpt_req->CDBLength = xs->cmdlen; + mpt_req->DataLength = xs->datalen; + mpt_req->SenseBufferLowAddr = req->sense_pbuf; + + /* + * Map the DMA transfer. + */ + if (xs->datalen) { + SGE_SIMPLE32 *se; + + error = bus_dmamap_load(mpt->sc_dmat, req->dmap, xs->data, + xs->datalen, NULL, + ((xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT + : BUS_DMA_WAITOK) | + BUS_DMA_STREAMING | + ((xs->flags & SCSI_DATA_IN) ? BUS_DMA_READ + : BUS_DMA_WRITE)); + switch (error) { + case 0: + break; + + case ENOMEM: + case EAGAIN: + xs->error = XS_DRIVER_STUFFUP; + /* xs->error = XS_RESOURCE_SHORTAGE; */ + goto out_bad; + default: + xs->error = XS_DRIVER_STUFFUP; + mpt_prt(mpt, "error %d loading DMA map", error); + out_bad: + s = splbio(); + mpt_free_request(mpt, req); + xs->flags |= ITSDONE; + scsi_done(xs); + splx(s); + return (TRY_AGAIN_LATER); + } + + if (req->dmap->dm_nsegs > MPT_NSGL_FIRST(mpt)) { + int seg, i, nleft = req->dmap->dm_nsegs; + uint32_t flags; + SGE_CHAIN32 *ce; + + seg = 0; + + mpt_req->DataLength = xs->datalen; + flags = MPI_SGE_FLAGS_SIMPLE_ELEMENT; + if (xs->flags & SCSI_DATA_OUT) + flags |= MPI_SGE_FLAGS_HOST_TO_IOC; + + se = (SGE_SIMPLE32 *) &mpt_req->SGL; + for (i = 0; i < MPT_NSGL_FIRST(mpt) - 1; + i++, se++, seg++) { + uint32_t tf; + + bzero(se, sizeof(*se)); + se->Address = req->dmap->dm_segs[seg].ds_addr; + MPI_pSGE_SET_LENGTH(se, + req->dmap->dm_segs[seg].ds_len); + tf = flags; + if (i == MPT_NSGL_FIRST(mpt) - 2) + tf |= MPI_SGE_FLAGS_LAST_ELEMENT; + MPI_pSGE_SET_FLAGS(se, tf); + nleft--; + } + + /* + * Tell the IOC where to find the first chain element. + */ + mpt_req->ChainOffset = + ((char *)se - (char *)mpt_req) >> 2; + + /* + * Until we're finished with all segments... + */ + while (nleft) { + int ntodo; + + /* + * Construct the chain element that points to + * the next segment. + */ + ce = (SGE_CHAIN32 *) se++; + if (nleft > MPT_NSGL(mpt)) { + ntodo = MPT_NSGL(mpt) - 1; + ce->NextChainOffset = (MPT_RQSL(mpt) - + sizeof(SGE_SIMPLE32)) >> 2; + } else { + ntodo = nleft; + ce->NextChainOffset = 0; + } + ce->Length = ntodo * sizeof(SGE_SIMPLE32); + ce->Address = req->req_pbuf + + ((char *)se - (char *)mpt_req); + ce->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT; + for (i = 0; i < ntodo; i++, se++, seg++) { + uint32_t tf; + + bzero(se, sizeof(*se)); + se->Address = + req->dmap->dm_segs[seg].ds_addr; + MPI_pSGE_SET_LENGTH(se, + req->dmap->dm_segs[seg].ds_len); + tf = flags; + if (i == ntodo - 1) { + tf |= + MPI_SGE_FLAGS_LAST_ELEMENT; + if (ce->NextChainOffset == 0) { + tf |= + MPI_SGE_FLAGS_END_OF_LIST | + MPI_SGE_FLAGS_END_OF_BUFFER; + } + } + MPI_pSGE_SET_FLAGS(se, tf); + nleft--; + } + } + bus_dmamap_sync(mpt->sc_dmat, req->dmap, 0, + req->dmap->dm_mapsize, + (xs->flags & SCSI_DATA_IN) ? + BUS_DMASYNC_PREREAD + : BUS_DMASYNC_PREWRITE); + } else { + int i; + uint32_t flags; + + mpt_req->DataLength = xs->datalen; + flags = MPI_SGE_FLAGS_SIMPLE_ELEMENT; + if (xs->flags & SCSI_DATA_OUT) + flags |= MPI_SGE_FLAGS_HOST_TO_IOC; + + /* Copy the segments into our SG list. */ + se = (SGE_SIMPLE32 *) &mpt_req->SGL; + for (i = 0; i < req->dmap->dm_nsegs; + i++, se++) { + uint32_t tf; + + bzero(se, sizeof(*se)); + se->Address = req->dmap->dm_segs[i].ds_addr; + MPI_pSGE_SET_LENGTH(se, + req->dmap->dm_segs[i].ds_len); + tf = flags; + if (i == req->dmap->dm_nsegs - 1) { + tf |= + MPI_SGE_FLAGS_LAST_ELEMENT | + MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_END_OF_LIST; + } + MPI_pSGE_SET_FLAGS(se, tf); + } + bus_dmamap_sync(mpt->sc_dmat, req->dmap, 0, + req->dmap->dm_mapsize, + (xs->flags & SCSI_DATA_IN) ? + BUS_DMASYNC_PREREAD + : BUS_DMASYNC_PREWRITE); + } + } else { + /* + * No data to transfer; just make a single simple SGL + * with zero length. + */ + SGE_SIMPLE32 *se = (SGE_SIMPLE32 *) &mpt_req->SGL; + bzero(se, sizeof(*se)); + MPI_pSGE_SET_FLAGS(se, + (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_SIMPLE_ELEMENT | MPI_SGE_FLAGS_END_OF_LIST)); + } + + if (mpt->verbose > 1) + mpt_print_scsi_io_request(mpt_req); + + s = splbio(); + + /* Always reset xs->stimeout, lest we timeout_del() with trash */ + timeout_set(&xs->stimeout, mpt_timeout, req); + + if ((xs->flags & SCSI_POLL) == 0) + timeout_add(&xs->stimeout, mstohz(xs->timeout)); + mpt_send_cmd(mpt, req); + splx(s); + + if ((xs->flags & SCSI_POLL) == 0) { + return (SUCCESSFULLY_QUEUED); + } + /* + * If we can't use interrupts, poll on completion. + */ + if (mpt_poll(mpt, xs, xs->timeout)) { + mpt_timeout(req); + /* XXX scsi_done called + return (TRY_AGAIN_LATER); + */ + return (COMPLETE); + } + + return (COMPLETE); +} + +void +mpt_set_xfer_mode(mpt_softc_t *mpt, struct scsi_xfer *xs) +{ + fCONFIG_PAGE_SCSI_DEVICE_1 tmp; + + if (mpt->is_fc) { + /* + * SCSI transport settings don't make any sense for + * Fibre Channel; silently ignore the request. + */ + return; + } + + /* + * Always allow disconnect; we don't have a way to disable + * it right now, in any case. + */ + mpt->mpt_disc_enable |= (1 << xs->sc_link->target); + + if (xs->sc_link->quirks & SDEV_NOTAGS) + mpt->mpt_tag_enable &= ~(1 << xs->sc_link->target); + else + mpt->mpt_tag_enable |= (1 << xs->sc_link->target); + + tmp = mpt->mpt_dev_page1[xs->sc_link->target]; + + /* + * Set the wide/narrow parameter for the target. + */ + if (xs->sc_link->quirks & SDEV_NOWIDE) + tmp.RequestedParameters &= ~MPI_SCSIDEVPAGE1_RP_WIDE; + else { + tmp.RequestedParameters |= MPI_SCSIDEVPAGE1_RP_WIDE; + } + /* + * Set the synchronous parameters for the target. + * + * XXX If we request sync transfers, we just go ahead and + * XXX request the maximum available. We need finer control + * XXX in order to implement Domain Validation. + */ + tmp.RequestedParameters &= ~(MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK | + MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK | + MPI_SCSIDEVPAGE1_RP_DT | MPI_SCSIDEVPAGE1_RP_QAS | + MPI_SCSIDEVPAGE1_RP_IU); + if (!(xs->sc_link->quirks & SDEV_NOSYNC)) { + int factor, offset, np; + + factor = (mpt->mpt_port_page0.Capabilities >> 8) & 0xff; + offset = (mpt->mpt_port_page0.Capabilities >> 16) & 0xff; + np = 0; + if (factor < 0x9) { + /* Ultra320 */ + np |= MPI_SCSIDEVPAGE1_RP_QAS | MPI_SCSIDEVPAGE1_RP_IU; + } + if (factor < 0xa) { + /* at least Ultra160 */ + np |= MPI_SCSIDEVPAGE1_RP_DT; + } + np |= (factor << 8) | (offset << 16); + tmp.RequestedParameters |= np; + } + + if (mpt_write_cfg_page(mpt, xs->sc_link->target, &tmp.Header)) { + mpt_prt(mpt, "unable to write Device Page 1"); + return; + } + + if (mpt_read_cfg_page(mpt, xs->sc_link->target, &tmp.Header)) { + mpt_prt(mpt, "unable to read back Device Page 1"); + return; + } + + mpt->mpt_dev_page1[xs->sc_link->target] = tmp; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Page 1: RequestedParameters %x Config %x", + xs->sc_link->target, + mpt->mpt_dev_page1[xs->sc_link->target].RequestedParameters, + mpt->mpt_dev_page1[xs->sc_link->target].Configuration); + } + + return; +} +#if 0 +static void +mpt_get_xfer_mode(mpt_softc_t *mpt, struct scsipi_periph *periph) +{ + fCONFIG_PAGE_SCSI_DEVICE_0 tmp; + struct scsipi_xfer_mode xm; + int period, offset; + + tmp = mpt->mpt_dev_page0[periph->periph_target]; + if (mpt_read_cfg_page(mpt, periph->periph_target, &tmp.Header)) { + mpt_prt(mpt, "unable to read Device Page 0"); + return; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 0: NParms %x Information %x", + periph->periph_target, + tmp.NegotiatedParameters, tmp.Information); + } + + xm.xm_target = periph->periph_target; + xm.xm_mode = 0; + + if (tmp.NegotiatedParameters & MPI_SCSIDEVPAGE0_NP_WIDE) + xm.xm_mode |= PERIPH_CAP_WIDE16; + + period = (tmp.NegotiatedParameters >> 8) & 0xff; + offset = (tmp.NegotiatedParameters >> 16) & 0xff; + if (offset) { + xm.xm_period = period; + xm.xm_offset = offset; + xm.xm_mode |= PERIPH_CAP_SYNC; + } + + /* + * Tagged queueing is all controlled by us; there is no + * other setting to query. + */ + if (mpt->mpt_tag_enable & (1 << periph->periph_target)) + xm.xm_mode |= PERIPH_CAP_TQING; + + /* + * We're going to deliver the async event, so clear the marker. + */ + mpt->mpt_report_xfer_mode &= ~(1 << periph->periph_target); + + scsipi_async_event(&mpt->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); +} +#endif /* scsipi_xfer_mode */ + +static void +mpt_ctlop(mpt_softc_t *mpt, void *vmsg, uint32_t reply) +{ + MSG_DEFAULT_REPLY *dmsg = vmsg; + + switch (dmsg->Function) { + case MPI_FUNCTION_EVENT_NOTIFICATION: + mpt_event_notify_reply(mpt, vmsg); + mpt_free_reply(mpt, (reply << 1)); + break; + + case MPI_FUNCTION_EVENT_ACK: + mpt_free_reply(mpt, (reply << 1)); + break; + + case MPI_FUNCTION_PORT_ENABLE: + { + MSG_PORT_ENABLE_REPLY *msg = vmsg; + int index = msg->MsgContext & ~0x80000000; + if (mpt->verbose > 1) + mpt_prt(mpt, "enable port reply index %d", index); + if (index >= 0 && index < MPT_MAX_REQUESTS(mpt)) { + request_t *req = &mpt->request_pool[index]; + req->debug = REQ_DONE; + } + mpt_free_reply(mpt, (reply << 1)); + break; + } + + case MPI_FUNCTION_CONFIG: + { + MSG_CONFIG_REPLY *msg = vmsg; + int index = msg->MsgContext & ~0x80000000; + if (index >= 0 && index < MPT_MAX_REQUESTS(mpt)) { + request_t *req = &mpt->request_pool[index]; + req->debug = REQ_DONE; + req->sequence = reply; + } else + mpt_free_reply(mpt, (reply << 1)); + break; + } + + default: + mpt_prt(mpt, "unknown ctlop: 0x%x", dmsg->Function); + } +} + +static void +mpt_event_notify_reply(mpt_softc_t *mpt, MSG_EVENT_NOTIFY_REPLY *msg) +{ + + switch (msg->Event) { + case MPI_EVENT_LOG_DATA: + { + int i; + + /* Some error occurrerd that the Fusion wants logged. */ + mpt_prt(mpt, "EvtLogData: IOCLogInfo: 0x%08x", msg->IOCLogInfo); + mpt_prt(mpt, "EvtLogData: Event Data:"); + for (i = 0; i < msg->EventDataLength; i++) { + if ((i % 4) == 0) + printf("%s:\t", mpt->mpt_dev.dv_xname); + printf("0x%08x%c", msg->Data[i], + ((i % 4) == 3) ? '\n' : ' '); + } + if ((i % 4) != 0) + printf("\n"); + break; + } + + case MPI_EVENT_UNIT_ATTENTION: + mpt_prt(mpt, "Unit Attn: Bus 0x%02x Target 0x%02x", + (msg->Data[0] >> 8) & 0xff, msg->Data[0] & 0xff); + break; + + case MPI_EVENT_IOC_BUS_RESET: + /* We generated a bus reset. */ + mpt_prt(mpt, "IOC Bus Reset Port %d", + (msg->Data[0] >> 8) & 0xff); + break; + + case MPI_EVENT_EXT_BUS_RESET: + /* Someone else generated a bus reset. */ + mpt_prt(mpt, "External Bus Reset"); + /* + * These replies don't return EventData like the MPI + * spec says they do. + */ + /* XXX Send an async event? */ + break; + + case MPI_EVENT_RESCAN: + /* + * In general, thise means a device has been added + * to the loop. + */ + mpt_prt(mpt, "Rescan Port %d", (msg->Data[0] >> 8) & 0xff); + /* XXX Send an async event? */ + break; + + case MPI_EVENT_LINK_STATUS_CHANGE: + mpt_prt(mpt, "Port %d: Link state %s", + (msg->Data[1] >> 8) & 0xff, + (msg->Data[0] & 0xff) == 0 ? "Failed" : "Active"); + break; + + case MPI_EVENT_LOOP_STATE_CHANGE: + switch ((msg->Data[0] >> 16) & 0xff) { + case 0x01: + mpt_prt(mpt, + "Port %d: FC Link Event: LIP(%02x,%02x) " + "(Loop Initialization)", + (msg->Data[1] >> 8) & 0xff, + (msg->Data[0] >> 8) & 0xff, + (msg->Data[0] ) & 0xff); + switch ((msg->Data[0] >> 8) & 0xff) { + case 0xf7: + if ((msg->Data[0] & 0xff) == 0xf7) + mpt_prt(mpt, "\tDevice needs AL_PA"); + else + mpt_prt(mpt, "\tDevice %02x doesn't " + "like FC performance", + msg->Data[0] & 0xff); + break; + + case 0xf8: + if ((msg->Data[0] & 0xff) == 0xf7) + mpt_prt(mpt, "\tDevice detected loop " + "failure before acquiring AL_PA"); + else + mpt_prt(mpt, "\tDevice %02x detected " + "loop failure", + msg->Data[0] & 0xff); + break; + + default: + mpt_prt(mpt, "\tDevice %02x requests that " + "device %02x reset itself", + msg->Data[0] & 0xff, + (msg->Data[0] >> 8) & 0xff); + break; + } + break; + + case 0x02: + mpt_prt(mpt, "Port %d: FC Link Event: LPE(%02x,%02x) " + "(Loop Port Enable)", + (msg->Data[1] >> 8) & 0xff, + (msg->Data[0] >> 8) & 0xff, + (msg->Data[0] ) & 0xff); + break; + + case 0x03: + mpt_prt(mpt, "Port %d: FC Link Event: LPB(%02x,%02x) " + "(Loop Port Bypass)", + (msg->Data[1] >> 8) & 0xff, + (msg->Data[0] >> 8) & 0xff, + (msg->Data[0] ) & 0xff); + break; + + default: + mpt_prt(mpt, "Port %d: FC Link Event: " + "Unknown event (%02x %02x %02x)", + (msg->Data[1] >> 8) & 0xff, + (msg->Data[0] >> 16) & 0xff, + (msg->Data[0] >> 8) & 0xff, + (msg->Data[0] ) & 0xff); + break; + } + break; + + case MPI_EVENT_LOGOUT: + mpt_prt(mpt, "Port %d: FC Logout: N_PortID: %02x", + (msg->Data[1] >> 8) & 0xff, msg->Data[0]); + break; + + case MPI_EVENT_EVENT_CHANGE: + /* + * This is just an acknowledgement of our + * mpt_send_event_request(). + */ + break; + + default: + mpt_prt(mpt, "Unknown async event: 0x%x", msg->Event); + break; + } + + if (msg->AckRequired) { + MSG_EVENT_ACK *ackp; + request_t *req; + + if ((req = mpt_get_request(mpt)) == NULL) { + /* XXX XXX XXX XXXJRT */ + panic("mpt_event_notify_reply: unable to allocate " + "request structure"); + } + + ackp = (MSG_EVENT_ACK *) req->req_vbuf; + bzero(ackp, sizeof(*ackp)); + ackp->Function = MPI_FUNCTION_EVENT_ACK; + ackp->Event = msg->Event; + ackp->EventContext = msg->EventContext; + ackp->MsgContext = req->index | 0x80000000; + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + } +} + +void +mpt_check_xfer_settings(mpt_softc_t *mpt, struct scsi_xfer *xs, MSG_SCSI_IO_REQUEST *mpt_req) +{ + if (mpt->is_fc) { + /* + * SCSI transport settings don't make any sense for + * Fibre Channel; silently ignore the request. + */ + return; + } +#if 0 + /* + * XXX never do these commands with tags. Should really be + * in a higher layer. + */ + if (xs->cmd->opcode == INQUIRY || + xs->cmd->opcode == TEST_UNIT_READY || + xs->cmd->opcode == REQUEST_SENSE) + return; +#endif + /* Set the queue behavior. */ + if (mpt->is_fc || (mpt->mpt_tag_enable & (1 << xs->sc_link->target))) { + mpt_req->Control |= MPI_SCSIIO_CONTROL_SIMPLEQ; + } else { + mpt_req->Control |= MPI_SCSIIO_CONTROL_UNTAGGED; + mpt_req->Control |= MPI_SCSIIO_CONTROL_NO_DISCONNECT; + } +#if 0 + if (mpt->is_fc == 0 && (mpt->mpt_disc_enable & + (1 << linkp->target)) == 0) + mpt_req->Control |= MPI_SCSIIO_CONTROL_NO_DISCONNECT; +#endif + return; +} + +/* XXXJRT mpt_bus_reset() */ + +/***************************************************************************** + * SCSI interface routines + *****************************************************************************/ + +static int +mpt_action(struct scsi_xfer *xfer) +{ + mpt_softc_t *mpt = (void *) xfer->sc_link->adapter_softc; + int ret; + + ret = mpt_run_xfer(mpt, xfer); + return ret; +#if 0 + switch (req) { + case ADAPTER_REQ_RUN_XFER: + mpt_run_xfer(mpt, (struct scsipi_xfer *) arg); + return; + + case ADAPTER_REQ_GROW_RESOURCES: + /* Not supported. */ + return; + + case ADAPTER_REQ_SET_XFER_MODE: + mpt_set_xfer_mode(mpt, (struct scsipi_xfer_mode *) arg); + return; + } +#endif +} + +static void +mpt_minphys(struct buf *bp) +{ + +/* + * Subtract one from the SGL limit, since we need an extra one to handle + * an non-page-aligned transfer. + */ +#define MPT_MAX_XFER ((MPT_SGL_MAX - 1) * PAGE_SIZE) + + if (bp->b_bcount > MPT_MAX_XFER) + bp->b_bcount = MPT_MAX_XFER; + minphys(bp); +} diff --git a/sys/dev/ic/mpt_openbsd.c.orig b/sys/dev/ic/mpt_openbsd.c.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/ic/mpt_openbsd.c.orig diff --git a/sys/dev/ic/mpt_openbsd.h b/sys/dev/ic/mpt_openbsd.h new file mode 100644 index 00000000000..44faea16ae5 --- /dev/null +++ b/sys/dev/ic/mpt_openbsd.h @@ -0,0 +1,298 @@ +/* $OpenBSD: mpt_openbsd.h,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt_netbsd.h,v 1.2 2003/04/16 23:02:14 thorpej Exp $ */ + +/* + * Copyright (c) 2004 Milos Urbanek + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + */ +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 2000, 2001 by Greg Ansley, Adam Prewett + * + * Partially derived from Matt Jacobs ISP driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +/* + * mpt_openbsd.h: + * + * OpenBSD-specific definitions for LSI Fusion adapters. + * + * Adapted from the NetBSD "mpt" driver by Milos Urbanek for + * ZOOM International, s.r.o. + */ + +#ifndef _DEV_IC_MPT_NETBSD_H_ +#define _DEV_IC_MPT_NETBSD_H_ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/device.h> +#include <sys/kernel.h> +#include <sys/timeout.h> +#include <sys/errno.h> +#include <sys/buf.h> +#include <sys/queue.h> + +#include <uvm/uvm_extern.h> + +#include <machine/bus.h> +#include <machine/intr.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> + +#include <dev/ic/mpt_mpilib.h> + +/* + * macro to convert from milliseconds to hz without integer overflow + * Default version using only 32bits arithmetics. + * 64bit port can define 64bit version in their <machine/param.h> + * 0x20000 is safe for hz < 20000 + */ +#ifndef mstohz +#define mstohz(ms) \ + (((ms +0u) / 1000u) * hz) +#endif + +/* Max MPT Reply we are willing to accept (must be a power of 2). */ +#define MPT_REPLY_SIZE 128 + +#define MPT_MAX_REQUESTS(mpt) ((mpt)->is_fc ? 1024 : 256) +#define MPT_REQUEST_AREA 512 +#define MPT_SENSE_SIZE 32 /* included in MPT_REQUEST_AREA */ +#define MPT_REQ_MEM_SIZE(mpt) (MPT_MAX_REQUESTS(mpt) * MPT_REQUEST_AREA) + +/* + * We cannot tell prior to getting IOC facts how big the IOC's request + * area is. Because of this we cannot tell at compile time how many + * simple SG elements we can fit within an IOC request prior to having + * to put in a chain element. + * + * Experimentally we know that the Ultra4 parts have a 96 byte request + * element size and the Fibre Channel units have a 144 byte request + * element size. Therefore, if we have 512-32 (== 480) bytes of request + * area to play with, we have room for between 3 and 5 request sized + * regions- the first of which is the command plus a simple SG list, + * the rest of which are chained continuation SG lists. Given that the + * normal request we use is 48 bytes w/o the first SG element, we can + * assume we have 480-48 == 432 bytes to have simple SG elements and/or + * chain elements. If we assume 32 bit addressing, this works out to + * 54 SG or chain elements. If we assume 5 chain elements, then we have + * a maximum of 49 seperate actual SG segments. + */ +#define MPT_SGL_MAX 49 + +#define MPT_RQSL(mpt) ((mpt)->request_frame_size << 2) +#define MPT_NSGL(mpt) (MPT_RQSL(mpt) / sizeof(SGE_SIMPLE32)) + +#define MPT_NSGL_FIRST(mpt) \ + ((((mpt)->request_frame_size << 2) - \ + sizeof(MSG_SCSI_IO_REQUEST) - \ + sizeof(SGE_IO_UNION)) / sizeof(SGE_SIMPLE32)) + +/* + * Convert a physical address returned from IOC to a virtual address + * needed to access the data. + */ +#define MPT_REPLY_PTOV(m, x) \ + ((void *)(&(m)->reply[(((x) << 1) - (m)->reply_phys)])) + +enum mpt_req_state { + REQ_FREE, + REQ_IN_PROGRESS, + REQ_TIMEOUT, + REQ_ON_CHIP, + REQ_DONE +}; +typedef struct req_entry { + uint16_t index; /* index of this entry */ + struct scsi_xfer *xfer; /* scsipi xfer request */ + void *req_vbuf; /* virtual address of entry */ + void *sense_vbuf; /* virtual address of sense data */ + bus_addr_t req_pbuf; /* physical address of entry */ + bus_addr_t sense_pbuf; /* physical address of sense data */ + bus_dmamap_t dmap; /* DMA map for data buffer */ + SLIST_ENTRY(req_entry) link; /* pointer to next in list */ + enum mpt_req_state debug; /* debugging */ + uint32_t sequence; /* sequence number */ +} request_t; + +typedef struct mpt_softc { + struct device mpt_dev; /* base device glue */ + + /* Locking context */ + int mpt_splsaved; + uint32_t mpt_islocked; + + int verbose : 3, + mpt_locksetup : 1, + is_fc : 1, + bus : 1, + : 26; + + /* IOC facts */ + uint16_t mpt_global_credits; + uint16_t request_frame_size; + uint8_t mpt_max_devices; + uint8_t mpt_max_buses; + + /* Port facts */ + uint16_t mpt_ini_id; + + /* Device configuration information */ + union { + struct mpt_spi_cfg { + fCONFIG_PAGE_SCSI_PORT_0 _port_page0; + fCONFIG_PAGE_SCSI_PORT_1 _port_page1; + fCONFIG_PAGE_SCSI_PORT_2 _port_page2; + fCONFIG_PAGE_SCSI_DEVICE_0 _dev_page0[16]; + fCONFIG_PAGE_SCSI_DEVICE_1 _dev_page1[16]; + uint16_t _tag_enable; + uint16_t _disc_enable; + uint16_t _update_params0; + uint16_t _update_params1; + uint16_t _report_xfer_mode; + } spi; +#define mpt_port_page0 cfg.spi._port_page0 +#define mpt_port_page1 cfg.spi._port_page1 +#define mpt_port_page2 cfg.spi._port_page2 +#define mpt_dev_page0 cfg.spi._dev_page0 +#define mpt_dev_page1 cfg.spi._dev_page1 +#define mpt_tag_enable cfg.spi._tag_enable +#define mpt_disc_enable cfg.spi._disc_enable +#define mpt_update_params0 cfg.spi._update_params0 +#define mpt_update_params1 cfg.spi._update_params1 +#define mpt_report_xfer_mode cfg.spi._report_xfer_mode + + struct mpt_fc_cfg { + uint8_t nada; + } fc; + } cfg; + + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + bus_dma_tag_t sc_dmat; + + /* Reply memory */ + bus_dmamap_t reply_dmap; + char *reply; + bus_addr_t reply_phys; + + /* Request memory */ + bus_dmamap_t request_dmap; + char *request; + bus_addr_t request_phys; + + /* scsi linkage */ + request_t *request_pool; + SLIST_HEAD(req_queue, req_entry) request_free_list; + + struct scsi_link sc_link; + struct scsi_adapter sc_adapter; + + uint32_t sequence; /* sequence number */ + uint32_t timeouts; /* timeout count */ + uint32_t success; /* success after timeout */ + + /* Companion part in a 929 or 1030, or NULL. */ + struct mpt_softc *mpt2; + + /* To restore configuration after hard reset. */ + void (*sc_set_config_regs)(struct mpt_softc *); +} mpt_softc_t; + +#define MPT_SYNC_REQ(mpt, req, ops) \ + bus_dmamap_sync((mpt)->sc_dmat, (mpt)->request_dmap, \ + (req)->req_pbuf - (mpt)->request_phys, \ + MPT_REQUEST_AREA, (ops)) + +#define mpt_read(mpt, reg) \ + bus_space_read_4((mpt)->sc_st, (mpt)->sc_sh, (reg)) +#define mpt_write(mpt, reg, val) \ + bus_space_write_4((mpt)->sc_st, (mpt)->sc_sh, (reg), (val)) + +void mpt_attach(mpt_softc_t *); +int mpt_dma_mem_alloc(mpt_softc_t *); +int mpt_intr(void *); +void mpt_prt(mpt_softc_t *, const char *, ...); + +#define mpt_set_config_regs(mpt) \ +do { \ + if ((mpt)->sc_set_config_regs != NULL) \ + (*(mpt)->sc_set_config_regs)((mpt)); \ +} while (/*CONSTCOND*/0) + +#endif /* _DEV_IC_MPT_NETBSD_H_ */ diff --git a/sys/dev/ic/mpt_openbsd.h.orig b/sys/dev/ic/mpt_openbsd.h.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/ic/mpt_openbsd.h.orig diff --git a/sys/dev/pci/mpt_pci.c b/sys/dev/pci/mpt_pci.c new file mode 100644 index 00000000000..7bcb7b69689 --- /dev/null +++ b/sys/dev/pci/mpt_pci.c @@ -0,0 +1,402 @@ +/* $OpenBSD: mpt_pci.c,v 1.1 2004/03/06 03:03:07 krw Exp $ */ +/* $NetBSD: mpt_pci.c,v 1.2 2003/07/14 15:47:26 lukem Exp $ */ + +/* + * Copyright (c) 2004 Milos Urbanek + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * mpt_pci.c: + * + * OpenBSD PCI-specific routines for LSI Fusion adapters. + */ + +#include <sys/cdefs.h> +/* __KERNEL_RCSID(0, "$NetBSD: mpt_pci.c,v 1.2 2003/07/14 15:47:26 lukem Exp $"); */ + +#include <dev/ic/mpt.h> /* pulls in all headers */ + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> + +#define MPT_PCI_MMBA (PCI_MAPREG_START+0x04) + +#define PCI_MAPREG_ROM 0x30 + +struct mpt_pci_softc { + mpt_softc_t sc_mpt; + + pci_chipset_tag_t sc_pc; + pcitag_t sc_tag; + + void *sc_ih; + + /* Saved volatile PCI configuration registers. */ + pcireg_t sc_pci_csr; + pcireg_t sc_pci_bhlc; + pcireg_t sc_pci_io_bar; + pcireg_t sc_pci_mem0_bar[2]; + pcireg_t sc_pci_mem1_bar[2]; + pcireg_t sc_pci_rom_bar; + pcireg_t sc_pci_int; + pcireg_t sc_pci_pmcsr; +}; + +static void mpt_pci_link_peer(mpt_softc_t *); +static void mpt_pci_read_config_regs(mpt_softc_t *); +static void mpt_pci_set_config_regs(mpt_softc_t *); + +#define MPP_F_FC 0x01 /* Fibre Channel adapter */ +#define MPP_F_DUAL 0x02 /* Dual port adapter */ + +static const struct mpt_pci_product { + pci_vendor_id_t mpp_vendor; + pci_product_id_t mpp_product; + int mpp_flags; + const char *mpp_name; +} mpt_pci_products[] = { + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_1030, + MPP_F_DUAL, + "LSI Logic 53c1030 Ultra320 SCSI" }, + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_FC909, + MPP_F_FC, + "LSI Logic FC909 FC Adapter" }, + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_FC909A, + MPP_F_FC, + "LSI Logic FC909A FC Adapter" }, + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_FC929, + MPP_F_FC | MPP_F_DUAL, + "LSI Logic FC929 FC Adapter" }, + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_FC929_1, + MPP_F_FC | MPP_F_DUAL, + "LSI Logic FC929 FC Adapter" }, + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_FC919, + MPP_F_FC, + "LSI Logic FC919 FC Adapter" }, + { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_FC919_1, + MPP_F_FC, + "LSI Logic FC919 FC Adapter" }, + + { 0, 0, + 0, + NULL }, +}; + +static const struct mpt_pci_product * +mpt_pci_lookup(const struct pci_attach_args *pa) +{ + const struct mpt_pci_product *mpp; + + for (mpp = mpt_pci_products; mpp->mpp_name != NULL; mpp++) { + if (PCI_VENDOR(pa->pa_id) == mpp->mpp_vendor && + PCI_PRODUCT(pa->pa_id) == mpp->mpp_product) + return (mpp); + } + return (NULL); +} + +/* probe for mpt controller */ +static int +mpt_pci_match(struct device *parent, void *match, void *aux) +{ + struct pci_attach_args *pa = aux; + + if (mpt_pci_lookup(pa) != NULL) + return (1); + + return (0); +} + +static void +mpt_pci_attach(struct device *parent, struct device *self, void *aux) +{ + struct mpt_pci_softc *psc = (void *) self; + mpt_softc_t *mpt = &psc->sc_mpt; + struct pci_attach_args *pa = aux; + const struct mpt_pci_product *mpp; + pci_intr_handle_t ih; + const char *intrstr; + pcireg_t reg, memtype; + bus_space_tag_t memt; + bus_space_handle_t memh; + int memh_valid; + + mpp = mpt_pci_lookup(pa); + if (mpp == NULL) { + printf("\n"); + panic("mpt_pci_attach"); + } + + if (mpp->mpp_flags & MPP_F_FC) { + mpt->is_fc = 1; + printf(": Fibre Channel controller\n"); + } else + printf(": SCSI controller\n"); + printf(": %s\n", mpp->mpp_name); + + psc->sc_pc = pa->pa_pc; + psc->sc_tag = pa->pa_tag; + + mpt->sc_dmat = pa->pa_dmat; + mpt->sc_set_config_regs = mpt_pci_set_config_regs; + + /* + * Map the device. + */ + memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MPT_PCI_MMBA); + switch (memtype) { + case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: + case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: + memh_valid = (pci_mapreg_map(pa, MPT_PCI_MMBA, + memtype, 0, &memt, &memh, NULL, NULL, 0) == 0); + break; + + default: + memh_valid = 0; + } + + if (memh_valid) { + mpt->sc_st = memt; + mpt->sc_sh = memh; + } else { + printf("%s: unable to map device registers\n", + mpt->mpt_dev.dv_xname); + return; + } + + /* + * Make sure the PCI command register is properly configured. + */ + reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + reg |= PCI_COMMAND_MASTER_ENABLE; + /* XXX PCI_COMMAND_INVALIDATE_ENABLE */ + /* XXX PCI_COMMAND_PARITY_ENABLE */ + /* XXX PCI_COMMAND_SERR_ENABLE */ + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); + + /* + * Ensure that the ROM is diabled. + */ + reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); + reg &= ~1; + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, reg); + + /* + * Map and establish our interrupt. + */ + if (pci_intr_map(pa, &ih) != 0) { + printf("%s: unable to map interrupt\n", + mpt->mpt_dev.dv_xname); + return; + } + intrstr = pci_intr_string(pa->pa_pc, ih); + psc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, mpt_intr, mpt, + mpt->mpt_dev.dv_xname); + if (psc->sc_ih == NULL) { + printf("%s: unable to establish interrupt", + mpt->mpt_dev.dv_xname); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + return; + } + printf("%s: interrupting at %s\n", mpt->mpt_dev.dv_xname, + intrstr); + + /* Disable interrupts on the part. */ + mpt_disable_ints(mpt); + + /* Allocate DMA memory. */ + if (mpt_dma_mem_alloc(mpt) != 0) { + printf("%s: unable to allocate DMA memory\n", + mpt->mpt_dev.dv_xname); + return; + } + + /* + * Save the PCI config register values. + * + * Hard resets are known to screw up the BAR for diagnostic + * memory accesses (Mem1). + * + * Using Mem1 is know to make the chip stop responding to + * configuration cycles, so we need to save it now. + */ + mpt_pci_read_config_regs(mpt); + + /* + * If we're a dual-port adapter, try to find our peer. We + * need to fix his PCI config registers, too. + */ + if (mpp->mpp_flags & MPP_F_DUAL) { + mpt_pci_link_peer(mpt); + } + /* Initialize the hardware. */ + if (mpt_init(mpt, MPT_DB_INIT_HOST) != 0) { + /* Error message already printed. */ + return; + } + + /* Complete attachment of hardware, include subdevices. */ + mpt_attach(mpt); +} + +#if defined(__NetBSD__) +CFATTACH_DECL(mpt_pci, sizeof(struct mpt_pci_softc), + mpt_pci_match, mpt_pci_attach, NULL, NULL); +#else +struct cfattach mpt_pci_ca = { + sizeof (struct mpt_pci_softc), mpt_pci_match, mpt_pci_attach, +}; +#endif + +/* + * Find and remember our peer PCI function on a dual-port device. + */ +static void +mpt_pci_link_peer(mpt_softc_t *mpt) +{ + extern struct cfdriver mpt_cd; + + struct mpt_pci_softc *peer_psc, *psc = (void *) mpt; + struct device *dev; + int unit, b, d, f, peer_b, peer_d, peer_f; + + pci_decompose_tag(psc->sc_pc, psc->sc_tag, &b, &d, &f); + + for (unit = 0; unit < mpt_cd.cd_ndevs; unit++) { + if (unit == mpt->mpt_dev.dv_unit) + continue; + dev = device_lookup(&mpt_cd, unit); + if (dev == NULL) + continue; + if (dev->dv_cfdata == NULL) + continue; + if (dev->dv_cfdata->cf_attach != &mpt_pci_ca) + continue; + peer_psc = (void *) dev; + if (peer_psc->sc_pc != psc->sc_pc) + continue; + pci_decompose_tag(peer_psc->sc_pc, peer_psc->sc_tag, + &peer_b, &peer_d, &peer_f); + if (peer_b == b && peer_d == d) { + if (mpt->verbose) + mpt_prt(mpt, "linking with peer: %s", + peer_psc->sc_mpt.mpt_dev.dv_xname); + mpt->mpt2 = (mpt_softc_t *) peer_psc; + peer_psc->sc_mpt.mpt2 = mpt; + return; + } + } +} + +/* + * Save the volatile PCI configuration registers. + */ +static void +mpt_pci_read_config_regs(mpt_softc_t *mpt) +{ + struct mpt_pci_softc *psc = (void *) mpt; + + psc->sc_pci_csr = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_COMMAND_STATUS_REG); + psc->sc_pci_bhlc = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_BHLC_REG); + psc->sc_pci_io_bar = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_MAPREG_START); + psc->sc_pci_mem0_bar[0] = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_MAPREG_START+0x04); + psc->sc_pci_mem0_bar[1] = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_MAPREG_START+0x08); + psc->sc_pci_mem1_bar[0] = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_MAPREG_START+0x0c); + psc->sc_pci_mem1_bar[1] = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_MAPREG_START+0x10); + psc->sc_pci_rom_bar = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_MAPREG_ROM); + psc->sc_pci_int = pci_conf_read(psc->sc_pc, psc->sc_tag, + PCI_INTERRUPT_REG); + psc->sc_pci_pmcsr = pci_conf_read(psc->sc_pc, psc->sc_tag, 0x44); +} + +/* + * Restore the volatile PCI configuration registers. + */ +static void +mpt_pci_set_config_regs(mpt_softc_t *mpt) +{ + struct mpt_pci_softc *psc = (void *) mpt; + + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_COMMAND_STATUS_REG, + psc->sc_pci_csr); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_BHLC_REG, + psc->sc_pci_bhlc); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_MAPREG_START, + psc->sc_pci_io_bar); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_MAPREG_START+0x04, + psc->sc_pci_mem0_bar[0]); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_MAPREG_START+0x08, + psc->sc_pci_mem0_bar[1]); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_MAPREG_START+0x0c, + psc->sc_pci_mem1_bar[0]); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_MAPREG_START+0x10, + psc->sc_pci_mem1_bar[1]); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_MAPREG_ROM, + psc->sc_pci_rom_bar); + pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_INTERRUPT_REG, + psc->sc_pci_int); + pci_conf_write(psc->sc_pc, psc->sc_tag, 0x44, psc->sc_pci_pmcsr); +} diff --git a/sys/dev/pci/mpt_pci.c.orig b/sys/dev/pci/mpt_pci.c.orig new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/sys/dev/pci/mpt_pci.c.orig |