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authorBrad Smith <brad@cvs.openbsd.org>2005-08-03 16:27:40 +0000
committerBrad Smith <brad@cvs.openbsd.org>2005-08-03 16:27:40 +0000
commit13c5938c4ce1e81531d5172192d5943111775725 (patch)
treea3005e4bbb2d33ff9d53e4d321cb65a4693a31f4 /sys/dev
parentf48fa8a83ce95e2254eb3a12ca0e8f689764ecd8 (diff)
This commit was derived from a commit to FreeBSD..
Use stream bus space accesses to program the ID (station address) registers; otherwise, the byte order of the address is changed on big-endian machines. Though our bus_space API is different. Tested by form at pdp-11 dotorg dot ru and robert@ ok mickey@ robert@
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/ic/rtl81x9.c8
-rw-r--r--sys/dev/ic/rtl81x9reg.h4
2 files changed, 8 insertions, 4 deletions
diff --git a/sys/dev/ic/rtl81x9.c b/sys/dev/ic/rtl81x9.c
index 7a61d069837..4249472551a 100644
--- a/sys/dev/ic/rtl81x9.c
+++ b/sys/dev/ic/rtl81x9.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: rtl81x9.c,v 1.44 2005/07/20 23:02:41 brad Exp $ */
+/* $OpenBSD: rtl81x9.c,v 1.45 2005/08/03 16:27:39 brad Exp $ */
/*
* Copyright (c) 1997, 1998
@@ -977,8 +977,10 @@ void rl_init(xsc)
* register write enable" mode to modify the ID registers.
*/
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
- CSR_WRITE_4(sc, RL_IDR0, *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]));
- CSR_WRITE_4(sc, RL_IDR4, *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]));
+ CSR_WRITE_RAW_4(sc, RL_IDR0,
+ (u_int8_t *)(&sc->sc_arpcom.ac_enaddr[0]));
+ CSR_WRITE_RAW_4(sc, RL_IDR4,
+ (u_int8_t *)(&sc->sc_arpcom.ac_enaddr[4]));
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
/* Init the RX buffer pointer register. */
diff --git a/sys/dev/ic/rtl81x9reg.h b/sys/dev/ic/rtl81x9reg.h
index f723a2a77a1..d3fd05f75d7 100644
--- a/sys/dev/ic/rtl81x9reg.h
+++ b/sys/dev/ic/rtl81x9reg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: rtl81x9reg.h,v 1.19 2005/04/15 03:13:03 brad Exp $ */
+/* $OpenBSD: rtl81x9reg.h,v 1.20 2005/08/03 16:27:39 brad Exp $ */
/*
* Copyright (c) 1997, 1998
@@ -675,6 +675,8 @@ struct rl_softc {
/*
* register space access macros
*/
+#define CSR_WRITE_RAW_4(sc, csr, val) \
+ bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4)
#define CSR_WRITE_4(sc, csr, val) \
bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val)
#define CSR_WRITE_2(sc, csr, val) \