AdvanSys SCSI driver from NetBSD, by dante@mclink.it. Based on the Linux

driver.

6 files changed, 6104 insertions, 0 deletions

diff --git a/sys/dev/ic/adv.c b/sys/dev/ic/adv.c
new file mode 100644
index 00000000000..e3220f1bece
--- /dev/null
+++ b/sys/dev/ic/adv.c
@@ -0,0 +1,1050 @@
+/*	$OpenBSD: adv.c,v 1.1 1998/09/27 03:36:13 downsj Exp $	*/
+/*	$NetBSD: adv.c,v 1.3 1998/09/09 05:28:58 thorpej Exp $	*/
+
+/*
+ * Generic driver for the Advanced Systems Inc. SCSI controllers
+ *
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Author: Baldassare Dante Profeta <dante@mclink.it>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    This product includes software developed by the NetBSD
+ *    Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/buf.h>
+#include <sys/proc.h>
+#include <sys/user.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/ic/adv.h>
+#include <dev/ic/advlib.h>
+
+#ifndef DDB
+#define	Debugger()	panic("should call debugger here (adv.c)")
+#endif /* ! DDB */
+
+/******************************************************************************/
+
+
+static void adv_enqueue __P((ASC_SOFTC *, struct scsi_xfer *, int));
+static struct scsi_xfer *adv_dequeue __P((ASC_SOFTC *));
+
+static int adv_alloc_ccbs __P((ASC_SOFTC *));
+static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
+static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
+static void adv_reset_ccb __P((ADV_CCB *));
+static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
+static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
+static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
+static void adv_start_ccbs __P((ASC_SOFTC *));
+
+static u_int8_t *adv_alloc_overrunbuf __P((char *dvname, bus_dma_tag_t));
+
+static int adv_scsi_cmd __P((struct scsi_xfer *));
+static void advminphys __P((struct buf *));
+static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
+
+static int adv_poll __P((ASC_SOFTC *, struct scsi_xfer *, int));
+static void adv_timeout __P((void *));
+static void adv_watchdog __P((void *));
+
+
+/******************************************************************************/
+
+
+struct cfdriver adv_cd = {
+	NULL, "adv", DV_DULL
+};
+
+
+struct scsi_adapter adv_switch =
+{
+	adv_scsi_cmd,		/* called to start/enqueue a SCSI command */
+	advminphys,		/* to limit the transfer to max device can do */
+	0,			/* IT SEEMS IT IS NOT USED YET */
+	0,			/* as above... */
+};
+
+
+/* the below structure is so we have a default dev struct for out link struct */
+struct scsi_device adv_dev =
+{
+	NULL,			/* Use default error handler */
+	NULL,			/* have a queue, served by this */
+	NULL,			/* have no async handler */
+	NULL,			/* Use default 'done' routine */
+};
+
+
+#define ADV_ABORT_TIMEOUT       2000	/* time to wait for abort (mSec) */
+#define ADV_WATCH_TIMEOUT       1000	/* time to wait for watchdog (mSec) */
+
+
+/******************************************************************************/
+/*                            scsi_xfer queue routines                      */
+/******************************************************************************/
+
+
+/*
+ * Insert a scsi_xfer into the software queue.  We overload xs->free_list
+ * to avoid having to allocate additional resources (since we're used
+ * only during resource shortages anyhow.
+ */
+static void
+adv_enqueue(sc, xs, infront)
+	ASC_SOFTC      *sc;
+	struct scsi_xfer *xs;
+	int             infront;
+{
+
+	if (infront || sc->sc_queue.lh_first == NULL) {
+		if (sc->sc_queue.lh_first == NULL)
+			sc->sc_queuelast = xs;
+		LIST_INSERT_HEAD(&sc->sc_queue, xs, free_list);
+		return;
+	}
+	LIST_INSERT_AFTER(sc->sc_queuelast, xs, free_list);
+	sc->sc_queuelast = xs;
+}
+
+
+/*
+ * Pull a scsi_xfer off the front of the software queue.
+ */
+static struct scsi_xfer *
+adv_dequeue(sc)
+	ASC_SOFTC      *sc;
+{
+	struct scsi_xfer *xs;
+
+	xs = sc->sc_queue.lh_first;
+	LIST_REMOVE(xs, free_list);
+
+	if (sc->sc_queue.lh_first == NULL)
+		sc->sc_queuelast = NULL;
+
+	return (xs);
+}
+
+
+/******************************************************************************/
+/*                             Control Blocks routines                        */
+/******************************************************************************/
+
+
+static int
+adv_alloc_ccbs(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_dma_segment_t seg;
+	int             error, rseg;
+
+	/*
+         * Allocate the control blocks.
+         */
+	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
+			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to allocate control structures,"
+		       " error = %d\n", sc->sc_dev.dv_xname, error);
+		return (error);
+	}
+	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
+		   sizeof(struct adv_control), (caddr_t *) & sc->sc_control,
+				 BUS_DMA_NOWAIT | BUS_DMAMEM_NOSYNC)) != 0) {
+		printf("%s: unable to map control structures, error = %d\n",
+		       sc->sc_dev.dv_xname, error);
+		return (error);
+	}
+	/*
+         * Create and load the DMA map used for the control blocks.
+         */
+	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
+			   1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
+				       &sc->sc_dmamap_control)) != 0) {
+		printf("%s: unable to create control DMA map, error = %d\n",
+		       sc->sc_dev.dv_xname, error);
+		return (error);
+	}
+	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
+			   sc->sc_control, sizeof(struct adv_control), NULL,
+				     BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to load control DMA map, error = %d\n",
+		       sc->sc_dev.dv_xname, error);
+		return (error);
+	}
+	return (0);
+}
+
+
+/*
+ * Create a set of ccbs and add them to the free list.  Called once
+ * by adv_init().  We return the number of CCBs successfully created.
+ */
+static int
+adv_create_ccbs(sc, ccbstore, count)
+	ASC_SOFTC      *sc;
+	ADV_CCB        *ccbstore;
+	int             count;
+{
+	ADV_CCB        *ccb;
+	int             i, error;
+
+	bzero(ccbstore, sizeof(ADV_CCB) * count);
+	for (i = 0; i < count; i++) {
+		ccb = &ccbstore[i];
+		if ((error = adv_init_ccb(sc, ccb)) != 0) {
+			printf("%s: unable to initialize ccb, error = %d\n",
+			       sc->sc_dev.dv_xname, error);
+			return (i);
+		}
+		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
+	}
+
+	return (i);
+}
+
+
+/*
+ * A ccb is put onto the free list.
+ */
+static void
+adv_free_ccb(sc, ccb)
+	ASC_SOFTC      *sc;
+	ADV_CCB        *ccb;
+{
+	int             s;
+
+	s = splbio();
+
+	adv_reset_ccb(ccb);
+	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
+
+	/*
+         * If there were none, wake anybody waiting for one to come free,
+         * starting with queued entries.
+         */
+	if (ccb->chain.tqe_next == 0)
+		wakeup(&sc->sc_free_ccb);
+
+	splx(s);
+}
+
+
+static void
+adv_reset_ccb(ccb)
+	ADV_CCB        *ccb;
+{
+
+	ccb->flags = 0;
+}
+
+
+static int
+adv_init_ccb(sc, ccb)
+	ASC_SOFTC      *sc;
+	ADV_CCB        *ccb;
+{
+	int             error;
+
+	/*
+         * Create the DMA map for this CCB.
+         */
+	error = bus_dmamap_create(sc->sc_dmat,
+				  (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
+			 ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
+		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
+	if (error) {
+		printf("%s: unable to create DMA map, error = %d\n",
+		       sc->sc_dev.dv_xname, error);
+		return (error);
+	}
+	adv_reset_ccb(ccb);
+	return (0);
+}
+
+
+/*
+ * Get a free ccb
+ *
+ * If there are none, see if we can allocate a new one
+ */
+static ADV_CCB *
+adv_get_ccb(sc, flags)
+	ASC_SOFTC      *sc;
+	int             flags;
+{
+	ADV_CCB        *ccb = 0;
+	int             s;
+
+	s = splbio();
+
+	/*
+         * If we can and have to, sleep waiting for one to come free
+         * but only if we can't allocate a new one.
+         */
+	for (;;) {
+		ccb = sc->sc_free_ccb.tqh_first;
+		if (ccb) {
+			TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
+			break;
+		}
+		if ((flags & SCSI_NOSLEEP) != 0)
+			goto out;
+
+		tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
+	}
+
+	ccb->flags |= CCB_ALLOC;
+
+out:
+	splx(s);
+	return (ccb);
+}
+
+
+/*
+ * Queue a CCB to be sent to the controller, and send it if possible.
+ */
+static void
+adv_queue_ccb(sc, ccb)
+	ASC_SOFTC      *sc;
+	ADV_CCB        *ccb;
+{
+
+	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
+
+	adv_start_ccbs(sc);
+}
+
+
+static void
+adv_start_ccbs(sc)
+	ASC_SOFTC      *sc;
+{
+	ADV_CCB        *ccb;
+
+	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
+		if (ccb->flags & CCB_WATCHDOG)
+			untimeout(adv_watchdog, ccb);
+
+		if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
+			ccb->flags |= CCB_WATCHDOG;
+			timeout(adv_watchdog, ccb,
+				(ADV_WATCH_TIMEOUT * hz) / 1000);
+			break;
+		}
+		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
+
+		if ((ccb->xs->flags & SCSI_POLL) == 0)
+			timeout(adv_timeout, ccb, (ccb->timeout * hz) / 1000);
+	}
+}
+
+
+/******************************************************************************/
+/*                      DMA able memory allocation routines                   */
+/******************************************************************************/
+
+
+/*
+ * Allocate a DMA able memory for overrun_buffer.
+ * This memory can be safely shared among all the AdvanSys boards.
+ */
+u_int8_t       *
+adv_alloc_overrunbuf(dvname, dmat)
+	char           *dvname;
+	bus_dma_tag_t   dmat;
+{
+	static u_int8_t *overrunbuf = NULL;
+
+	bus_dmamap_t    ovrbuf_dmamap;
+	bus_dma_segment_t seg;
+	int             rseg, error;
+
+
+	/*
+         * if an overrun buffer has been already allocated don't allocate it
+         * again. Instead return the address of the allocated buffer.
+         */
+	if (overrunbuf)
+		return (overrunbuf);
+
+
+	if ((error = bus_dmamem_alloc(dmat, ASC_OVERRUN_BSIZE,
+			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to allocate overrun buffer, error = %d\n",
+		       dvname, error);
+		return (0);
+	}
+	if ((error = bus_dmamem_map(dmat, &seg, rseg, ASC_OVERRUN_BSIZE,
+	(caddr_t *) & overrunbuf, BUS_DMA_NOWAIT | BUS_DMAMEM_NOSYNC)) != 0) {
+		printf("%s: unable to map overrun buffer, error = %d\n",
+		       dvname, error);
+
+		bus_dmamem_free(dmat, &seg, 1);
+		return (0);
+	}
+	if ((error = bus_dmamap_create(dmat, ASC_OVERRUN_BSIZE, 1,
+	      ASC_OVERRUN_BSIZE, 0, BUS_DMA_NOWAIT, &ovrbuf_dmamap)) != 0) {
+		printf("%s: unable to create overrun buffer DMA map,"
+		       " error = %d\n", dvname, error);
+
+		bus_dmamem_unmap(dmat, overrunbuf, ASC_OVERRUN_BSIZE);
+		bus_dmamem_free(dmat, &seg, 1);
+		return (0);
+	}
+	if ((error = bus_dmamap_load(dmat, ovrbuf_dmamap, overrunbuf,
+			   ASC_OVERRUN_BSIZE, NULL, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to load overrun buffer DMA map,"
+		       " error = %d\n", dvname, error);
+
+		bus_dmamap_destroy(dmat, ovrbuf_dmamap);
+		bus_dmamem_unmap(dmat, overrunbuf, ASC_OVERRUN_BSIZE);
+		bus_dmamem_free(dmat, &seg, 1);
+		return (0);
+	}
+	return (overrunbuf);
+}
+
+
+/******************************************************************************/
+/*                         SCSI layer interfacing routines                    */
+/******************************************************************************/
+
+
+int
+adv_init(sc)
+	ASC_SOFTC      *sc;
+{
+	int             warn;
+
+	if (ASC_IS_NARROW_BOARD(sc)) {
+		if (!AscFindSignature(sc->sc_iot, sc->sc_ioh))
+			panic("adv_init: adv_find_signature failed");
+
+		/*
+                 * Read the board configuration
+                 */
+		AscInitASC_SOFTC(sc);
+		warn = AscInitFromEEP(sc);
+		if (warn) {
+			printf("%s -get: ", sc->sc_dev.dv_xname);
+			switch (warn) {
+			case -1:
+				printf("Chip is not halted\n");
+				break;
+
+			case -2:
+				printf("Couldn't get MicroCode Start"
+				       " address\n");
+				break;
+
+			case ASC_WARN_IO_PORT_ROTATE:
+				printf("I/O port address modified\n");
+				break;
+
+			case ASC_WARN_AUTO_CONFIG:
+				printf("I/O port increment switch enabled\n");
+				break;
+
+			case ASC_WARN_EEPROM_CHKSUM:
+				printf("EEPROM checksum error\n");
+				break;
+
+			case ASC_WARN_IRQ_MODIFIED:
+				printf("IRQ modified\n");
+				break;
+
+			case ASC_WARN_CMD_QNG_CONFLICT:
+				printf("tag queuing enabled w/o disconnects\n");
+				break;
+
+			default:
+				printf("unknown warning %d\n", warn);
+			}
+		}
+		if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
+			sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
+
+		/*
+                 * Modify the board configuration
+                 */
+		warn = AscInitFromASC_SOFTC(sc);
+		if (warn) {
+			printf("%s -set: ", sc->sc_dev.dv_xname);
+			switch (warn) {
+			case ASC_WARN_CMD_QNG_CONFLICT:
+				printf("tag queuing enabled w/o disconnects\n");
+				break;
+
+			case ASC_WARN_AUTO_CONFIG:
+				printf("I/O port increment switch enabled\n");
+				break;
+
+			default:
+				printf("unknown warning %d\n", warn);
+			}
+		}
+		sc->isr_callback = (ulong) adv_narrow_isr_callback;
+
+		if (!(sc->overrun_buf = adv_alloc_overrunbuf(sc->sc_dev.dv_xname,
+							     sc->sc_dmat))) {
+			return (1);
+		}
+	} else
+		//IS_WIDE_BOARD
+	{
+		printf("%s: Wide boards are not supported yet\n",
+		       sc->sc_dev.dv_xname);
+		return (1);
+	}
+
+	return (0);
+}
+
+
+void
+adv_attach(sc)
+	ASC_SOFTC      *sc;
+{
+	int             i, error;
+
+	if (ASC_IS_NARROW_BOARD(sc)) {
+		/*
+                 * Initialize board RISC chip and enable interrupts.
+                 */
+		switch (AscInitDriver(sc)) {
+		case 0:
+			/* AllOK */
+			break;
+
+		case 1:
+			panic("%s: bad signature", sc->sc_dev.dv_xname);
+			break;
+
+		case 2:
+			panic("%s: unable to load MicroCode",
+			      sc->sc_dev.dv_xname);
+			break;
+
+		case 3:
+			panic("%s: unable to initialize MicroCode",
+			      sc->sc_dev.dv_xname);
+			break;
+
+		default:
+			panic("%s: unable to initialize board RISC chip",
+			      sc->sc_dev.dv_xname);
+		}
+	} else
+		//Wide Boards
+	{
+		/* ToDo */
+	}
+
+
+	/*
+         * fill in the prototype scsi_link.
+         */
+	sc->sc_link.adapter_softc = sc;
+	sc->sc_link.adapter_target = sc->chip_scsi_id;
+	sc->sc_link.adapter = &adv_switch;
+	sc->sc_link.device = &adv_dev;
+	sc->sc_link.openings = 4;
+	sc->sc_link.adapter_buswidth = ASC_IS_NARROW_BOARD(sc) ? 7 : 15;
+
+
+	TAILQ_INIT(&sc->sc_free_ccb);
+	TAILQ_INIT(&sc->sc_waiting_ccb);
+	LIST_INIT(&sc->sc_queue);
+
+
+	/*
+         * Allocate the Control Blocks.
+         */
+	error = adv_alloc_ccbs(sc);
+	if (error)
+		return; /* (error) */ ;
+
+	/*
+         * Create and initialize the Control Blocks.
+         */
+	i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
+	if (i == 0) {
+		printf("%s: unable to create control blocks\n",
+		       sc->sc_dev.dv_xname);
+		return; /* (ENOMEM) */ ;
+	} else if (i != ADV_MAX_CCB) {
+		printf("%s: WARNING: only %d of %d control blocks created\n",
+		       sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
+	}
+	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
+}
+
+
+static void
+advminphys(bp)
+	struct buf     *bp;
+{
+
+	if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
+		bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
+	minphys(bp);
+}
+
+
+/*
+ * start a scsi operation given the command and the data address.  Also needs
+ * the unit, target and lu.
+ */
+static int
+adv_scsi_cmd(xs)
+	struct scsi_xfer *xs;
+{
+	struct scsi_link *sc_link = xs->sc_link;
+	ASC_SOFTC      *sc = sc_link->adapter_softc;
+	bus_dma_tag_t   dmat = sc->sc_dmat;
+	ADV_CCB        *ccb;
+	int             s, flags, error, nsegs;
+	int             fromqueue = 1, dontqueue = 0;
+
+
+	s = splbio();		/* protect the queue */
+
+	/*
+         * If we're running the queue from adv_done(), we've been
+         * called with the first queue entry as our argument.
+         */
+	if (xs == sc->sc_queue.lh_first) {
+		xs = adv_dequeue(sc);
+		fromqueue = 1;
+	} else {
+
+		/* Polled requests can't be queued for later. */
+		dontqueue = xs->flags & SCSI_POLL;
+
+		/*
+                 * If there are jobs in the queue, run them first.
+                 */
+		if (sc->sc_queue.lh_first != NULL) {
+			/*
+                         * If we can't queue, we have to abort, since
+                         * we have to preserve order.
+                         */
+			if (dontqueue) {
+				splx(s);
+				xs->error = XS_DRIVER_STUFFUP;
+				return (TRY_AGAIN_LATER);
+			}
+			/*
+                         * Swap with the first queue entry.
+                         */
+			adv_enqueue(sc, xs, 0);
+			xs = adv_dequeue(sc);
+			fromqueue = 1;
+		}
+	}
+
+
+	/*
+         * get a ccb to use. If the transfer
+         * is from a buf (possibly from interrupt time)
+         * then we can't allow it to sleep
+         */
+
+	flags = xs->flags;
+	if ((ccb = adv_get_ccb(sc, flags)) == NULL) {
+		/*
+                 * If we can't queue, we lose.
+                 */
+		if (dontqueue) {
+			splx(s);
+			xs->error = XS_DRIVER_STUFFUP;
+			return (TRY_AGAIN_LATER);
+		}
+		/*
+                 * Stuff ourselves into the queue, in front
+                 * if we came off in the first place.
+                 */
+		adv_enqueue(sc, xs, fromqueue);
+		splx(s);
+		return (SUCCESSFULLY_QUEUED);
+	}
+	splx(s);		/* done playing with the queue */
+
+	ccb->xs = xs;
+	ccb->timeout = xs->timeout;
+
+	/*
+         * Build up the request
+         */
+	memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
+
+	ccb->scsiq.q2.ccb_ptr = (ulong) ccb;
+
+	ccb->scsiq.cdbptr = &xs->cmd->opcode;
+	ccb->scsiq.q2.cdb_len = xs->cmdlen;
+	ccb->scsiq.q1.target_id = ASC_TID_TO_TARGET_ID(sc_link->target);
+	ccb->scsiq.q1.target_lun = sc_link->lun;
+	ccb->scsiq.q2.target_ix = ASC_TIDLUN_TO_IX(sc_link->target,
+						   sc_link->lun);
+#define offsetof(type, member) ((size_t)(&((type *)0)->member))
+	ccb->scsiq.q1.sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
+		ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
+#undef offsetof
+	ccb->scsiq.q1.sense_len = sizeof(struct scsi_sense_data);
+
+	/*
+         * If  there  are  any  outstanding  requests  for  the  current target,
+         * then  every  255th request  send an  ORDERED request.  This heuristic
+         * tries  to  retain  the  benefit  of request  sorting while preventing
+         * request starvation. 255 is the max number of tags or pending commands
+         * a device may have outstanding.
+         */
+	sc->reqcnt[sc_link->target]++;
+	if ((sc->reqcnt[sc_link->target] > 0) &&
+	    (sc->reqcnt[sc_link->target] % 255) == 0) {
+		ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
+	} else {
+		ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
+	}
+
+
+	if (xs->datalen) {
+		/*
+                 * Map the DMA transfer.
+                 */
+#ifdef TFS
+		if (flags & SCSI_DATA_UIO) {
+			error = bus_dmamap_load_uio(dmat,
+				  ccb->dmamap_xfer, (struct uio *) xs->data,
+						    (flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
+		} else
+#endif				/* TFS */
+		{
+			error = bus_dmamap_load(dmat,
+			      ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
+						(flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
+		}
+
+		if (error) {
+			if (error == EFBIG) {
+				printf("%s: adv_scsi_cmd, more than %d dma"
+				       " segments\n",
+				       sc->sc_dev.dv_xname, ASC_MAX_SG_LIST);
+			} else {
+				printf("%s: adv_scsi_cmd, error %d loading"
+				       " dma map\n",
+				       sc->sc_dev.dv_xname, error);
+			}
+
+			xs->error = XS_DRIVER_STUFFUP;
+			adv_free_ccb(sc, ccb);
+			return (COMPLETE);
+		}
+		bus_dmamap_sync(dmat, ccb->dmamap_xfer,
+			      (flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
+				BUS_DMASYNC_PREWRITE);
+
+
+		memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
+
+		for (nsegs = 0; nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
+
+			ccb->sghead.sg_list[nsegs].addr =
+				ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
+			ccb->sghead.sg_list[nsegs].bytes =
+				ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
+		}
+
+		ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
+			ccb->dmamap_xfer->dm_nsegs;
+
+		ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
+		ccb->scsiq.sg_head = &ccb->sghead;
+		ccb->scsiq.q1.data_addr = 0;
+		ccb->scsiq.q1.data_cnt = 0;
+	} else {
+		/*
+                 * No data xfer, use non S/G values.
+                 */
+		ccb->scsiq.q1.data_addr = 0;
+		ccb->scsiq.q1.data_cnt = 0;
+	}
+
+	s = splbio();
+	adv_queue_ccb(sc, ccb);
+	splx(s);
+
+	/*
+         * Usually return SUCCESSFULLY QUEUED
+         */
+	if ((flags & SCSI_POLL) == 0)
+		return (SUCCESSFULLY_QUEUED);
+
+	/*
+         * If we can't use interrupts, poll on completion
+         */
+	if (adv_poll(sc, xs, ccb->timeout)) {
+		adv_timeout(ccb);
+		if (adv_poll(sc, xs, ccb->timeout))
+			adv_timeout(ccb);
+	}
+	return (COMPLETE);
+}
+
+
+int
+adv_intr(arg)
+	void           *arg;
+{
+	ASC_SOFTC      *sc = arg;
+	struct scsi_xfer *xs;
+
+	if (ASC_IS_NARROW_BOARD(sc)) {
+		AscISR(sc);
+	} else
+		//Wide Boards
+	{
+		/* ToDo AdvISR */
+	}
+
+	/*
+         * If there are queue entries in the software queue, try to
+         * run the first one.  We should be more or less guaranteed
+         * to succeed, since we just freed a CCB.
+         *
+         * NOTE: adv_scsi_cmd() relies on our calling it with
+         * the first entry in the queue.
+         */
+	if ((xs = sc->sc_queue.lh_first) != NULL)
+		(void) adv_scsi_cmd(xs);
+
+	return (1);
+}
+
+
+/*
+ * Poll a particular unit, looking for a particular xs
+ */
+static int
+adv_poll(sc, xs, count)
+	ASC_SOFTC      *sc;
+	struct scsi_xfer *xs;
+	int             count;
+{
+
+	/* timeouts are in msec, so we loop in 1000 usec cycles */
+	while (count) {
+		adv_intr(sc);
+		if (xs->flags & ITSDONE)
+			return (0);
+		delay(1000);	/* only happens in boot so ok */
+		count--;
+	}
+	return (1);
+}
+
+
+static void
+adv_timeout(arg)
+	void           *arg;
+{
+	ADV_CCB        *ccb = arg;
+	struct scsi_xfer *xs = ccb->xs;
+	struct scsi_link *sc_link = xs->sc_link;
+	ASC_SOFTC      *sc = sc_link->adapter_softc;
+	int             s;
+
+	sc_print_addr(sc_link);
+	printf("timed out");
+
+	s = splbio();
+
+	/*
+         * If it has been through before, then a previous abort has failed,
+         * don't try abort again, reset the bus instead.
+         */
+	if (ccb->flags & CCB_ABORT) {
+		/* abort timed out */
+		printf(" AGAIN. Resetting Bus\n");
+		/* Lets try resetting the bus! */
+		if (AscResetBus(sc) == ASC_ERROR) {
+			ccb->timeout = sc->scsi_reset_wait;
+			adv_queue_ccb(sc, ccb);
+		}
+	} else {
+		/* abort the operation that has timed out */
+		printf("\n");
+		AscAbortCCB(sc, (u_int32_t) ccb);
+		ccb->xs->error = XS_TIMEOUT;
+		ccb->timeout = ADV_ABORT_TIMEOUT;
+		ccb->flags |= CCB_ABORT;
+		adv_queue_ccb(sc, ccb);
+	}
+
+	splx(s);
+}
+
+
+static void
+adv_watchdog(arg)
+	void           *arg;
+{
+	ADV_CCB        *ccb = arg;
+	struct scsi_xfer *xs = ccb->xs;
+	struct scsi_link *sc_link = xs->sc_link;
+	ASC_SOFTC      *sc = sc_link->adapter_softc;
+	int             s;
+
+	s = splbio();
+
+	ccb->flags &= ~CCB_WATCHDOG;
+	adv_start_ccbs(sc);
+
+	splx(s);
+}
+
+
+/******************************************************************************/
+/*                  NARROW and WIDE boards Interrupt callbacks                */
+/******************************************************************************/
+
+
+/*
+ * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
+ *
+ * Interrupt callback function for the Narrow SCSI Asc Library.
+ */
+static void
+adv_narrow_isr_callback(sc, qdonep)
+	ASC_SOFTC      *sc;
+	ASC_QDONE_INFO *qdonep;
+{
+	bus_dma_tag_t   dmat = sc->sc_dmat;
+	ADV_CCB        *ccb = (ADV_CCB *) qdonep->d2.ccb_ptr;
+	struct scsi_xfer *xs = ccb->xs;
+	struct scsi_sense_data *s1, *s2;
+
+
+	untimeout(adv_timeout, ccb);
+
+	/*
+         * If we were a data transfer, unload the map that described
+         * the data buffer.
+         */
+	if (xs->datalen) {
+		bus_dmamap_sync(dmat, ccb->dmamap_xfer,
+			 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
+				BUS_DMASYNC_POSTWRITE);
+		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
+	}
+	if ((ccb->flags & CCB_ALLOC) == 0) {
+		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
+		Debugger();
+		return;
+	}
+	/*
+         * 'qdonep' contains the command's ending status.
+         */
+	switch (qdonep->d3.done_stat) {
+	case ASC_QD_NO_ERROR:
+		switch (qdonep->d3.host_stat) {
+		case ASC_QHSTA_NO_ERROR:
+			xs->error = XS_NOERROR;
+			xs->resid = 0;
+			break;
+
+		default:
+			/* QHSTA error occurred */
+			xs->error = XS_DRIVER_STUFFUP;
+			break;
+		}
+
+		/*
+                 * If an INQUIRY command completed successfully, then call
+                 * the AscInquiryHandling() function to patch bugged boards.
+                 */
+		if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
+		    (xs->sc_link->lun == 0) &&
+		    (xs->datalen - qdonep->remain_bytes) >= 8) {
+			AscInquiryHandling(sc,
+				      xs->sc_link->target & 0x7,
+					   (ASC_SCSI_INQUIRY *) xs->data);
+		}
+		break;
+
+	case ASC_QD_WITH_ERROR:
+		switch (qdonep->d3.host_stat) {
+		case ASC_QHSTA_NO_ERROR:
+			if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
+				s1 = &ccb->scsi_sense;
+				s2 = &xs->sense;
+				*s2 = *s1;
+				xs->error = XS_SENSE;
+			} else
+				xs->error = XS_DRIVER_STUFFUP;
+			break;
+
+		default:
+			/* QHSTA error occurred */
+			xs->error = XS_DRIVER_STUFFUP;
+			break;
+		}
+		break;
+
+	case ASC_QD_ABORTED_BY_HOST:
+	default:
+		xs->error = XS_DRIVER_STUFFUP;
+		break;
+	}
+
+
+	adv_free_ccb(sc, ccb);
+	xs->flags |= ITSDONE;
+	scsi_done(xs);
+}
diff --git a/sys/dev/ic/adv.h b/sys/dev/ic/adv.h
new file mode 100644
index 00000000000..da5e5d592fc
--- /dev/null
+++ b/sys/dev/ic/adv.h
@@ -0,0 +1,96 @@
+/*	$OpenBSD: adv.h,v 1.1 1998/09/27 03:36:13 downsj Exp $	*/
+/*      $NetBSD: adv.h,v 1.2 1998/08/29 13:45:56 dante Exp $        */
+
+/*
+ * Generic driver definitions and exported functions for the Advanced
+ * Systems Inc. SCSI controllers
+ * 
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Author: Baldassare Dante Profeta <dante@mclink.it>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    This product includes software developed by the NetBSD
+ *    Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ADVANSYS_H_
+#define _ADVANSYS_H_
+
+#include <dev/ic/advlib.h>
+
+/******************************************************************************/
+
+struct adv_ccb
+{
+	ASC_SG_HEAD	sghead;
+	ASC_SCSI_Q	scsiq;
+
+	struct scsi_sense_data scsi_sense;
+
+	TAILQ_ENTRY(adv_ccb) chain;
+	struct scsi_xfer	*xs;	/* the scsi_xfer for this cmd */
+	int			flags;	/* see below */
+
+	int			timeout;
+	/*
+	 * This DMA map maps the buffer involved in the transfer.
+	 */
+	bus_dmamap_t		dmamap_xfer;
+};
+
+typedef struct adv_ccb ADV_CCB;
+
+/* flags for ADV_CCB */
+#define CCB_ALLOC       0x01
+#define CCB_ABORT       0x02
+#define	CCB_WATCHDOG	0x10
+
+
+#define ADV_MAX_CCB	32
+
+struct adv_control
+{
+	ADV_CCB	ccbs[ADV_MAX_CCB];	/* all our control blocks */
+};
+
+/*
+ * Offset of a CCB from the beginning of the control DMA mapping.
+ */
+#define	ADV_CCB_OFF(c)	(offsetof(struct adv_control, ccbs[0]) +	\
+		    (((u_long)(c)) - ((u_long)&sc->sc_control->ccbs[0])))
+
+/******************************************************************************/
+
+int adv_init __P((ASC_SOFTC *sc));
+void adv_attach __P((ASC_SOFTC *sc));
+int adv_intr __P((void *arg));
+
+/******************************************************************************/
+
+#endif /* _ADVANSYS_H_ */
diff --git a/sys/dev/ic/advlib.c b/sys/dev/ic/advlib.c
new file mode 100644
index 00000000000..6140585592d
--- /dev/null
+++ b/sys/dev/ic/advlib.c
@@ -0,0 +1,3370 @@
+/*	$OpenBSD: advlib.c,v 1.1 1998/09/27 03:36:14 downsj Exp $	*/
+/*      $NetBSD: advlib.c,v 1.3 1998/08/29 13:45:57 dante Exp $        */
+
+/*
+ * Low level routines for the Advanced Systems Inc. SCSI controllers chips
+ *
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Author: Baldassare Dante Profeta <dante@mclink.it>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    This product includes software developed by the NetBSD
+ *    Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Ported from:
+ */
+/*
+ * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
+ *
+ * Copyright (c) 1995-1998 Advanced System Products, Inc.
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that redistributions of source
+ * code retain the above copyright notice and this comment without
+ * modification.
+ *
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/queue.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+
+#include <dev/ic/adv.h>
+#include <dev/ic/advlib.h>
+#include <dev/ic/advmcode.h>
+
+
+/******************************************************************************/
+/*                                Static functions                            */
+/******************************************************************************/
+
+/* Initializzation routines */
+static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t *, u_int16_t));
+static void AscInitLram __P((ASC_SOFTC *));
+static void AscInitQLinkVar __P((ASC_SOFTC *));
+static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t));
+static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t));
+
+/* Chip register routines */
+static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t));
+
+/* RISC Chip routines */
+static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t));
+static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t));
+static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t));
+static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t));
+static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t, u_int8_t));
+static int ASC_SET_CHIP_SYNRegAtID __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t, u_int8_t));
+static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t));
+static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t));
+static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t));
+
+/* Lram routines */
+static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int8_t));
+static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t));
+static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int32_t));
+static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t, int));
+static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t *, int));
+static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t *, int));
+static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int32_t *, int));
+static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, int));
+static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t));
+
+/* MicroCode routines */
+static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *));
+static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t));
+
+/* EEProm routines */
+static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t));
+static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static void AscWaitEEPRead __P((void));
+static void AscWaitEEPWrite __P((void));
+static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t));
+static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t, u_int16_t));
+static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t,
+					ASCEEP_CONFIG *, u_int16_t));
+static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t,
+					ASCEEP_CONFIG *, u_int16_t));
+static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t,
+					ASCEEP_CONFIG *, u_int16_t));
+
+/* Interrupt routines */
+static void AscIsrChipHalted __P((ASC_SOFTC *));
+static int AscIsrQDone __P((ASC_SOFTC *));
+static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t));
+static int AscWaitISRDone __P((ASC_SOFTC *));
+static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, ASC_QDONE_INFO *,
+					u_int32_t));
+static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t));
+static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t));
+static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t));
+static u_int8_t AscGetChipIRQ __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t, u_int16_t));
+static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t));
+static u_int32_t AscGetMaxDmaCount __P((u_int16_t));
+static u_int16_t AscGetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t));
+static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t));
+static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t));
+static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t));
+		
+/* Messages routines */
+static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t,
+					ASC_SCSI_BIT_ID_TYPE, int, u_int8_t));
+static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t));
+		
+/* SDTR routines */
+static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t, u_int8_t));
+static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t));
+static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t));
+		
+/* Queue routines */
+static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t));
+static int AscSgListToQueue __P((int));
+static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t));
+static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t));
+static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t));
+static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t,
+					u_int8_t));
+static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t,
+					bus_space_handle_t,
+					u_int8_t, u_int8_t));
+static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t));
+static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t));
+static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t));
+static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t,
+					ASC_SCSI_Q *));
+static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t));
+		
+/* Abort and Reset CCB routines */
+static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, u_int32_t));
+static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t));
+		
+/* Error Handling routines */
+static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t));
+		
+/* Handle bugged borads routines */
+static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *));
+static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *));
+		
+/* Miscellaneous routines */
+static int AscCompareString __P((u_char *, u_char *, int));
+		
+/* Device oriented routines */
+static int DvcEnterCritical __P((void));
+static void DvcLeaveCritical __P((int));
+static void DvcSleepMilliSecond __P((u_int32_t));
+//static void DvcDelayMicroSecond __P((u_int32_t));
+static void DvcDelayNanoSecond __P((u_int32_t));
+static u_int32_t DvcGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t,
+					ASC_SG_HEAD *));
+static void DvcPutScsiQ __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t *, int));
+static void DvcGetQinfo __P((bus_space_tag_t, bus_space_handle_t,
+					u_int16_t, u_int16_t *, int words));
+
+
+/******************************************************************************/
+/*                            Initializzation routines                        */
+/******************************************************************************/
+
+/*
+ * This function perform the following steps:
+ * - initialize ASC_SOFTC structure with defaults values.
+ * - inquire board registers to know what kind of board it is.
+ * - keep track of bugged borads.
+ */
+void
+AscInitASC_SOFTC(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	int             i;
+	u_int8_t        chip_version;
+
+
+	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
+	ASC_SET_CHIP_STATUS(iot, ioh, 0);
+
+	sc->bug_fix_cntl = 0;
+	sc->pci_fix_asyn_xfer = 0;
+	sc->pci_fix_asyn_xfer_always = 0;
+	sc->sdtr_done = 0;
+	sc->cur_total_qng = 0;
+	sc->last_q_shortage = 0;
+	sc->use_tagged_qng = 0;
+	sc->unit_not_ready = 0;
+	sc->queue_full_or_busy = 0;
+	sc->host_init_sdtr_index = 0;
+	sc->can_tagged_qng = 0;
+	sc->cmd_qng_enabled = 0;
+	sc->dvc_cntl = ASC_DEF_DVC_CNTL;
+	sc->init_sdtr = 0;
+	sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
+	sc->scsi_reset_wait = 3;
+	sc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
+	sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type);
+	sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
+	sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
+	sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
+	sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
+	sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR;
+	chip_version = AscGetChipVersion(iot, ioh, sc->bus_type);
+	sc->chip_version = chip_version;
+	if ((sc->bus_type & ASC_IS_PCI) &&
+	    (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
+		sc->bus_type = ASC_IS_PCI_ULTRA;
+		sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
+		sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
+		sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
+		sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
+		sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
+		sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
+		sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
+		sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
+		sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
+		sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
+		sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
+		sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
+		sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
+		sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
+		sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
+		sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
+		sc->max_sdtr_index = 15;
+		if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
+			ASC_SET_EXTRA_CONTROL(iot, ioh,
+				       (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
+		else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050)
+			ASC_SET_EXTRA_CONTROL(iot, ioh,
+				   (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
+	} else {
+		sc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
+		sc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
+		sc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
+		sc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
+		sc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
+		sc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
+		sc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
+		sc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
+		sc->max_sdtr_index = 7;
+	}
+
+	if (sc->bus_type == ASC_IS_PCI)
+		ASC_SET_EXTRA_CONTROL(iot, ioh,
+				      (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
+
+	sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
+	if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) {
+		ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT);
+		sc->bus_type = ASC_IS_ISAPNP;
+	}
+	if ((sc->bus_type & ASC_IS_ISA) != 0)
+		sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh);
+
+	for (i = 0; i <= ASC_MAX_TID; i++) {
+		sc->cur_dvc_qng[i] = 0;
+		sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
+		sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
+	}
+}
+
+
+/*
+ * This function initialize some ASC_SOFTC fields with values read from
+ * on-board EEProm.
+ */
+u_int16_t
+AscInitFromEEP(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	ASCEEP_CONFIG   eep_config_buf;
+	ASCEEP_CONFIG  *eep_config;
+	u_int16_t       chksum;
+	u_int16_t       warn_code;
+	u_int16_t       cfg_msw, cfg_lsw;
+	int             i;
+	int             write_eep = 0;
+
+
+	warn_code = 0;
+	AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE);
+	AscStopQueueExe(iot, ioh);
+	if ((AscStopChip(iot, ioh) == FALSE) ||
+	    (AscGetChipScsiCtrl(iot, ioh) != 0)) {
+		AscResetChipAndScsiBus(iot, ioh);
+		DvcSleepMilliSecond(sc->scsi_reset_wait * 1000);
+	}
+	if (AscIsChipHalted(iot, ioh) == FALSE)
+		return (-1);
+
+	ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
+	if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR)
+		return (-2);
+
+	eep_config = (ASCEEP_CONFIG *) & eep_config_buf;
+	cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
+	cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
+	if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
+		cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
+		warn_code |= ASC_WARN_CFG_MSW_RECOVER;
+		ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
+	}
+	chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type);
+	if (chksum == 0)
+		chksum = 0xAA55;
+
+	if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) {
+		warn_code |= ASC_WARN_AUTO_CONFIG;
+		if (sc->chip_version == 3) {
+			if (eep_config->cfg_lsw != cfg_lsw) {
+				warn_code |= ASC_WARN_EEPROM_RECOVER;
+				eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
+			}
+			if (eep_config->cfg_msw != cfg_msw) {
+				warn_code |= ASC_WARN_EEPROM_RECOVER;
+				eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
+			}
+		}
+	}
+	eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
+	eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
+
+	if (chksum != eep_config->chksum) {
+		if (AscGetChipVersion(iot, ioh, sc->bus_type) ==
+		    ASC_CHIP_VER_PCI_ULTRA_3050) {
+			eep_config->init_sdtr = 0xFF;
+			eep_config->disc_enable = 0xFF;
+			eep_config->start_motor = 0xFF;
+			eep_config->use_cmd_qng = 0;
+			eep_config->max_total_qng = 0xF0;
+			eep_config->max_tag_qng = 0x20;
+			eep_config->cntl = 0xBFFF;
+			eep_config->chip_scsi_id = 7;
+			eep_config->no_scam = 0;
+			eep_config->adapter_info[0] = 0;
+			eep_config->adapter_info[1] = 0;
+			eep_config->adapter_info[2] = 0;
+			eep_config->adapter_info[3] = 0;
+			eep_config->adapter_info[4] = 0;
+			/* Indicate EEPROM-less board. */
+			eep_config->adapter_info[5] = 0xBB;
+		} else {
+			write_eep = 1;
+			warn_code |= ASC_WARN_EEPROM_CHKSUM;
+		}
+	}
+	sc->sdtr_enable = eep_config->init_sdtr;
+	sc->disc_enable = eep_config->disc_enable;
+	sc->cmd_qng_enabled = eep_config->use_cmd_qng;
+	sc->isa_dma_speed = eep_config->isa_dma_speed;
+	sc->start_motor = eep_config->start_motor;
+	sc->dvc_cntl = eep_config->cntl;
+	sc->adapter_info[0] = eep_config->adapter_info[0];
+	sc->adapter_info[1] = eep_config->adapter_info[1];
+	sc->adapter_info[2] = eep_config->adapter_info[2];
+	sc->adapter_info[3] = eep_config->adapter_info[3];
+	sc->adapter_info[4] = eep_config->adapter_info[4];
+	sc->adapter_info[5] = eep_config->adapter_info[5];
+
+	if (!AscTestExternalLram(iot, ioh)) {
+		if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
+			eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
+			eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
+		} else {
+			eep_config->cfg_msw |= 0x0800;
+			cfg_msw |= 0x0800;
+			ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
+			eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
+			eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
+		}
+	}
+	if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG)
+		eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
+
+	if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG)
+		eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
+
+	if (eep_config->max_tag_qng > eep_config->max_total_qng)
+		eep_config->max_tag_qng = eep_config->max_total_qng;
+
+	if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC)
+		eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
+
+	sc->max_total_qng = eep_config->max_total_qng;
+	if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
+	    eep_config->use_cmd_qng) {
+		eep_config->disc_enable = eep_config->use_cmd_qng;
+		warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
+	}
+	if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA))
+		sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type);
+
+	eep_config->chip_scsi_id &= ASC_MAX_TID;
+	sc->chip_scsi_id = eep_config->chip_scsi_id;
+	if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
+	    !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
+		sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
+	}
+	for (i = 0; i <= ASC_MAX_TID; i++) {
+		sc->max_tag_qng[i] = eep_config->max_tag_qng;
+		sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET |
+			(sc->host_init_sdtr_index << 4);
+	}
+
+	eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
+	if (write_eep)
+		AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type);
+
+	return (warn_code);
+}
+
+
+u_int16_t
+AscInitFromASC_SOFTC(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int16_t       cfg_msw;
+	u_int16_t       warn_code;
+	u_int16_t       pci_device_id = sc->pci_device_id;
+
+
+	warn_code = 0;
+	cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
+
+	if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
+		cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
+		warn_code |= ASC_WARN_CFG_MSW_RECOVER;
+		ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
+	}
+	if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) {
+		sc->disc_enable = sc->cmd_qng_enabled;
+		warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
+	}
+	if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) {
+		warn_code |= ASC_WARN_AUTO_CONFIG;
+	}
+	if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
+		AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type);
+	}
+	if (sc->bus_type & ASC_IS_PCI) {
+		cfg_msw &= 0xFFC0;
+		ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
+
+		if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) {
+			if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) ||
+			    (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) {
+				sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
+				sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
+			}
+		}
+	} else if (sc->bus_type == ASC_IS_ISAPNP) {
+		if (AscGetChipVersion(iot, ioh, sc->bus_type) ==
+		    ASC_CHIP_VER_ASYN_BUG) {
+			sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
+		}
+	}
+	AscSetChipScsiID(iot, ioh, sc->chip_scsi_id);
+
+	if (sc->bus_type & ASC_IS_ISA) {
+		AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel);
+		AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed);
+	}
+	return (warn_code);
+}
+
+
+/*
+ * - Initialize RISC chip
+ * - Intialize Lram
+ * - Load uCode into Lram
+ * - Enable Interrupts
+ */
+int
+AscInitDriver(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int32_t       chksum;
+
+
+	if (!AscFindSignature(iot, ioh))
+		return (1);
+
+	AscDisableInterrupt(iot, ioh);
+
+	AscInitLram(sc);
+	chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode,
+				  asc_mcode_size);
+	if (chksum != asc_mcode_chksum)
+		return (2);
+
+	if (AscInitMicroCodeVar(sc) == 0)
+		return (3);
+
+	AscEnableInterrupt(iot, ioh);
+
+	return (0);
+}
+
+
+int
+AscFindSignature(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int16_t       sig_word;
+
+	if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) {
+		sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh);
+		if (sig_word == ASC_1000_ID0W ||
+		    sig_word == ASC_1000_ID0W_FIX)
+			return (1);
+	}
+	return (0);
+}
+
+
+static u_int32_t
+AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int16_t      *mcode_buf;
+	u_int16_t       mcode_size;
+{
+	u_int32_t       chksum;
+	u_int16_t       mcode_word_size;
+	u_int16_t       mcode_chksum;
+
+	mcode_word_size = mcode_size >> 1;
+	/* clear board memory */
+	AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size);
+	/* copy uCode to board memory */
+	AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size);
+	chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size);
+	mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG,
+			   ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1));
+	AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum);
+	AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size);
+
+	return (chksum);
+}
+
+
+static void
+AscInitLram(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int8_t        i;
+	u_int16_t       s_addr;
+
+
+	AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0,
+			  (((sc->max_total_qng + 2 + 1) * 64) >> 1));
+
+	i = ASC_MIN_ACTIVE_QNO;
+	s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
+	AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1);
+	AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng);
+	AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
+	i++;
+	s_addr += ASC_QBLK_SIZE;
+	for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
+		AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1);
+		AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1);
+		AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
+	}
+	AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END);
+	AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1);
+	AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng);
+	i++;
+	s_addr += ASC_QBLK_SIZE;
+	for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) {
+		AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i);
+		AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i);
+		AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
+	}
+}
+
+
+void
+AscReInitLram(sc)
+	ASC_SOFTC      *sc;
+{
+
+	AscInitLram(sc);
+	AscInitQLinkVar(sc);
+}
+
+
+static void
+AscInitQLinkVar(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int8_t        i;
+	u_int16_t       lram_addr;
+
+
+	ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1);
+	ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng);
+	ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1);
+	ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng);
+	AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1);
+	AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2);
+	AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng);
+	AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0);
+	AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0);
+	AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0);
+	AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0);
+	ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0);
+	lram_addr = ASC_QADR_BEG;
+	for (i = 0; i < 32; i++, lram_addr += 2)
+		AscWriteLramWord(iot, ioh, lram_addr, 0);
+}
+
+
+static int
+AscResetChipAndScsiBus(bus_space_tag_t iot,
+		       bus_space_handle_t ioh)
+{
+	while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE);
+
+	AscStopChip(iot, ioh);
+	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT);
+
+	DvcDelayNanoSecond(60000);
+
+	AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM);
+	AscSetChipIH(iot, ioh, ASC_INS_HALT);
+	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT);
+	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
+
+	DvcSleepMilliSecond(200);
+
+	ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
+	AscStartChip(iot, ioh);
+
+	DvcSleepMilliSecond(200);
+
+	return (AscIsChipHalted(iot, ioh));
+}
+
+
+static u_int16_t
+AscGetChipBusType(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int16_t       chip_ver;
+
+	chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh);
+	if ((chip_ver >= ASC_CHIP_MIN_VER_VL) &&
+	    (chip_ver <= ASC_CHIP_MAX_VER_VL)) {
+		/*
+		 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50)
+		 * == 0x0C50)) return (ASC_IS_EISA);
+		 */
+		return (ASC_IS_VL);
+	}
+	if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
+	    (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
+		if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP)
+			return (ASC_IS_ISAPNP);
+
+		return (ASC_IS_ISA);
+	} else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
+		   (chip_ver <= ASC_CHIP_MAX_VER_PCI))
+		return (ASC_IS_PCI);
+
+	return (0);
+}
+
+
+/******************************************************************************/
+/*                             Chip register routines                         */
+/******************************************************************************/
+
+
+static void
+AscSetBank(iot, ioh, bank)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        bank;
+{
+	u_int8_t        val;
+
+	val = ASC_GET_CHIP_CONTROL(iot, ioh) &
+		(~(ASC_CC_SINGLE_STEP | ASC_CC_TEST |
+		   ASC_CC_DIAG | ASC_CC_SCSI_RESET |
+		   ASC_CC_CHIP_RESET));
+
+	switch (bank) {
+	case 1:
+		val |= ASC_CC_BANK_ONE;
+		break;
+
+	case 2:
+		val |= ASC_CC_DIAG | ASC_CC_BANK_ONE;
+		break;
+
+	default:
+		val &= ~ASC_CC_BANK_ONE;
+	}
+
+	ASC_SET_CHIP_CONTROL(iot, ioh, val);
+	return;
+}
+
+
+/******************************************************************************/
+/*                                 Chip routines                              */
+/******************************************************************************/
+
+
+static int
+AscStartChip(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	ASC_SET_CHIP_CONTROL(iot, ioh, 0);
+	if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0)
+		return (0);
+
+	return (1);
+}
+
+
+static int
+AscStopChip(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int8_t        cc_val;
+
+	cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) &
+		(~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG));
+	ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT);
+	AscSetChipIH(iot, ioh, ASC_INS_HALT);
+	AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM);
+	if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0)
+		return (0);
+
+	return (1);
+}
+
+
+static u_int8_t
+AscGetChipVersion(iot, ioh, bus_type)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       bus_type;
+{
+	if (bus_type & ASC_IS_EISA) {
+		/*
+		 * u_int16_t	eisa_iop; u_int8_t	revision;
+		 *
+		 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) |
+		 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop);
+		 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision);
+		 */
+	}
+	return (ASC_GET_CHIP_VER_NO(iot, ioh));
+}
+
+
+static u_int8_t
+AscSetChipScsiID(iot, ioh, new_id)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        new_id;
+{
+	u_int16_t       cfg_lsw;
+
+	if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id)
+		return (new_id);
+
+	cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh);
+	cfg_lsw &= 0xF8FF;
+	cfg_lsw |= (new_id & ASC_MAX_TID) << 8;
+	ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
+	return (ASC_GET_CHIP_SCSI_ID(iot, ioh));
+}
+
+
+static u_int8_t
+AscGetChipScsiCtrl(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int8_t        scsi_ctrl;
+
+	AscSetBank(iot, ioh, 1);
+	scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC);
+	AscSetBank(iot, ioh, 0);
+	return (scsi_ctrl);
+}
+
+
+static int
+AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        tid_no;
+	u_int8_t        sdtr_data;
+{
+	int             retval = FALSE;
+
+	if (AscHostReqRiscHalt(iot, ioh)) {
+		retval = ASC_SET_CHIP_SYNRegAtID(iot, ioh, tid_no, sdtr_data);
+		AscStartChip(iot, ioh);
+	}
+	return (retval);
+}
+
+
+static int
+ASC_SET_CHIP_SYNRegAtID(iot, ioh, id, sdtr_data)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        id;
+	u_int8_t        sdtr_data;
+{
+	ASC_SCSI_BIT_ID_TYPE org_id;
+	int             i;
+	int             sta = TRUE;
+
+	AscSetBank(iot, ioh, 1);
+	org_id = ASC_READ_CHIP_DVC_ID(iot, ioh);
+	for (i = 0; i <= ASC_MAX_TID; i++)
+		if (org_id == (0x01 << i))
+			break;
+
+	org_id = i;
+	ASC_WRITE_CHIP_DVC_ID(iot, ioh, id);
+	if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) {
+		AscSetBank(iot, ioh, 0);
+		ASC_SET_CHIP_SYN(iot, ioh, sdtr_data);
+		if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data)
+			sta = FALSE;
+	} else
+		sta = FALSE;
+
+	AscSetBank(iot, ioh, 1);
+	ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id);
+	AscSetBank(iot, ioh, 0);
+	return (sta);
+}
+
+
+static int
+AscHostReqRiscHalt(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	int             count = 0;
+	int             retval = 0;
+	u_int8_t        saved_stop_code;
+
+
+	if (AscIsChipHalted(iot, ioh))
+		return (1);
+	saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
+	AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B,
+		      ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
+
+	do {
+		if (AscIsChipHalted(iot, ioh)) {
+			retval = 1;
+			break;
+		}
+		DvcSleepMilliSecond(100);
+	} while (count++ < 20);
+
+	AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code);
+
+	return (retval);
+}
+
+
+static int
+AscIsChipHalted(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0)
+		if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0)
+			return (1);
+
+	return (0);
+}
+
+
+static void
+AscSetChipIH(iot, ioh, ins_code)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       ins_code;
+{
+	AscSetBank(iot, ioh, 1);
+	ASC_WRITE_CHIP_IH(iot, ioh, ins_code);
+	AscSetBank(iot, ioh, 0);
+
+	return;
+}
+
+
+/******************************************************************************/
+/*                                 Lram routines                              */
+/******************************************************************************/
+
+
+static u_int8_t
+AscReadLramByte(iot, ioh, addr)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       addr;
+{
+	u_int8_t        byte_data;
+	u_int16_t       word_data;
+
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE);
+	word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
+#if BYTE_ORDER == BIG_ENDIAN
+	if (addr & 1)
+		//odd address
+			byte_data = (u_int8_t) (word_data & 0xFF);
+	else
+		byte_data = (u_int8_t) ((word_data >> 8) & 0xFF);
+#else
+	if (addr & 1)
+		//odd address
+			byte_data = (u_int8_t) ((word_data >> 8) & 0xFF);
+	else
+		byte_data = (u_int8_t) (word_data & 0xFF);
+#endif
+	return (byte_data);
+}
+
+
+static void
+AscWriteLramByte(iot, ioh, addr, data)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       addr;
+	u_int8_t        data;
+{
+	u_int16_t       word_data;
+
+
+	word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE);
+#if BYTE_ORDER == BIG_ENDIAN
+	if (addr & 1)
+		//odd address
+	{
+		word_data &= 0xFF00;
+		word_data |= ((u_int16_t) data) & 0x00FF;
+	} else {
+		word_data &= 0xFF00;
+		word_data |= (((u_int16_t) data) << 8) & 0xFF00;
+	}
+#else
+	if (addr & 1)
+		//odd address
+	{
+		word_data &= 0x00FF;
+		word_data |= (((u_int16_t) data) << 8) & 0xFF00;
+	} else {
+		word_data &= 0xFF00;
+		word_data |= ((u_int16_t) data) & 0x00FF;
+	}
+#endif
+	AscWriteLramWord(iot, ioh, addr, word_data);
+}
+
+
+static u_int16_t
+AscReadLramWord(iot, ioh, addr)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       addr;
+{
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
+	return (ASC_GET_CHIP_LRAM_DATA(iot, ioh));
+}
+
+
+static void
+AscWriteLramWord(iot, ioh, addr, data)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       addr;
+	u_int16_t       data;
+{
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
+	ASC_SET_CHIP_LRAM_DATA(iot, ioh, data);
+}
+
+
+static u_int32_t
+AscReadLramDWord(iot, ioh, addr)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       addr;
+{
+	u_int16_t       low_word, hi_word;
+
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
+	low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
+	hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
+
+	return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word);
+}
+
+
+static void
+AscWriteLramDWord(iot, ioh, addr, data)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       addr;
+	u_int32_t       data;
+{
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
+	ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF));
+	ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16));
+}
+
+
+static void
+AscMemWordSetLram(iot, ioh, s_addr, s_words, count)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int16_t       s_words;
+	int             count;
+{
+	int             i;
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
+	for (i = 0; i < count; i++)
+		ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words);
+}
+
+
+static void
+AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int16_t      *s_buffer;
+	int             words;
+{
+	int             i;
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
+	for (i = 0; i < words; i++, s_buffer++)
+		ASC_SET_CHIP_LRAM_DATA(iot, ioh, *s_buffer);
+}
+
+
+static void
+AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int16_t      *s_buffer;
+	int             words;
+{
+	int             i;
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
+	for (i = 0; i < words; i++, s_buffer++)
+		*s_buffer = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
+}
+
+
+static void
+AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int32_t      *s_buffer;
+	int             dwords;
+{
+	int             i;
+	int             words;
+	u_int16_t      *pw;
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
+
+	pw = (u_int16_t *) s_buffer;
+	words = dwords << 1;
+	for (i = 0; i < words; i++, pw++)
+		ASC_SET_CHIP_LRAM_DATA(iot, ioh, *pw);
+}
+
+
+static u_int32_t
+AscMemSumLramWord(iot, ioh, s_addr, words)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	int             words;
+{
+	u_int32_t       sum = 0L;
+	u_int16_t       i;
+
+
+	for (i = 0; i < words; i++, s_addr += 2)
+		sum += AscReadLramWord(iot, ioh, s_addr);
+
+	return (sum);
+}
+
+
+static int
+AscTestExternalLram(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int16_t       q_addr;
+	u_int16_t       saved_word;
+	int             retval;
+
+
+	retval = 0;
+	q_addr = ASC_QNO_TO_QADDR(241);
+	saved_word = AscReadLramWord(iot, ioh, q_addr);
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr);
+	ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA);
+	DvcSleepMilliSecond(10);
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr);
+
+	if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) {
+		retval = 1;
+		AscWriteLramWord(iot, ioh, q_addr, saved_word);
+	}
+	return (retval);
+}
+
+
+/******************************************************************************/
+/*                               MicroCode routines                           */
+/******************************************************************************/
+
+
+static u_int16_t
+AscInitMicroCodeVar(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int32_t       phy_addr;
+	int             i;
+
+
+	for (i = 0; i <= ASC_MAX_TID; i++)
+		ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i,
+					      sc->sdtr_period_offset[i]);
+
+	AscInitQLinkVar(sc);
+	AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable);
+	AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B,
+			 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id));
+
+	if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf,
+					 ASC_OVERRUN_BSIZE)) == 0L) {
+		return (0);
+	} else {
+		phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8;
+		AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr);
+		AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D,
+				  ASC_OVERRUN_BSIZE - 8);
+	}
+
+	sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W);
+	sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W);
+	ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
+
+	if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) {
+		return (0);
+	}
+	if (AscStartChip(iot, ioh) != 1) {
+		return (0);
+	}
+	return (1);
+}
+
+
+static u_int32_t
+AscGetOnePhyAddr(sc, buf_addr, buf_size)
+	ASC_SOFTC      *sc;
+	u_int8_t       *buf_addr;
+	u_int32_t       buf_size;
+{
+	ASC_MIN_SG_HEAD sg_head;
+
+	sg_head.entry_cnt = ASC_MIN_SG_LIST;
+	if (DvcGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) !=
+	    buf_size) {
+		return (0L);
+	}
+	if (sg_head.entry_cnt > 1) {
+		return (0L);
+	}
+	return (sg_head.sg_list[0].addr);
+}
+/******************************************************************************/
+/*                                 EEProm routines                            */
+/******************************************************************************/
+
+
+static int
+AscWriteEEPCmdReg(iot, ioh, cmd_reg)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        cmd_reg;
+{
+	u_int8_t        read_back;
+	int             retry;
+
+	retry = 0;
+
+	while (TRUE) {
+		ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg);
+		DvcSleepMilliSecond(1);
+		read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh);
+		if (read_back == cmd_reg)
+			return (1);
+
+		if (retry++ > ASC_EEP_MAX_RETRY)
+			return (0);
+	}
+}
+
+
+static int
+AscWriteEEPDataReg(iot, ioh, data_reg)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       data_reg;
+{
+	u_int16_t       read_back;
+	int             retry;
+
+	retry = 0;
+	while (TRUE) {
+		ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg);
+		DvcSleepMilliSecond(1);
+		read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh);
+		if (read_back == data_reg)
+			return (1);
+
+		if (retry++ > ASC_EEP_MAX_RETRY)
+			return (0);
+	}
+}
+
+
+static void
+AscWaitEEPRead(void)
+{
+
+	DvcSleepMilliSecond(1);
+}
+
+
+static void
+AscWaitEEPWrite(void)
+{
+
+	DvcSleepMilliSecond(1);
+}
+
+
+static u_int16_t
+AscReadEEPWord(iot, ioh, addr)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        addr;
+{
+	u_int16_t       read_wval;
+	u_int8_t        cmd_reg;
+
+	AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE);
+	AscWaitEEPRead();
+	cmd_reg = addr | ASC_EEP_CMD_READ;
+	AscWriteEEPCmdReg(iot, ioh, cmd_reg);
+	AscWaitEEPRead();
+	read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh);
+	AscWaitEEPRead();
+
+	return (read_wval);
+}
+
+
+static u_int16_t
+AscWriteEEPWord(iot, ioh, addr, word_val)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        addr;
+	u_int16_t       word_val;
+{
+	u_int16_t       read_wval;
+
+	read_wval = AscReadEEPWord(iot, ioh, addr);
+	if (read_wval != word_val) {
+		AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE);
+		AscWaitEEPRead();
+		AscWriteEEPDataReg(iot, ioh, word_val);
+		AscWaitEEPRead();
+		AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr);
+		AscWaitEEPWrite();
+		AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE);
+		AscWaitEEPRead();
+		return (AscReadEEPWord(iot, ioh, addr));
+	}
+	return (read_wval);
+}
+
+
+static u_int16_t
+AscGetEEPConfig(iot, ioh, cfg_buf, bus_type)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	ASCEEP_CONFIG  *cfg_buf;
+	u_int16_t       bus_type;
+{
+	u_int16_t       wval;
+	u_int16_t       sum;
+	u_int16_t      *wbuf;
+	int             cfg_beg;
+	int             cfg_end;
+	int             s_addr;
+	int             isa_pnp_wsize;
+
+
+	wbuf = (u_int16_t *) cfg_buf;
+	sum = 0;
+	isa_pnp_wsize = 0;
+
+	for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) {
+		wval = AscReadEEPWord(iot, ioh, s_addr);
+		sum += wval;
+		*wbuf = wval;
+	}
+
+	if (bus_type & ASC_IS_VL) {
+		cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
+		cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
+	} else {
+		cfg_beg = ASC_EEP_DVC_CFG_BEG;
+		cfg_end = ASC_EEP_MAX_DVC_ADDR;
+	}
+
+	for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
+		wval = AscReadEEPWord(iot, ioh, s_addr);
+		sum += wval;
+		*wbuf = wval;
+	}
+
+	*wbuf = AscReadEEPWord(iot, ioh, s_addr);
+
+	return (sum);
+}
+
+
+static int
+AscSetEEPConfig(iot, ioh, cfg_buf, bus_type)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	ASCEEP_CONFIG  *cfg_buf;
+	u_int16_t       bus_type;
+{
+	int             retry;
+	int             n_error;
+
+	retry = 0;
+	while (TRUE) {
+		if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0)
+			break;
+
+		if (++retry > ASC_EEP_MAX_RETRY)
+			break;
+	}
+
+	return (n_error);
+}
+
+
+static int
+AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	ASCEEP_CONFIG  *cfg_buf;
+	u_int16_t       bus_type;
+{
+	int             n_error;
+	u_int16_t      *wbuf;
+	u_int16_t       sum;
+	int             s_addr;
+	int             cfg_beg;
+	int             cfg_end;
+
+	wbuf = (u_int16_t *) cfg_buf;
+	n_error = 0;
+	sum = 0;
+
+	for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
+		sum += *wbuf;
+		if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf))
+			n_error++;
+	}
+
+	if (bus_type & ASC_IS_VL) {
+		cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
+		cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
+	} else {
+		cfg_beg = ASC_EEP_DVC_CFG_BEG;
+		cfg_end = ASC_EEP_MAX_DVC_ADDR;
+	}
+
+	for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
+		sum += *wbuf;
+		if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf))
+			n_error++;
+	}
+
+	*wbuf = sum;
+	if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum))
+		n_error++;
+
+	wbuf = (u_int16_t *) cfg_buf;
+	for (s_addr = 0; s_addr < 2; s_addr++, wbuf++)
+		if (*wbuf != AscReadEEPWord(iot, ioh, s_addr))
+			n_error++;
+
+	for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++)
+		if (*wbuf != AscReadEEPWord(iot, ioh, s_addr))
+			n_error++;
+
+	return (n_error);
+}
+
+
+/******************************************************************************/
+/*                               Interrupt routines                           */
+/******************************************************************************/
+
+
+int
+AscISR(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int16_t       chipstat;
+	u_int16_t       saved_ram_addr;
+	u_int8_t        ctrl_reg;
+	u_int8_t        saved_ctrl_reg;
+	int             int_pending;
+	int             status;
+	u_int8_t        host_flag;
+
+
+	int_pending = FALSE;
+
+	ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh);
+	saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET |
+			   ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST));
+	chipstat = ASC_GET_CHIP_STATUS(iot, ioh);
+	if (chipstat & ASC_CSW_SCSI_RESET_LATCH)
+		if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
+			int_pending = TRUE;
+			sc->sdtr_done = 0;
+			saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT);
+
+			while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE);
+
+			ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT));
+			ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
+			ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
+			ASC_SET_CHIP_STATUS(iot, ioh, 0);
+			chipstat = ASC_GET_CHIP_STATUS(iot, ioh);
+		}
+	saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh);
+	host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) &
+		(u_int8_t) (~ASC_HOST_FLAG_IN_ISR);
+	AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B,
+			 (host_flag | ASC_HOST_FLAG_IN_ISR));
+
+	if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) {
+		AscAckInterrupt(iot, ioh);
+		int_pending = TRUE;
+
+		if ((chipstat & ASC_CSW_HALTED) &&
+		    (ctrl_reg & ASC_CC_SINGLE_STEP)) {
+			AscIsrChipHalted(sc);
+			saved_ctrl_reg &= ~ASC_CC_HALT;
+		} else {
+			if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) {
+				while (((status = AscIsrQDone(sc)) & 0x01) != 0);
+			} else {
+				do {
+					if ((status = AscIsrQDone(sc)) == 1)
+						break;
+				} while (status == 0x11);
+			}
+
+			if (status & 0x80)
+				int_pending = -1;
+		}
+	}
+	AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag);
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr);
+	ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg);
+
+	return (1);
+	/* return(int_pending); */
+}
+
+
+static int
+AscIsrQDone(sc)
+	ASC_SOFTC      *sc;
+{
+	u_int8_t        next_qp;
+	u_int8_t        n_q_used;
+	u_int8_t        sg_list_qp;
+	u_int8_t        sg_queue_cnt;
+	u_int8_t        q_cnt;
+	u_int8_t        done_q_tail;
+	u_int8_t        tid_no;
+	ASC_SCSI_BIT_ID_TYPE scsi_busy;
+	ASC_SCSI_BIT_ID_TYPE target_id;
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int16_t       q_addr;
+	u_int16_t       sg_q_addr;
+	u_int8_t        cur_target_qng;
+	ASC_QDONE_INFO  scsiq_buf;
+	ASC_QDONE_INFO *scsiq;
+	ASC_ISR_CALLBACK asc_isr_callback;
+
+
+	asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback;
+	n_q_used = 1;
+	scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
+	done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh);
+	q_addr = ASC_QNO_TO_QADDR(done_q_tail);
+	next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD));
+
+	if (next_qp != ASC_QLINK_END) {
+		ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp);
+		q_addr = ASC_QNO_TO_QADDR(next_qp);
+		sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq,
+						     sc->max_dma_count);
+		AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS),
+		      (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED)));
+		tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
+		target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
+		if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) {
+			sg_q_addr = q_addr;
+			sg_list_qp = next_qp;
+			for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
+				sg_list_qp = AscReadLramByte(iot, ioh,
+					       sg_q_addr + ASC_SCSIQ_B_FWD);
+				sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
+				if (sg_list_qp == ASC_QLINK_END) {
+					AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS);
+					scsiq->d3.done_stat = ASC_QD_WITH_ERROR;
+					scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED;
+					panic("AscIsrQDone: Corrupted SG list encountered");
+				}
+				AscWriteLramByte(iot, ioh,
+				sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE);
+			}
+			n_q_used = sg_queue_cnt + 1;
+			ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp);
+		}
+		if (sc->queue_full_or_busy & target_id) {
+			cur_target_qng = AscReadLramByte(iot, ioh,
+					ASC_QADR_BEG + scsiq->d2.target_ix);
+
+			if (cur_target_qng < sc->max_dvc_qng[tid_no]) {
+				scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
+				scsi_busy &= ~target_id;
+				AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
+				sc->queue_full_or_busy &= ~target_id;
+			}
+		}
+		if (sc->cur_total_qng >= n_q_used) {
+			sc->cur_total_qng -= n_q_used;
+			if (sc->cur_dvc_qng[tid_no] != 0)
+				sc->cur_dvc_qng[tid_no]--;
+		} else {
+			AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG);
+			scsiq->d3.done_stat = ASC_QD_WITH_ERROR;
+			panic("AscIsrQDone: Attempting to free more queues than are active");
+		}
+
+		if ((scsiq->d2.ccb_ptr == 0UL) || ((scsiq->q_status & ASC_QS_ABORTED) != 0)) {
+			return (0x11);
+		} else if (scsiq->q_status == ASC_QS_DONE) {
+			scsiq->remain_bytes += scsiq->extra_bytes;
+
+			if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) {
+				if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) {
+					if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) {
+						scsiq->d3.done_stat = ASC_QD_NO_ERROR;
+						scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR;
+					}
+				} else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
+					AscStopChip(iot, ioh);
+					ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT));
+					DvcDelayNanoSecond(60000);
+					ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
+					ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
+					ASC_SET_CHIP_STATUS(iot, ioh, 0);
+					ASC_SET_CHIP_CONTROL(iot, ioh, 0);
+				}
+			}
+			(*asc_isr_callback) (sc, scsiq);
+
+			return (1);
+		} else {
+			AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS);
+			panic("AscIsrQDone: completed scsiq with unknown status");
+
+			return (0x80);
+		}
+	}
+	return (0);
+}
+
+
+/*
+ * handle all the conditions that may halt the board
+ * waiting us to intervene
+ */
+static void
+AscIsrChipHalted(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	EXT_MSG         out_msg;
+	u_int16_t       int_halt_code;
+	u_int16_t       halt_q_addr;
+	u_int8_t        halt_qp;
+	u_int8_t        target_ix;
+	u_int8_t        tag_code;
+	u_int8_t        q_status;
+	u_int8_t        q_cntl;
+	u_int8_t        tid_no;
+	u_int8_t        cur_dvc_qng;
+	u_int8_t        asyn_sdtr;
+	u_int8_t        scsi_status;
+	u_int8_t        sdtr_data;
+	ASC_SCSI_BIT_ID_TYPE scsi_busy;
+	ASC_SCSI_BIT_ID_TYPE target_id;
+
+
+	int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W);
+
+	halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B);
+	halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
+	target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX);
+	q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL);
+	tid_no = ASC_TIX_TO_TID(target_ix);
+	target_id = ASC_TID_TO_TARGET_ID(tid_no);
+
+	if (sc->pci_fix_asyn_xfer & target_id)
+		asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
+	else
+		asyn_sdtr = 0;
+
+	if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
+		if (sc->pci_fix_asyn_xfer & target_id) {
+			AscSetChipSDTR(iot, ioh, 0, tid_no);
+			sc->sdtr_data[tid_no] = 0;
+		}
+		AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	} else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
+		if (sc->pci_fix_asyn_xfer & target_id) {
+			AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
+			sc->sdtr_data[tid_no] = asyn_sdtr;
+		}
+		AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	} else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
+		AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id,
+				  tid_no, asyn_sdtr);
+		AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	} else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
+		q_cntl |= ASC_QC_REQ_SENSE;
+
+		if (sc->init_sdtr & target_id) {
+			sc->sdtr_done &= ~target_id;
+
+			sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
+			q_cntl |= ASC_QC_MSG_OUT;
+			AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) &
+						  (sc->max_sdtr_index - 1)],
+				      (sdtr_data & ASC_SYN_MAX_OFFSET));
+		}
+		AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
+
+		tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE);
+		tag_code &= 0xDC;
+
+		if ((sc->pci_fix_asyn_xfer & target_id) &&
+		    !(sc->pci_fix_asyn_xfer_always & target_id)) {
+			tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT |
+				     ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
+		}
+		AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code);
+
+		q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS);
+		q_status |= ASC_QS_READY | ASC_QS_BUSY;
+
+		AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status);
+
+		scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
+		scsi_busy &= ~target_id;
+		AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
+
+		AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	} else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
+		AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG,
+			     (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1);
+
+		if ((out_msg.msg_type == MS_EXTEND) &&
+		    (out_msg.msg_len == MS_SDTR_LEN) &&
+		    (out_msg.msg_req == MS_SDTR_CODE)) {
+
+			sc->init_sdtr &= ~target_id;
+			sc->sdtr_done &= ~target_id;
+			AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
+			sc->sdtr_data[tid_no] = asyn_sdtr;
+		}
+		q_cntl &= ~ASC_QC_MSG_OUT;
+		AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
+		AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	} else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
+		scsi_status = AscReadLramByte(iot, ioh,
+				       halt_q_addr + ASC_SCSIQ_SCSI_STATUS);
+		cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG);
+
+		if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) {
+			scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
+			scsi_busy |= target_id;
+			AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
+			sc->queue_full_or_busy |= target_id;
+
+			if (scsi_status == SS_QUEUE_FULL) {
+				if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
+					cur_dvc_qng -= 1;
+					sc->max_dvc_qng[tid_no] = cur_dvc_qng;
+
+					AscWriteLramByte(iot, ioh,
+							 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng);
+
+#if ASC_QUEUE_FLOW_CONTROL
+					if ((sc->device[tid_no] != NULL) &&
+					    (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) {
+						sc->device[tid_no]->queue_curr_depth = cur_dvc_qng;
+					}
+#endif				/* ASC_QUEUE_FLOW_CONTROL */
+				}
+			}
+		}
+		AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
+	}
+	return;
+}
+
+
+static int
+AscWaitTixISRDone(sc, target_ix)
+	ASC_SOFTC      *sc;
+	u_int8_t        target_ix;
+{
+	u_int8_t        cur_req;
+	u_int8_t        tid_no;
+	int             i = 0;
+
+	tid_no = ASC_TIX_TO_TID(target_ix);
+	while (i++ < 10) {
+		if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0)
+			break;
+
+		DvcSleepMilliSecond(1000L);
+		if (sc->cur_dvc_qng[tid_no] == cur_req)
+			break;
+	}
+	return (1);
+}
+
+static int
+AscWaitISRDone(sc)
+	ASC_SOFTC      *sc;
+{
+	int             tid;
+
+	for (tid = 0; tid <= ASC_MAX_TID; tid++)
+		AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid));
+
+	return (1);
+}
+
+
+static u_int8_t
+_AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       q_addr;
+	ASC_QDONE_INFO *scsiq;
+	u_int32_t       max_dma_count;
+{
+	u_int16_t       _val;
+	u_int8_t        sg_queue_cnt;
+
+	DvcGetQinfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, (u_int16_t *) scsiq,
+		    ((sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2));
+	_val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
+	scsiq->q_status = _val;
+	scsiq->q_no = (_val >> 8);
+	_val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL);
+	scsiq->cntl = _val;
+	sg_queue_cnt = (_val >> 8);
+	_val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN);
+	scsiq->sense_len = _val;
+	scsiq->extra_bytes = (_val >> 8);
+	scsiq->remain_bytes = AscReadLramWord(iot, ioh,
+				     q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT);
+	scsiq->remain_bytes &= max_dma_count;
+
+	return (sg_queue_cnt);
+}
+
+
+static void
+AscToggleIRQAct(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+
+	ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT);
+	ASC_SET_CHIP_STATUS(iot, ioh, 0);
+}
+
+
+static void
+AscDisableInterrupt(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int16_t       cfg;
+
+	cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh);
+	ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON));
+}
+
+
+static void
+AscEnableInterrupt(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int16_t       cfg;
+
+	cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh);
+	ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON);
+}
+
+
+static u_int8_t
+AscGetChipIRQ(iot, ioh, bus_type)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       bus_type;
+{
+	u_int16_t       cfg_lsw;
+	u_int8_t        chip_irq;
+
+
+	if (bus_type & ASC_IS_EISA) {
+		/*
+		 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq =
+		 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) ||
+		 * (chip_irq > 15)) return (0); return(chip_irq);
+		 */
+	}
+	if ((bus_type & ASC_IS_VL) != 0) {
+		cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
+		chip_irq = (cfg_lsw >> 2) & 0x07;
+		if ((chip_irq == 0) ||
+		    (chip_irq == 4) ||
+		    (chip_irq == 7)) {
+			return (0);
+		}
+		return (chip_irq + (ASC_MIN_IRQ_NO - 1));
+	}
+	cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
+	chip_irq = (cfg_lsw >> 2) & 0x03;
+	if (chip_irq == 3)
+		chip_irq += 2;
+	return (chip_irq + ASC_MIN_IRQ_NO);
+}
+
+
+static u_int8_t
+AscSetChipIRQ(iot, ioh, irq_no, bus_type)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        irq_no;
+	u_int16_t       bus_type;
+{
+	u_int16_t       cfg_lsw;
+
+
+	if (bus_type & ASC_IS_VL) {
+		if (irq_no) {
+			if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO))
+				irq_no = 0;
+			else
+				irq_no -= ASC_MIN_IRQ_NO - 1;
+		}
+
+		cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3;
+		cfg_lsw |= 0x0010;
+		ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
+		AscToggleIRQAct(iot, ioh);
+		cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0;
+		cfg_lsw |= (irq_no & 0x07) << 2;
+		ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
+		AscToggleIRQAct(iot, ioh);
+
+		return (AscGetChipIRQ(iot, ioh, bus_type));
+	}
+	if (bus_type & ASC_IS_ISA) {
+		if (irq_no == 15)
+			irq_no -= 2;
+		irq_no -= ASC_MIN_IRQ_NO;
+		cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3;
+		cfg_lsw |= (irq_no & 0x03) << 2;
+		ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
+
+		return (AscGetChipIRQ(iot, ioh, bus_type));
+	}
+	return (0);
+}
+
+
+static void
+AscAckInterrupt(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int8_t        host_flag;
+	u_int8_t        risc_flag;
+	u_int16_t       loop;
+
+
+	loop = 0;
+	do {
+		risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B);
+		if (loop++ > 0x7FFF)
+			break;
+	} while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
+
+	host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) &
+		(~ASC_HOST_FLAG_ACK_INT);
+	AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B,
+			 host_flag | ASC_HOST_FLAG_ACK_INT);
+	ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK);
+
+	loop = 0;
+	while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) {
+		ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK);
+		if (loop++ > 3)
+			break;
+	}
+
+	AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag);
+}
+
+
+static u_int32_t
+AscGetMaxDmaCount(bus_type)
+	u_int16_t       bus_type;
+{
+	if (bus_type & ASC_IS_ISA)
+		return (ASC_MAX_ISA_DMA_COUNT);
+	else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
+		return (ASC_MAX_VL_DMA_COUNT);
+	return (ASC_MAX_PCI_DMA_COUNT);
+}
+
+
+static u_int16_t
+AscGetIsaDmaChannel(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int16_t       channel;
+
+	channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003;
+	if (channel == 0x03)
+		return (0);
+	else if (channel == 0x00)
+		return (7);
+	return (channel + 4);
+}
+
+
+static u_int16_t
+AscSetIsaDmaChannel(iot, ioh, dma_channel)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       dma_channel;
+{
+	u_int16_t       cfg_lsw;
+	u_int8_t        value;
+
+	if ((dma_channel >= 5) && (dma_channel <= 7)) {
+		if (dma_channel == 7)
+			value = 0x00;
+		else
+			value = dma_channel - 4;
+		cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC;
+		cfg_lsw |= value;
+		ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
+		return (AscGetIsaDmaChannel(iot, ioh));
+	}
+	return (0);
+}
+
+
+static u_int8_t
+AscGetIsaDmaSpeed(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	u_int8_t        speed_value;
+
+	AscSetBank(iot, ioh, 1);
+	speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh);
+	speed_value &= 0x07;
+	AscSetBank(iot, ioh, 0);
+	return (speed_value);
+}
+
+
+static u_int8_t
+AscSetIsaDmaSpeed(iot, ioh, speed_value)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        speed_value;
+{
+	speed_value &= 0x07;
+	AscSetBank(iot, ioh, 1);
+	ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value);
+	AscSetBank(iot, ioh, 0);
+	return (AscGetIsaDmaSpeed(iot, ioh));
+}
+
+
+/******************************************************************************/
+/*                              Messages routines                             */
+/******************************************************************************/
+
+
+static void
+AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr)
+	ASC_SOFTC      *sc;
+	u_int16_t       halt_q_addr;
+	u_int8_t        q_cntl;
+	ASC_SCSI_BIT_ID_TYPE target_id;
+	int             tid_no;
+	u_int8_t        asyn_sdtr;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	EXT_MSG         ext_msg;
+	u_int8_t        sdtr_data;
+	int             sdtr_accept;
+
+
+	AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG,
+			     (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
+
+	if (ext_msg.msg_type == MS_EXTEND &&
+	    ext_msg.msg_req == MS_SDTR_CODE &&
+	    ext_msg.msg_len == MS_SDTR_LEN) {
+		sdtr_accept = TRUE;
+
+		if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) {
+			sdtr_accept = FALSE;
+			ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
+		}
+		if ((ext_msg.xfer_period <
+		     sc->sdtr_period_tbl[sc->host_init_sdtr_index]) ||
+		    (ext_msg.xfer_period >
+		     sc->sdtr_period_tbl[sc->max_sdtr_index])) {
+			sdtr_accept = FALSE;
+			ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index];
+		}
+		if (sdtr_accept) {
+			sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
+						   ext_msg.req_ack_offset);
+			if (sdtr_data == 0xFF) {
+				q_cntl |= ASC_QC_MSG_OUT;
+				sc->init_sdtr &= ~target_id;
+				sc->sdtr_done &= ~target_id;
+				AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
+				sc->sdtr_data[tid_no] = asyn_sdtr;
+			}
+		}
+		if (ext_msg.req_ack_offset == 0) {
+			q_cntl &= ~ASC_QC_MSG_OUT;
+			sc->init_sdtr &= ~target_id;
+			sc->sdtr_done &= ~target_id;
+			AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
+		} else {
+			if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) {
+				q_cntl &= ~ASC_QC_MSG_OUT;
+				sc->sdtr_done |= target_id;
+				sc->init_sdtr |= target_id;
+				sc->pci_fix_asyn_xfer &= ~target_id;
+				sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
+						    ext_msg.req_ack_offset);
+				AscSetChipSDTR(iot, ioh, sdtr_data, tid_no);
+				sc->sdtr_data[tid_no] = sdtr_data;
+			} else {
+				q_cntl |= ASC_QC_MSG_OUT;
+				AscMsgOutSDTR(sc, ext_msg.xfer_period,
+					      ext_msg.req_ack_offset);
+				sc->pci_fix_asyn_xfer &= ~target_id;
+				sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
+						    ext_msg.req_ack_offset);
+				AscSetChipSDTR(iot, ioh, sdtr_data, tid_no);
+				sc->sdtr_data[tid_no] = sdtr_data;
+				sc->sdtr_done |= target_id;
+				sc->init_sdtr |= target_id;
+			}
+		}
+	} else if (ext_msg.msg_type == MS_EXTEND &&
+		   ext_msg.msg_req == MS_WDTR_CODE &&
+		   ext_msg.msg_len == MS_WDTR_LEN) {
+		ext_msg.wdtr_width = 0;
+		AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
+			     (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
+		q_cntl |= ASC_QC_MSG_OUT;
+	} else {
+		ext_msg.msg_type = M1_MSG_REJECT;
+		AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
+			     (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
+		q_cntl |= ASC_QC_MSG_OUT;
+	}
+
+	AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
+}
+
+
+static u_int8_t
+AscMsgOutSDTR(sc, sdtr_period, sdtr_offset)
+	ASC_SOFTC      *sc;
+	u_int8_t        sdtr_period;
+	u_int8_t        sdtr_offset;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	EXT_MSG         sdtr_buf;
+	u_int8_t        sdtr_period_index;
+
+
+	sdtr_buf.msg_type = MS_EXTEND;
+	sdtr_buf.msg_len = MS_SDTR_LEN;
+	sdtr_buf.msg_req = MS_SDTR_CODE;
+	sdtr_buf.xfer_period = sdtr_period;
+	sdtr_offset &= ASC_SYN_MAX_OFFSET;
+	sdtr_buf.req_ack_offset = sdtr_offset;
+	if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <=
+	    sc->max_sdtr_index) {
+		AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
+			    (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1);
+		return ((sdtr_period_index << 4) | sdtr_offset);
+	} else {
+		sdtr_buf.req_ack_offset = 0;
+		AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
+			    (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1);
+		return (0);
+	}
+}
+
+
+/******************************************************************************/
+/*                                  SDTR routines                             */
+/******************************************************************************/
+
+
+static void
+AscSetChipSDTR(iot, ioh, sdtr_data, tid_no)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        sdtr_data;
+	u_int8_t        tid_no;
+{
+	ASC_SET_CHIP_SYNRegAtID(iot, ioh, tid_no, sdtr_data);
+	AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data);
+}
+
+
+static u_int8_t
+AscCalSDTRData(sc, sdtr_period, syn_offset)
+	ASC_SOFTC      *sc;
+	u_int8_t        sdtr_period;
+	u_int8_t        syn_offset;
+{
+	u_int8_t        byte;
+	u_int8_t        sdtr_period_ix;
+
+	sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period);
+	if (sdtr_period_ix > sc->max_sdtr_index)
+		return (0xFF);
+
+	byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
+	return (byte);
+}
+
+
+static u_int8_t
+AscGetSynPeriodIndex(sc, syn_time)
+	ASC_SOFTC      *sc;
+	u_int8_t        syn_time;
+{
+	u_int8_t       *period_table;
+	int             max_index;
+	int             min_index;
+	int             i;
+
+	period_table = sc->sdtr_period_tbl;
+	max_index = sc->max_sdtr_index;
+	min_index = sc->host_init_sdtr_index;
+	if ((syn_time <= period_table[max_index])) {
+		for (i = min_index; i < (max_index - 1); i++) {
+			if (syn_time <= period_table[i])
+				return (i);
+		}
+
+		return (max_index);
+	} else
+		return (max_index + 1);
+}
+
+
+/******************************************************************************/
+/*                                 Queue routines                             */
+/******************************************************************************/
+
+/*
+ * Send a command to the board
+ */
+int
+AscExeScsiQueue(sc, scsiq)
+	ASC_SOFTC      *sc;
+	ASC_SCSI_Q     *scsiq;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	ASC_SG_HEAD    *sg_head = scsiq->sg_head;
+	int             retval;
+	int             n_q_required;
+	int             disable_syn_offset_one_fix;
+	int             i;
+	u_int32_t       addr;
+	u_int16_t       sg_entry_cnt = 0;
+	u_int16_t       sg_entry_cnt_minus_one = 0;
+	u_int8_t        target_ix;
+	u_int8_t        tid_no;
+	u_int8_t        sdtr_data;
+	u_int8_t        extra_bytes;
+	u_int8_t        scsi_cmd;
+	u_int32_t       data_cnt;
+
+
+	scsiq->q1.q_no = 0;
+	if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)
+		scsiq->q1.extra_bytes = 0;
+
+	retval = ASC_BUSY;
+	target_ix = scsiq->q2.target_ix;
+	tid_no = ASC_TIX_TO_TID(target_ix);
+	n_q_required = 1;
+
+	if (scsiq->cdbptr[0] == SCSICMD_RequestSense)
+		if ((sc->init_sdtr & scsiq->q1.target_id) != 0) {
+			sc->sdtr_done &= ~scsiq->q1.target_id;
+			sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
+			AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) &
+						  (sc->max_sdtr_index - 1)],
+				      sdtr_data & ASC_SYN_MAX_OFFSET);
+			scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT);
+		}
+	/*
+	 * if there is just one segment into S/G list then
+	 * map it as it was a single request, filling
+	 * data_addr and data_cnt of ASC_SCSIQ structure.
+	 */
+	if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
+		sg_entry_cnt = sg_head->entry_cnt;
+
+		if (sg_entry_cnt < 1)
+			panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.",
+			      sg_entry_cnt);
+
+		if (sg_entry_cnt > ASC_MAX_SG_LIST)
+			panic("AscExeScsiQueue: Queue with too many segs.");
+
+		if (sg_entry_cnt == 1) {
+			scsiq->q1.data_addr = sg_head->sg_list[0].addr;
+			scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
+			scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE);
+		}
+		sg_entry_cnt_minus_one = sg_entry_cnt - 1;
+	}
+	scsi_cmd = scsiq->cdbptr[0];
+	disable_syn_offset_one_fix = FALSE;
+	if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
+	    !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
+		if (scsiq->q1.cntl & ASC_QC_SG_HEAD) {
+			data_cnt = 0;
+			for (i = 0; i < sg_entry_cnt; i++)
+				data_cnt += sg_head->sg_list[i].bytes;
+		} else {
+			data_cnt = scsiq->q1.data_cnt;
+		}
+
+		if (data_cnt != 0ul) {
+			if (data_cnt < 512ul) {
+				disable_syn_offset_one_fix = TRUE;
+			} else {
+				if (scsi_cmd == SCSICMD_Inquiry ||
+				    scsi_cmd == SCSICMD_RequestSense ||
+				    scsi_cmd == SCSICMD_ReadCapacity ||
+				    scsi_cmd == SCSICMD_ReadTOC ||
+				    scsi_cmd == SCSICMD_ModeSelect6 ||
+				    scsi_cmd == SCSICMD_ModeSense6 ||
+				    scsi_cmd == SCSICMD_ModeSelect10 ||
+				    scsi_cmd == SCSICMD_ModeSense10) {
+					disable_syn_offset_one_fix = TRUE;
+				}
+			}
+		}
+	}
+	if (disable_syn_offset_one_fix) {
+		scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE;
+		scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
+				       ASC_TAG_FLAG_DISABLE_DISCONNECT);
+	} else {
+		scsiq->q2.tag_code &= 0x23;
+	}
+
+	if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
+		if (sc->bug_fix_cntl) {
+			if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
+				if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) {
+					addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr +
+						sg_head->sg_list[sg_entry_cnt_minus_one].bytes;
+					extra_bytes = addr & 0x0003;
+					if ((extra_bytes != 0) &&
+					    ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) {
+						scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
+						scsiq->q1.extra_bytes = extra_bytes;
+						sg_head->sg_list[sg_entry_cnt_minus_one].bytes -=
+							extra_bytes;
+					}
+				}
+			}
+		}
+		sg_head->entry_to_copy = sg_head->entry_cnt;
+		n_q_required = AscSgListToQueue(sg_entry_cnt);
+		if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required)
+		    || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) {
+			retval = AscSendScsiQueue(sc, scsiq, n_q_required);
+		}
+	} else {
+		if (sc->bug_fix_cntl) {
+			if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
+				if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) {
+					addr = scsiq->q1.data_addr + scsiq->q1.data_cnt;
+					extra_bytes = addr & 0x0003;
+					if ((extra_bytes != 0) &&
+					    ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) {
+						if ((scsiq->q1.data_cnt & 0x01FF) == 0) {
+							scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
+							scsiq->q1.data_cnt -= extra_bytes;
+							scsiq->q1.extra_bytes = extra_bytes;
+						}
+					}
+				}
+			}
+		}
+		n_q_required = 1;
+		if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) ||
+		    ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) {
+			retval = AscSendScsiQueue(sc, scsiq, n_q_required);
+		}
+	}
+
+	return (retval);
+}
+
+
+static int
+AscSendScsiQueue(sc, scsiq, n_q_required)
+	ASC_SOFTC      *sc;
+	ASC_SCSI_Q     *scsiq;
+	u_int8_t        n_q_required;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int8_t        free_q_head;
+	u_int8_t        next_qp;
+	u_int8_t        tid_no;
+	u_int8_t        target_ix;
+	int             retval;
+
+
+	target_ix = scsiq->q2.target_ix;
+	tid_no = ASC_TIX_TO_TID(target_ix);
+	retval = ASC_BUSY;
+	free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh);
+
+	if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required))
+	    != ASC_QLINK_END) {
+		if (n_q_required > 1) {
+			sc->last_q_shortage = 0;
+			scsiq->sg_head->queue_cnt = n_q_required - 1;
+		}
+		scsiq->q1.q_no = free_q_head;
+
+		if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) {
+			ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp);
+			sc->cur_total_qng += n_q_required;
+			sc->cur_dvc_qng[tid_no]++;
+		}
+	}
+	return (retval);
+}
+
+
+static int
+AscPutReadySgListQueue(sc, scsiq, q_no)
+	ASC_SOFTC      *sc;
+	ASC_SCSI_Q     *scsiq;
+	u_int8_t        q_no;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	int             retval;
+	int             i;
+	ASC_SG_HEAD    *sg_head;
+	ASC_SG_LIST_Q   scsi_sg_q;
+	u_int32_t       saved_data_addr;
+	u_int32_t       saved_data_cnt;
+	u_int16_t       sg_list_dwords;
+	u_int16_t       sg_index;
+	u_int16_t       sg_entry_cnt;
+	u_int16_t       q_addr;
+	u_int8_t        next_qp;
+
+
+	saved_data_addr = scsiq->q1.data_addr;
+	saved_data_cnt = scsiq->q1.data_cnt;
+
+	if ((sg_head = scsiq->sg_head) != 0) {
+		scsiq->q1.data_addr = sg_head->sg_list[0].addr;
+		scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
+		sg_entry_cnt = sg_head->entry_cnt - 1;
+		if (sg_entry_cnt != 0) {
+			q_addr = ASC_QNO_TO_QADDR(q_no);
+			sg_index = 1;
+			scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
+			scsi_sg_q.sg_head_qp = q_no;
+			scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST;
+
+			for (i = 0; i < sg_head->queue_cnt; i++) {
+				scsi_sg_q.seq_no = i + 1;
+				if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
+					sg_list_dwords = ASC_SG_LIST_PER_Q * 2;
+					sg_entry_cnt -= ASC_SG_LIST_PER_Q;
+					if (i == 0) {
+						scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
+						scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
+					} else {
+						scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
+						scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
+					}
+				} else {
+					scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END;
+					sg_list_dwords = sg_entry_cnt << 1;
+					if (i == 0) {
+						scsi_sg_q.sg_list_cnt = sg_entry_cnt;
+						scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
+					} else {
+						scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
+						scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
+					}
+
+					sg_entry_cnt = 0;
+				}
+
+				next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD);
+				scsi_sg_q.q_no = next_qp;
+				q_addr = ASC_QNO_TO_QADDR(next_qp);
+
+				/*
+				 * Tell the board how many entries are in the S/G list
+				 */
+				AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
+						     (u_int16_t *) & scsi_sg_q, sizeof(ASC_SG_LIST_Q) >> 1);
+				/*
+				 * Tell the board the addresses of the S/G list segments
+				 */
+				AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG,
+						      (u_int32_t *) & sg_head->sg_list[sg_index], sg_list_dwords);
+				sg_index += ASC_SG_LIST_PER_Q;
+			}
+		}
+	}
+	retval = AscPutReadyQueue(sc, scsiq, q_no);
+	scsiq->q1.data_addr = saved_data_addr;
+	scsiq->q1.data_cnt = saved_data_cnt;
+	return (retval);
+}
+
+
+static int
+AscPutReadyQueue(sc, scsiq, q_no)
+	ASC_SOFTC      *sc;
+	ASC_SCSI_Q     *scsiq;
+	u_int8_t        q_no;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int16_t       q_addr;
+	u_int8_t        tid_no;
+	u_int8_t        sdtr_data;
+	u_int8_t        syn_period_ix;
+	u_int8_t        syn_offset;
+
+
+	if (((sc->init_sdtr & scsiq->q1.target_id) != 0) &&
+	    ((sc->sdtr_done & scsiq->q1.target_id) == 0)) {
+		tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
+		sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
+		syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1);
+		syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
+		AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset);
+		scsiq->q1.cntl |= ASC_QC_MSG_OUT;
+	}
+	q_addr = ASC_QNO_TO_QADDR(q_no);
+
+	if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) {
+		scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE;
+	}
+	scsiq->q1.status = ASC_QS_FREE;
+	AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG,
+		       (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
+
+	DvcPutScsiQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG,
+		    (u_int16_t *) & scsiq->q1.cntl,
+		    ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
+
+	/*
+	 * Let's start the command
+	 */
+	AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
+			 (scsiq->q1.q_no << 8) | ASC_QS_READY);
+
+	return (ASC_NOERROR);
+}
+
+
+static int
+AscSgListToQueue(sg_list)
+	int             sg_list;
+{
+	int             n_sg_list_qs;
+
+	n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
+	if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
+		n_sg_list_qs++;
+
+	return (n_sg_list_qs + 1);
+}
+
+
+static u_int
+AscGetNumOfFreeQueue(sc, target_ix, n_qs)
+	ASC_SOFTC      *sc;
+	u_int8_t        target_ix;
+	u_int8_t        n_qs;
+{
+	u_int           cur_used_qs;
+	u_int           cur_free_qs;
+
+
+	if (n_qs == 1) {
+		cur_used_qs = sc->cur_total_qng +
+			sc->last_q_shortage +
+			ASC_MIN_FREE_Q;
+	} else {
+		cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q;
+	}
+
+	if ((cur_used_qs + n_qs) <= sc->max_total_qng) {
+		cur_free_qs = sc->max_total_qng - cur_used_qs;
+		return (cur_free_qs);
+	}
+	if (n_qs > 1)
+		if ((n_qs > sc->last_q_shortage) &&
+		    (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) {
+			sc->last_q_shortage = n_qs;
+		}
+	return (0);
+}
+
+
+static u_int8_t
+AscAllocFreeQueue(iot, ioh, free_q_head)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        free_q_head;
+{
+	u_int16_t       q_addr;
+	u_int8_t        next_qp;
+	u_int8_t        q_status;
+
+
+	q_addr = ASC_QNO_TO_QADDR(free_q_head);
+	q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
+	next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD);
+	if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END))
+		return (next_qp);
+
+	return (ASC_QLINK_END);
+}
+
+
+static u_int8_t
+AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t        free_q_head;
+	u_int8_t        n_free_q;
+{
+	u_int8_t        i;
+
+	for (i = 0; i < n_free_q; i++) {
+		free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head);
+		if (free_q_head == ASC_QLINK_END)
+			break;
+	}
+
+	return (free_q_head);
+}
+
+
+static int
+AscStopQueueExe(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	int             count = 0;
+
+	if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) {
+		AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP);
+		do {
+			if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) &
+			    ASC_STOP_ACK_RISC_STOP)
+				return (1);
+
+			DvcSleepMilliSecond(100);
+		} while (count++ < 20);
+	}
+	return (0);
+}
+
+
+static void
+AscStartQueueExe(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+
+	if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0)
+		AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0);
+}
+
+
+static void
+AscCleanUpBusyQueue(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	int             count = 0;
+	u_int8_t        stop_code;
+
+
+	if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) {
+		AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q);
+		do {
+			stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
+			if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0)
+				break;
+
+			DvcSleepMilliSecond(100);
+		} while (count++ < 20);
+	}
+}
+
+
+static int
+_AscWaitQDone(iot, ioh, scsiq)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	ASC_SCSI_Q     *scsiq;
+{
+	u_int16_t       q_addr;
+	u_int8_t        q_status;
+	int             count = 0;
+
+	while (scsiq->q1.q_no == 0);
+
+	q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no);
+	do {
+		q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
+		DvcSleepMilliSecond(100L);
+		if (count++ > 30)
+			return (0);
+
+	} while ((q_status & ASC_QS_READY) != 0);
+
+	return (1);
+}
+
+
+static int
+AscCleanUpDiscQueue(iot, ioh)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+{
+	int             count;
+	u_int8_t        stop_code;
+
+	count = 0;
+	if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) {
+		AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q);
+		do {
+			stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
+			if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0)
+				break;
+
+			DvcSleepMilliSecond(100);
+		} while (count++ < 20);
+	}
+	return (1);
+}
+
+
+/******************************************************************************/
+/*                           Abort and Reset CCB routines                     */
+/******************************************************************************/
+
+
+int
+AscAbortCCB(sc, ccb)
+	ASC_SOFTC      *sc;
+	u_int32_t       ccb;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	int             retval;
+	ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready;
+
+
+	retval = -1;
+	saved_unit_not_ready = sc->unit_not_ready;
+	sc->unit_not_ready = 0xFF;
+	AscWaitISRDone(sc);
+	if (AscStopQueueExe(iot, ioh) == 1) {
+		if (AscRiscHaltedAbortCCB(sc, ccb) == 1) {
+			retval = 1;
+			AscCleanUpBusyQueue(iot, ioh);
+			AscStartQueueExe(iot, ioh);
+		} else {
+			retval = 0;
+			AscStartQueueExe(iot, ioh);
+		}
+	}
+	sc->unit_not_ready = saved_unit_not_ready;
+
+	return (retval);
+}
+
+
+static int
+AscRiscHaltedAbortCCB(sc, ccb)
+	ASC_SOFTC      *sc;
+	u_int32_t       ccb;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int16_t       q_addr;
+	u_int8_t        q_no;
+	ASC_QDONE_INFO  scsiq_buf;
+	ASC_QDONE_INFO *scsiq;
+	ASC_ISR_CALLBACK asc_isr_callback;
+	int             last_int_level;
+
+
+	asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback;
+	last_int_level = DvcEnterCritical();
+	scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
+
+	for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) {
+		q_addr = ASC_QNO_TO_QADDR(q_no);
+		scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh,
+					       q_addr + ASC_SCSIQ_D_CCBPTR);
+		if (scsiq->d2.ccb_ptr == ccb) {
+			_AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count);
+			if (((scsiq->q_status & ASC_QS_READY) != 0)
+			    && ((scsiq->q_status & ASC_QS_ABORTED) == 0)
+			  && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) {
+				scsiq->q_status |= ASC_QS_ABORTED;
+				scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST;
+				AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L);
+				AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
+						 scsiq->q_status);
+				(*asc_isr_callback) (sc, scsiq);
+				return (1);
+			}
+		}
+	}
+
+	DvcLeaveCritical(last_int_level);
+	return (0);
+}
+
+
+static int
+AscRiscHaltedAbortTIX(sc, target_ix)
+	ASC_SOFTC      *sc;
+	u_int8_t        target_ix;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	u_int16_t       q_addr;
+	u_int8_t        q_no;
+	ASC_QDONE_INFO  scsiq_buf;
+	ASC_QDONE_INFO *scsiq;
+	ASC_ISR_CALLBACK asc_isr_callback;
+	int             last_int_level;
+
+
+	asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback;
+	last_int_level = DvcEnterCritical();
+	scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
+	for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) {
+		q_addr = ASC_QNO_TO_QADDR(q_no);
+		_AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count);
+		if (((scsiq->q_status & ASC_QS_READY) != 0) &&
+		    ((scsiq->q_status & ASC_QS_ABORTED) == 0) &&
+		    ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) {
+			if (scsiq->d2.target_ix == target_ix) {
+				scsiq->q_status |= ASC_QS_ABORTED;
+				scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST;
+				AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L);
+				AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
+						 scsiq->q_status);
+				(*asc_isr_callback) (sc, scsiq);
+			}
+		}
+	}
+	DvcLeaveCritical(last_int_level);
+	return (1);
+}
+
+
+/*
+ * AscResetDevice calls _AscWaitQDone which requires interrupt enabled,
+ * so we cannot use this function with the actual NetBSD SCSI layer
+ * because at boot time interrupts are disabled.
+ */
+int
+AscResetDevice(sc, target_ix)
+	ASC_SOFTC      *sc;
+	u_char          target_ix;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	int             retval;
+	u_int8_t        tid_no;
+	ASC_SCSI_BIT_ID_TYPE target_id;
+	int             i;
+	ASC_SCSI_REQ_Q  scsiq_buf;
+	ASC_SCSI_REQ_Q *scsiq;
+	u_int8_t       *buf;
+	ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready;
+
+
+	tid_no = ASC_TIX_TO_TID(target_ix);
+	target_id = ASC_TID_TO_TARGET_ID(tid_no);
+	saved_unit_not_ready = sc->unit_not_ready;
+	sc->unit_not_ready = target_id;
+	retval = ASC_ERROR;
+
+	AscWaitTixISRDone(sc, target_ix);
+
+	if (AscStopQueueExe(iot, ioh) == 1) {
+		if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) {
+			AscCleanUpBusyQueue(iot, ioh);
+			AscStartQueueExe(iot, ioh);
+			AscWaitTixISRDone(sc, target_ix);
+			retval = ASC_NOERROR;
+			scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf;
+			buf = (u_char *) & scsiq_buf;
+			for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++)
+				*buf++ = 0x00;
+			scsiq->q1.status = (u_char) ASC_QS_READY;
+			scsiq->q2.cdb_len = 6;
+			scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE;
+			scsiq->q1.target_id = target_id;
+			scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0);
+			scsiq->cdbptr = (u_int8_t *) scsiq->cdb;
+			scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT;
+			AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET);
+			sc->unit_not_ready &= ~target_id;
+			sc->sdtr_done |= target_id;
+			if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) {
+				sc->unit_not_ready = target_id;
+				DvcSleepMilliSecond(1000);
+				_AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq);
+				if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) {
+					AscCleanUpDiscQueue(iot, ioh);
+					AscStartQueueExe(iot, ioh);
+					if (sc->pci_fix_asyn_xfer & target_id)
+						AscSetRunChipSynRegAtID(iot, ioh, tid_no,
+									ASYN_SDTR_DATA_FIX_PCI_REV_AB);
+					AscWaitTixISRDone(sc, target_ix);
+				}
+			} else
+				retval = ASC_BUSY;
+			sc->sdtr_done &= ~target_id;
+		} else {
+			retval = ASC_ERROR;
+			AscStartQueueExe(iot, ioh);
+		}
+	}
+	sc->unit_not_ready = saved_unit_not_ready;
+	return (retval);
+}
+
+
+int
+AscResetBus(sc)
+	ASC_SOFTC      *sc;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	int             retval;
+	int             i;
+
+
+	sc->unit_not_ready = 0xFF;
+	retval = ASC_NOERROR;
+
+	AscWaitISRDone(sc);
+	AscStopQueueExe(iot, ioh);
+	sc->sdtr_done = 0;
+	AscResetChipAndScsiBus(iot, ioh);
+	DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000));
+	AscReInitLram(sc);
+	for (i = 0; i <= ASC_MAX_TID; i++) {
+		sc->cur_dvc_qng[i] = 0;
+		if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i))
+			ASC_SET_CHIP_SYNRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB);
+	}
+
+	ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
+	if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR)
+		retval = ASC_ERROR;
+
+	if (AscStartChip(iot, ioh) == 0)
+		retval = ASC_ERROR;
+
+	AscStartQueueExe(iot, ioh);
+	sc->unit_not_ready = 0;
+	sc->queue_full_or_busy = 0;
+	return (retval);
+}
+
+
+/******************************************************************************/
+/*                            Error Handling routines                         */
+/******************************************************************************/
+
+
+static int
+AscSetLibErrorCode(sc, err_code)
+	ASC_SOFTC      *sc;
+	u_int16_t       err_code;
+{
+	/*
+	 * if(sc->err_code == 0) { sc->err_code = err_code;
+	 	 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W,
+			       err_code);
+	/*
+	 * }
+	 */
+	return (err_code);
+}
+
+
+/******************************************************************************/
+/*                            Handle bugged borads routines                   */
+/******************************************************************************/
+
+
+void
+AscInquiryHandling(sc, tid_no, inq)
+	ASC_SOFTC      *sc;
+	u_int8_t        tid_no;
+	ASC_SCSI_INQUIRY *inq;
+{
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
+	ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
+
+
+	orig_init_sdtr = sc->init_sdtr;
+	orig_use_tagged_qng = sc->use_tagged_qng;
+
+	sc->init_sdtr &= ~tid_bit;
+	sc->can_tagged_qng &= ~tid_bit;
+	sc->use_tagged_qng &= ~tid_bit;
+
+	if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) {
+		if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync)
+			sc->init_sdtr |= tid_bit;
+
+		if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue)
+			if (AscTagQueuingSafe(inq)) {
+				sc->use_tagged_qng |= tid_bit;
+				sc->can_tagged_qng |= tid_bit;
+			}
+	}
+	if (orig_use_tagged_qng != sc->use_tagged_qng) {
+		AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B,
+				 sc->disc_enable);
+		AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B,
+				 sc->use_tagged_qng);
+		AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B,
+				 sc->can_tagged_qng);
+
+		sc->max_dvc_qng[tid_no] =
+			sc->max_tag_qng[tid_no];
+		AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no,
+				 sc->max_dvc_qng[tid_no]);
+	}
+	if (orig_init_sdtr != sc->init_sdtr)
+		AscAsyncFix(sc, tid_no, inq);
+}
+
+
+static int
+AscTagQueuingSafe(inq)
+	ASC_SCSI_INQUIRY *inq;
+{
+	if ((inq->add_len >= 32) &&
+	    (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) &&
+	    (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) {
+		return 0;
+	}
+	return 1;
+}
+
+
+static void
+AscAsyncFix(sc, tid_no, inq)
+	ASC_SOFTC      *sc;
+	u_int8_t        tid_no;
+	ASC_SCSI_INQUIRY *inq;
+{
+	u_int8_t        dvc_type;
+	ASC_SCSI_BIT_ID_TYPE tid_bits;
+
+
+	dvc_type = inq->byte0.peri_dvc_type;
+	tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
+
+	if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) {
+		if (!(sc->init_sdtr & tid_bits)) {
+			if ((dvc_type == SCSI_TYPE_CDROM) &&
+			(AscCompareString(inq->vendor_id, "HP ", 3) == 0)) {
+				sc->pci_fix_asyn_xfer_always |= tid_bits;
+			}
+			sc->pci_fix_asyn_xfer |= tid_bits;
+			if ((dvc_type == SCSI_TYPE_PROC) ||
+			    (dvc_type == SCSI_TYPE_SCANNER)) {
+				sc->pci_fix_asyn_xfer &= ~tid_bits;
+			}
+			if ((dvc_type == SCSI_TYPE_SASD) &&
+			    (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) &&
+			    (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) {
+				sc->pci_fix_asyn_xfer &= ~tid_bits;
+			}
+			if ((dvc_type == SCSI_TYPE_SASD) &&
+			    (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) {
+				sc->pci_fix_asyn_xfer &= ~tid_bits;
+			}
+			if ((dvc_type == SCSI_TYPE_CDROM) &&
+			    (AscCompareString(inq->vendor_id, "NEC	 ", 8) == 0) &&
+			    (AscCompareString(inq->product_id, "CD-ROM DRIVE	", 16) == 0)) {
+				sc->pci_fix_asyn_xfer &= ~tid_bits;
+			}
+			if ((dvc_type == SCSI_TYPE_CDROM) &&
+			    (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) &&
+			    (AscCompareString(inq->product_id, "CDR400", 6) == 0)) {
+				sc->pci_fix_asyn_xfer &= ~tid_bits;
+			}
+			if (sc->pci_fix_asyn_xfer & tid_bits) {
+				AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no,
+					     ASYN_SDTR_DATA_FIX_PCI_REV_AB);
+			}
+		}
+	}
+}
+
+
+/******************************************************************************/
+/*                              Miscellaneous routines                        */
+/******************************************************************************/
+
+
+static int
+AscCompareString(str1, str2, len)
+	u_char         *str1;
+	u_char         *str2;
+	int             len;
+{
+	int             i;
+	int             diff;
+
+	for (i = 0; i < len; i++) {
+		diff = (int) (str1[i] - str2[i]);
+		if (diff != 0)
+			return (diff);
+	}
+
+	return (0);
+}
+
+
+/******************************************************************************/
+/*                            Device oriented routines                        */
+/******************************************************************************/
+
+
+static int
+DvcEnterCritical(void)
+{
+	int             s;
+
+	s = splbio();
+	return (s);
+}
+
+
+static void
+DvcLeaveCritical(s)
+	int             s;
+{
+
+	splx(s);
+}
+
+
+static void
+DvcSleepMilliSecond(n)
+	u_int32_t       n;
+{
+
+	DELAY(n * 1000);
+}
+
+#ifdef UNUSED
+static void
+DvcDelayMicroSecond(n)
+	u_int32_t       n;
+{
+
+	DELAY(n);
+}
+#endif
+
+static void
+DvcDelayNanoSecond(n)
+	u_int32_t       n;
+{
+
+	DELAY((n + 999) / 1000);
+}
+
+
+static u_int32_t
+DvcGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr)
+	ASC_SOFTC      *sc;
+	u_int8_t       *buf_addr;
+	u_int32_t       buf_len;
+	ASC_SG_HEAD    *asc_sg_head_ptr;
+{
+	u_int32_t       buf_size;
+
+	buf_size = buf_len;
+	asc_sg_head_ptr->entry_cnt = 1;
+	asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr;
+	asc_sg_head_ptr->sg_list[0].bytes = buf_size;
+
+	return (buf_size);
+}
+
+
+static void
+DvcPutScsiQ(iot, ioh, s_addr, outbuf, words)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int16_t      *outbuf;
+	int             words;
+{
+	int             i;
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
+	for (i = 0; i < words; i++, outbuf++) {
+		if (i == 2 || i == 10)
+			continue;
+
+		ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *outbuf);
+	}
+}
+
+
+static void
+DvcGetQinfo(iot, ioh, s_addr, inbuf, words)
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int16_t       s_addr;
+	u_int16_t      *inbuf;
+	int             words;
+{
+	int             i;
+
+	ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
+	for (i = 0; i < words; i++, inbuf++) {
+		if (i == 5)
+			continue;
+
+		*inbuf = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh);
+	}
+}
diff --git a/sys/dev/ic/advlib.h b/sys/dev/ic/advlib.h
new file mode 100644
index 00000000000..7a05077569c
--- /dev/null
+++ b/sys/dev/ic/advlib.h
@@ -0,0 +1,1318 @@
+/*	$OpenBSD: advlib.h,v 1.1 1998/09/27 03:36:14 downsj Exp $	*/
+/*      $NetBSD: advlib.h,v 1.2 1998/08/29 13:45:57 dante Exp $        */
+
+/*
+ * Definitions for low level routines and data structures
+ * for the Advanced Systems Inc. SCSI controllers chips.
+ *
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Author: Baldassare Dante Profeta <dante@mclink.it>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    This product includes software developed by the NetBSD
+ *    Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Ported from:
+ */
+/*
+ * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
+ *     
+ * Copyright (c) 1995-1996 Advanced System Products, Inc.
+ * All Rights Reserved.
+ *   
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that redistributions of source
+ * code retain the above copyright notice and this comment without
+ * modification.
+ */
+
+#ifndef	_ADVANSYS_LIBRARY_H_
+#define	_ADVANSYS_LIBRARY_H_
+
+#include <dev/ic/adv.h>
+
+/******************************************************************************/
+
+#define ADV_VERSION	"3.1E"		/* AdvanSys Driver Version */
+
+#define ASC_LIB_VERSION_MAJOR  1
+#define ASC_LIB_VERSION_MINOR  22
+#define ASC_LIB_SERIAL_NUMBER  113
+
+
+#define ASC_NOERROR	1
+#define ASC_BUSY	0
+#define ASC_ERROR	-1
+
+
+#define HI_BYTE(x)	(*((__u8 *)(&x)+1))
+#define LO_BYTE(x)	(*((__u8 *)&x))
+#define HI_WORD(x)	(*((__u16 *)(&x)+1))
+#define LO_WORD(x)	(*((__u16 *)&x))
+#ifndef MAKEWORD
+#define MAKEWORD(lo, hi)	((__u16) (((__u16) lo) | ((__u16) hi << 8)))
+#endif
+#ifndef MAKELONG
+#define MAKELONG(lo, hi)	((__u32) (((__u32) lo) | ((__u32) hi << 16)))
+#endif
+#define SwapWords(dWord)	((__u32) ((dWord >> 16) | (dWord << 16)))
+#define SwapBytes(word)		((__u16) ((word >> 8) | (word << 8)))
+#define BigToLittle(dWord)	((__u32) (SwapWords(MAKELONG(SwapBytes(LO_WORD(dWord)), SwapBytes(HI_WORD(dWord))))))
+#define LittleToBig(dWord)	BigToLittle(dWord)
+
+
+#define ASC_PCI_ID2BUS(id)	((id) & 0xFF)
+#define ASC_PCI_ID2DEV(id)	(((id) >> 11) & 0x1F)
+#define ASC_PCI_ID2FUNC(id)	(((id) >> 8) & 0x7)
+#define ASC_PCI_MKID(bus, dev, func)	((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
+#define ASC_PCI_REVISION_3150	0x02
+#define ASC_PCI_REVISION_3050	0x03
+
+
+#define ASC_IS_NARROW_BOARD(sc) (((sc)->sc_flags & ASC_WIDE_BOARD) == 0)
+#define ASC_IS_WIDE_BOARD(sc)   ((sc)->sc_flags & ASC_WIDE_BOARD)
+
+
+#define ASC_MAX_SG_QUEUE	7
+#define ASC_SG_LIST_PER_Q 	ASC_MAX_SG_QUEUE
+#define ASC_MAX_SG_LIST		(1 + ((ASC_SG_LIST_PER_Q) * (ASC_MAX_SG_QUEUE))) /* SG_ALL */
+
+
+#define ASC_IS_ISA		0x0001
+#define ASC_IS_ISAPNP		0x0081
+#define ASC_IS_EISA		0x0002
+#define ASC_IS_PCI		0x0004
+#define ASC_IS_PCI_ULTRA	0x0104
+#define ASC_IS_PCMCIA		0x0008
+#define ASC_IS_MCA		0x0020
+#define ASC_IS_VL		0x0040
+
+
+#define ASC_ISA_PNP_PORT_ADDR	0x279
+#define ASC_ISA_PNP_PORT_WRITE	(ASC_ISA_PNP_PORT_ADDR+0x800)
+
+#define ASC_IS_WIDESCSI_16	0x0100
+#define ASC_IS_WIDESCSI_32	0x0200
+#define ASC_IS_BIG_ENDIAN	0x8000
+
+
+#define ASC_CHIP_MIN_VER_VL		0x01
+#define ASC_CHIP_MAX_VER_VL		0x07
+#define ASC_CHIP_MIN_VER_PCI		0x09
+#define ASC_CHIP_MAX_VER_PCI		0x0F
+#define ASC_CHIP_VER_PCI_BIT		0x08
+#define ASC_CHIP_MIN_VER_ISA		0x11
+#define ASC_CHIP_MIN_VER_ISA_PNP	0x21
+#define ASC_CHIP_MAX_VER_ISA		0x27
+#define ASC_CHIP_VER_ISA_BIT		0x30
+#define ASC_CHIP_VER_ISAPNP_BIT		0x20
+#define ASC_CHIP_VER_ASYN_BUG		0x21
+#define ASC_CHIP_VER_PCI		0x08
+#define ASC_CHIP_VER_PCI_ULTRA_3150	(ASC_CHIP_VER_PCI | 0x02)
+#define ASC_CHIP_VER_PCI_ULTRA_3050	(ASC_CHIP_VER_PCI | 0x03)
+#define ASC_CHIP_MIN_VER_EISA		0x41
+#define ASC_CHIP_MAX_VER_EISA		0x47
+#define ASC_CHIP_VER_EISA_BIT		0x40
+#define ASC_CHIP_LATEST_VER_EISA	((ASC_CHIP_MIN_VER_EISA - 1) + 3)
+
+
+#define ASC_MAX_VL_DMA_ADDR	0x07FFFFFFL
+#define ASC_MAX_VL_DMA_COUNT	0x07FFFFFFL
+#define ASC_MAX_PCI_DMA_ADDR	0xFFFFFFFFL
+#define ASC_MAX_PCI_DMA_COUNT	0xFFFFFFFFL
+#define ASC_MAX_ISA_DMA_ADDR	0x00FFFFFFL
+#define ASC_MAX_ISA_DMA_COUNT	0x00FFFFFFL
+#define ASC_MAX_EISA_DMA_ADDR	0x07FFFFFFL
+#define ASC_MAX_EISA_DMA_COUNT	0x07FFFFFFL
+
+
+#define ASC_SCSI_ID_BITS	3
+#define ASC_SCSI_TIX_TYPE	u_int8_t
+
+#define ASC_ALL_DEVICE_BIT_SET	0xFF
+
+#ifdef ASC_WIDESCSI_16
+#undef  ASC_SCSI_ID_BITS
+#define ASC_SCSI_ID_BITS	4
+#define ASC_ALL_DEVICE_BIT_SET	0xFFFF
+#endif
+
+#ifdef ASC_WIDESCSI_32
+#undef  ASC_SCSI_ID_BITS
+#define ASC_SCSI_ID_BITS	5
+#define ASC_ALL_DEVICE_BIT_SET	0xFFFFFFFFL
+#endif
+
+#if ASC_SCSI_ID_BITS == 3
+#define ASC_SCSI_BIT_ID_TYPE	u_int8_t
+#define ASC_MAX_TID		7
+#define ASC_MAX_LUN		7
+#define ASC_SCSI_WIDTH_BIT_SET	0xFF
+#elif ASC_SCSI_ID_BITS == 4
+#define ASC_SCSI_BIT_ID_TYPE	u_int16_t
+#define ASC_MAX_TID		15
+#define ASC_MAX_LUN		7
+#define ASC_SCSI_WIDTH_BIT_SET	0xFFFF
+#elif ASC_SCSI_ID_BITS == 5
+#define ASC_SCSI_BIT_ID_TYPE	u_int32_t
+#define ASC_MAX_TID		31
+#define ASC_MAX_LUN		7
+#define ASC_SCSI_WIDTH_BIT_SET	0xFFFFFFFF
+#else
+#error  ASC_SCSI_ID_BITS definition is wrong
+#endif
+
+
+#define ASC_MAX_SENSE_LEN	32
+#define ASC_MIN_SENSE_LEN	14
+#define ASC_MAX_CDB_LEN		12
+
+#define ASC_SCSI_RESET_HOLD_TIME_US  60
+
+
+#define SCSICMD_TestUnitReady		0x00
+#define SCSICMD_Rewind			0x01
+#define SCSICMD_Rezero			0x01
+#define SCSICMD_RequestSense		0x03
+#define SCSICMD_Format			0x04
+#define SCSICMD_FormatUnit		0x04
+#define SCSICMD_Read6			0x08
+#define SCSICMD_Write6			0x0A
+#define SCSICMD_Seek6			0x0B
+#define SCSICMD_Inquiry			0x12
+#define SCSICMD_Verify6			0x13
+#define SCSICMD_ModeSelect6		0x15
+#define SCSICMD_ModeSense6		0x1A
+#define SCSICMD_StartStopUnit		0x1B
+#define SCSICMD_LoadUnloadTape		0x1B
+#define SCSICMD_ReadCapacity		0x25
+#define SCSICMD_Read10			0x28
+#define SCSICMD_Write10			0x2A
+#define SCSICMD_Seek10			0x2B
+#define SCSICMD_Erase10			0x2C
+#define SCSICMD_WriteAndVerify10	0x2E
+#define SCSICMD_Verify10		0x2F
+#define SCSICMD_WriteBuffer		0x3B
+#define SCSICMD_ReadBuffer		0x3C
+#define SCSICMD_ReadLong		0x3E
+#define SCSICMD_WriteLong		0x3F
+#define SCSICMD_ReadTOC			0x43
+#define SCSICMD_ReadHeader		0x44
+#define SCSICMD_ModeSelect10		0x55
+#define SCSICMD_ModeSense10		0x5A
+
+
+#define SCSI_TYPE_DASD		0x00
+#define SCSI_TYPE_SASD		0x01
+#define SCSI_TYPE_PRN		0x02
+#define SCSI_TYPE_PROC		0x03
+#define SCSI_TYPE_WORM		0x04
+#define SCSI_TYPE_CDROM		0x05
+#define SCSI_TYPE_SCANNER	0x06
+#define SCSI_TYPE_OPTMEM	0x07
+#define SCSI_TYPE_MED_CHG	0x08
+#define SCSI_TYPE_COMM		0x09
+#define SCSI_TYPE_UNKNOWN	0x1F
+#define SCSI_TYPE_NO_DVC	0xFF
+
+
+#define ASC_SCSIDIR_NOCHK	0x00
+#define ASC_SCSIDIR_T2H		0x08
+#define ASC_SCSIDIR_H2T		0x10
+#define ASC_SCSIDIR_NODATA	0x18
+
+
+#define SCSI_SENKEY_NO_SENSE		0x00
+#define SCSI_SENKEY_UNDEFINED		0x01
+#define SCSI_SENKEY_NOT_READY		0x02
+#define SCSI_SENKEY_MEDIUM_ERR		0x03
+#define SCSI_SENKEY_HW_ERR		0x04
+#define SCSI_SENKEY_ILLEGAL		0x05
+#define SCSI_SENKEY_ATTENTION		0x06
+#define SCSI_SENKEY_PROTECTED		0x07
+#define SCSI_SENKEY_BLANK		0x08
+#define SCSI_SENKEY_V_UNIQUE		0x09
+#define SCSI_SENKEY_CPY_ABORT		0x0A
+#define SCSI_SENKEY_ABORT		0x0B
+#define SCSI_SENKEY_EQUAL		0x0C
+#define SCSI_SENKEY_VOL_OVERFLOW	0x0D
+#define SCSI_SENKEY_MISCOMP		0x0E
+#define SCSI_SENKEY_RESERVED		0x0F
+#define SCSI_ASC_NOMEDIA		0x3A
+
+
+#define ASC_CCB_HOST(x)  ((u_int8_t)((u_int8_t)(x) >> 4))
+#define ASC_CCB_TID(x)   ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F))
+#define ASC_CCB_LUN(x)   ((u_int8_t)((uint)(x) >> 13))
+
+
+#define SS_GOOD				0x00
+#define SS_CHK_CONDITION		0x02
+#define SS_CONDITION_MET		0x04
+#define SS_TARGET_BUSY			0x08
+#define SS_INTERMID			0x10
+#define SS_INTERMID_COND_MET		0x14
+#define SS_RSERV_CONFLICT		0x18
+#define SS_CMD_TERMINATED		0x22
+#define SS_QUEUE_FULL			0x28
+
+
+#define MS_CMD_DONE			0x00
+#define MS_EXTEND			0x01
+#define MS_SDTR_LEN			0x03
+#define MS_SDTR_CODE			0x01
+#define MS_WDTR_LEN			0x02
+#define MS_WDTR_CODE			0x03
+#define MS_MDP_LEN			0x05
+#define MS_MDP_CODE			0x00
+
+
+#define M1_SAVE_DATA_PTR		0x02
+#define M1_RESTORE_PTRS			0x03
+#define M1_DISCONNECT			0x04
+#define M1_INIT_DETECTED_ERR		0x05
+#define M1_ABORT			0x06
+#define M1_MSG_REJECT			0x07
+#define M1_NO_OP			0x08
+#define M1_MSG_PARITY_ERR		0x09
+#define M1_LINK_CMD_DONE		0x0A
+#define M1_LINK_CMD_DONE_WFLAG		0x0B
+#define M1_BUS_DVC_RESET		0x0C
+#define M1_ABORT_TAG			0x0D
+#define M1_CLR_QUEUE			0x0E
+#define M1_INIT_RECOVERY		0x0F
+#define M1_RELEASE_RECOVERY		0x10
+#define M1_KILL_IO_PROC			0x11
+#define M2_QTAG_MSG_SIMPLE		0x20
+#define M2_QTAG_MSG_HEAD		0x21
+#define M2_QTAG_MSG_ORDERED		0x22
+#define M2_IGNORE_WIDE_RESIDUE		0x23
+
+
+/*
+ * SCSI Iquiry structure
+ */
+
+typedef struct
+{
+	u_int8_t	peri_dvc_type:5;
+	u_int8_t	peri_qualifier:3;
+} ASC_SCSI_INQ0;
+
+typedef struct
+{
+	u_int8_t	dvc_type_modifier:7;
+	u_int8_t	rmb:1;
+} ASC_SCSI_INQ1;
+
+typedef struct
+{
+	u_int8_t	ansi_apr_ver:3;
+	u_int8_t	ecma_ver:3;
+	u_int8_t	iso_ver:2;
+} ASC_SCSI_INQ2;
+
+typedef struct
+{
+	u_int8_t	rsp_data_fmt:4;
+	u_int8_t	res:2;
+	u_int8_t	TemIOP:1;
+	u_int8_t	aenc:1;
+} ASC_SCSI_INQ3;
+
+typedef struct
+{
+	u_int8_t	StfRe:1;
+	u_int8_t	CmdQue:1;
+	u_int8_t	Reserved:1;
+	u_int8_t	Linked:1;
+	u_int8_t	Sync:1;
+	u_int8_t	WBus16:1;
+	u_int8_t	WBus32:1;
+	u_int8_t	RelAdr:1;
+} ASC_SCSI_INQ7;
+
+typedef struct
+{
+	ASC_SCSI_INQ0	byte0;
+	ASC_SCSI_INQ1	byte1;
+	ASC_SCSI_INQ2	byte2;
+	ASC_SCSI_INQ3	byte3;
+	u_int8_t	add_len;
+	u_int8_t	res1;
+	u_int8_t	res2;
+	ASC_SCSI_INQ7	byte7;
+	u_int8_t	vendor_id[8];
+	u_int8_t	product_id[16];
+	u_int8_t	product_rev_level[4];
+} ASC_SCSI_INQUIRY;
+
+
+/*
+ * SCSIQ Microcode offsets
+ */
+#define ASC_SCSIQ_CPY_BEG		 4
+#define ASC_SCSIQ_SGHD_CPY_BEG		 2
+#define ASC_SCSIQ_B_FWD			 0
+#define ASC_SCSIQ_B_BWD			 1
+#define ASC_SCSIQ_B_STATUS		 2
+#define ASC_SCSIQ_B_QNO			 3
+#define ASC_SCSIQ_B_CNTL		 4
+#define ASC_SCSIQ_B_SG_QUEUE_CNT	 5
+#define ASC_SCSIQ_D_DATA_ADDR		 8
+#define ASC_SCSIQ_D_DATA_CNT		12
+#define ASC_SCSIQ_B_SENSE_LEN		20
+#define ASC_SCSIQ_DONE_INFO_BEG		22
+#define ASC_SCSIQ_D_CCBPTR		22
+#define ASC_SCSIQ_B_TARGET_IX		26
+#define ASC_SCSIQ_B_CDB_LEN		28
+#define ASC_SCSIQ_B_TAG_CODE		29
+#define ASC_SCSIQ_W_VM_ID		30
+#define ASC_SCSIQ_DONE_STATUS		32
+#define ASC_SCSIQ_HOST_STATUS		33
+#define ASC_SCSIQ_SCSI_STATUS		34
+#define ASC_SCSIQ_CDB_BEG		36
+#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR	56
+#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 	60
+#define ASC_SCSIQ_B_SG_WK_QP		49
+#define ASC_SCSIQ_B_SG_WK_IX		50
+#define ASC_SCSIQ_W_REQ_COUNT		52
+#define ASC_SCSIQ_B_LIST_CNT		 6
+#define ASC_SCSIQ_B_CUR_LIST_CNT	 7
+
+
+#define ASC_DEF_SCSI1_QNG	4
+#define ASC_MAX_SCSI1_QNG	4
+#define ASC_DEF_SCSI2_QNG	16
+#define ASC_MAX_SCSI2_QNG	32
+
+#define ASC_TAG_CODE_MASK	0x23
+
+#define ASC_STOP_REQ_RISC_STOP		0x01
+#define ASC_STOP_ACK_RISC_STOP		0x03
+#define ASC_STOP_CLEAN_UP_BUSY_Q	0x10
+#define ASC_STOP_CLEAN_UP_DISC_Q	0x20
+#define ASC_STOP_HOST_REQ_RISC_HALT	0x40
+
+#define ASC_TIDLUN_TO_IX(tid, lun)	(ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
+#define ASC_TID_TO_TARGET_ID(tid)	(ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
+#define ASC_TIX_TO_TARGET_ID(tix)	(0x01 << ((tix) & ASC_MAX_TID))
+#define ASC_TIX_TO_TID(tix)		((tix) & ASC_MAX_TID)
+#define ASC_TID_TO_TIX(tid)		((tid) & ASC_MAX_TID)
+#define ASC_TIX_TO_LUN(tix)		(((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
+#define ASC_QNO_TO_QADDR(q_no)		((ASC_QADR_BEG)+((int)(q_no) << 6))
+
+
+/*
+ * Structures used to dialog with the RISC engine
+ */
+
+typedef struct asc_scisq_1
+{
+	u_int8_t	status;	/* see below status values */
+	u_int8_t	q_no;	/* Queue ID of the first queue for this transaction */
+	u_int8_t	cntl;	/* see below cntl values */
+	u_int8_t	sg_queue_cnt;	/* number of SG entries */
+	u_int8_t	target_id;
+	u_int8_t	target_lun;
+	u_int32_t	data_addr; /* physical address of first segment to transef */
+	u_int32_t	data_cnt;  /* byte count of first segment to transfer */
+	u_int32_t	sense_addr; /* physical address of the sense buffer */
+	u_int8_t	sense_len; /* lenght of sense buffer */
+	u_int8_t	extra_bytes;
+} ASC_SCSIQ_1;
+
+/* status values */
+#define ASC_QS_FREE		0x00
+#define ASC_QS_READY		0x01
+#define ASC_QS_DISC1		0x02
+#define ASC_QS_DISC2		0x04
+#define ASC_QS_BUSY		0x08
+#define ASC_QS_ABORTED		0x40
+#define ASC_QS_DONE		0x80
+
+/* cntl values */
+#define ASC_QC_NO_CALLBACK	0x01
+#define ASC_QC_SG_SWAP_QUEUE	0x02
+#define ASC_QC_SG_HEAD		0x04
+#define ASC_QC_DATA_IN		0x08
+#define ASC_QC_DATA_OUT		0x10
+#define ASC_QC_URGENT		0x20
+#define ASC_QC_MSG_OUT		0x40
+#define ASC_QC_REQ_SENSE	0x80
+
+
+typedef struct asc_scisq_2
+{
+	u_int32_t	ccb_ptr;	/* pointer to our CCB */
+	u_int8_t	target_ix;	/* combined TID and LUN */
+	u_int8_t	flag;
+	u_int8_t	cdb_len;	/* bytes of Command Descriptor Block */
+	u_int8_t	tag_code;	/* type of this transaction. see below */
+	u_int16_t	vm_id;
+} ASC_SCSIQ_2;
+
+/* tag_code values */
+#define ASC_TAG_FLAG_EXTRA_BYTES		0x10
+#define ASC_TAG_FLAG_DISABLE_DISCONNECT		0x04
+#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX	0x08
+#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST	0x40
+
+
+typedef struct asc_scsiq_3
+{
+	u_int8_t	done_stat;	/* see below done_stat values */
+	u_int8_t	host_stat;	/* see below host_stat values */
+	u_int8_t	scsi_stat;
+	u_int8_t	scsi_msg;
+} ASC_SCSIQ_3;
+
+/* done_stat values */
+#define ASC_QD_IN_PROGRESS		0x00
+#define ASC_QD_NO_ERROR			0x01
+#define ASC_QD_ABORTED_BY_HOST		0x02
+#define ASC_QD_WITH_ERROR		0x04
+#define ASC_QD_INVALID_REQUEST		0x80
+#define ASC_QD_INVALID_HOST_NUM		0x81
+#define ASC_QD_INVALID_DEVICE		0x82
+#define ASC_QD_ERR_INTERNAL		0xFF
+
+/* host_stat values */
+#define ASC_QHSTA_NO_ERROR			0x00
+#define ASC_QHSTA_M_SEL_TIMEOUT			0x11
+#define ASC_QHSTA_M_DATA_OVER_RUN		0x12
+#define ASC_QHSTA_M_DATA_UNDER_RUN		0x12
+#define ASC_QHSTA_M_UNEXPECTED_BUS_FREE		0x13
+#define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ		0x14
+#define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED	0x21
+#define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET	0x22
+#define ASC_QHSTA_D_HOST_ABORT_FAILED		0x23
+#define ASC_QHSTA_D_EXE_SCSI_Q_FAILED		0x24
+#define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT	0x25
+#define ASC_QHSTA_D_ASPI_NO_BUF_POOL		0x26
+#define ASC_QHSTA_M_WTM_TIMEOUT			0x41
+#define ASC_QHSTA_M_BAD_CMPL_STATUS_IN		0x42
+#define ASC_QHSTA_M_NO_AUTO_REQ_SENSE		0x43
+#define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL		0x44
+#define ASC_QHSTA_M_TARGET_STATUS_BUSY		0x45
+#define ASC_QHSTA_M_BAD_TAG_CODE		0x46
+#define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY	0x47
+#define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET	0x48
+#define ASC_QHSTA_D_LRAM_CMP_ERROR		0x81
+#define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT	0xA1
+
+
+typedef struct asc_scsiq_4
+{
+	u_int8_t	cdb[ASC_MAX_CDB_LEN];
+	u_int8_t	y_first_sg_list_qp;
+	u_int8_t	y_working_sg_qp;
+	u_int8_t	y_working_sg_ix;
+	u_int8_t	y_res;
+	u_int16_t	x_req_count;
+	u_int16_t	x_reconnect_rtn;
+	u_int32_t	x_saved_data_addr;
+	u_int32_t	x_saved_data_cnt;
+} ASC_SCSIQ_4;
+
+typedef struct asc_q_done_info
+{
+	ASC_SCSIQ_2	d2;
+	ASC_SCSIQ_3	d3;
+	u_int8_t	q_status;
+	u_int8_t	q_no;
+	u_int8_t	cntl;
+	u_int8_t	sense_len;
+	u_int8_t	extra_bytes;
+	u_int8_t	res;
+	u_int32_t	remain_bytes;
+} ASC_QDONE_INFO;
+
+typedef struct asc_sg_list
+{
+	u_int32_t	addr;
+	u_int32_t	bytes;
+} ASC_SG_LIST;
+
+typedef struct asc_sg_head
+{
+	u_int16_t	entry_cnt;	/* number of SG entries */
+	u_int16_t	queue_cnt;	/* number of queues required to store SG entries */
+	u_int16_t	entry_to_copy;	/* number of SG entries to copy to the board */
+	u_int16_t	res;
+	ASC_SG_LIST	sg_list[ASC_MAX_SG_LIST];
+} ASC_SG_HEAD;
+
+#define ASC_MIN_SG_LIST   2
+
+typedef struct asc_min_sg_head
+{
+	u_int16_t	entry_cnt;
+	u_int16_t	queue_cnt;
+	u_int16_t	entry_to_copy;
+	u_int16_t	res;
+	ASC_SG_LIST	sg_list[ASC_MIN_SG_LIST];
+} ASC_MIN_SG_HEAD;
+
+#define ASC_QCX_SORT		0x0001
+#define ASC_QCX_COALEASE	0x0002
+
+typedef struct asc_scsi_q
+{
+	ASC_SCSIQ_1	q1;
+	ASC_SCSIQ_2	q2;
+	u_int8_t	*cdbptr;	/* pointer to CDB to execute */
+	ASC_SG_HEAD	*sg_head;	/* pointer to SG list */
+} ASC_SCSI_Q;
+
+typedef struct asc_scsi_req_q
+{
+	ASC_SCSIQ_1	q1;
+	ASC_SCSIQ_2	q2;
+	u_int8_t	*cdbptr;
+	ASC_SG_HEAD	*sg_head;
+	u_int8_t	*sense_ptr;
+	ASC_SCSIQ_3	q3;
+	u_int8_t	cdb[ASC_MAX_CDB_LEN];
+	u_int8_t	sense[ASC_MIN_SENSE_LEN];
+} ASC_SCSI_REQ_Q;
+
+typedef struct asc_scsi_bios_req_q
+{
+	ASC_SCSIQ_1	q1;
+	ASC_SCSIQ_2	q2;
+	u_int8_t	*cdbptr;
+	ASC_SG_HEAD	*sg_head;
+	u_int8_t	*sense_ptr;
+	ASC_SCSIQ_3	q3;
+	u_int8_t	cdb[ASC_MAX_CDB_LEN];
+	u_int8_t	sense[ASC_MIN_SENSE_LEN];
+} ASC_SCSI_BIOS_REQ_Q;
+
+typedef struct asc_risc_q
+{
+	u_int8_t	fwd;
+	u_int8_t	bwd;
+	ASC_SCSIQ_1	i1;
+	ASC_SCSIQ_2	i2;
+	ASC_SCSIQ_3	i3;
+	ASC_SCSIQ_4	i4;
+} ASC_RISC_Q;
+
+typedef struct asc_sg_list_q
+{
+	u_int8_t	seq_no;
+	u_int8_t	q_no;
+	u_int8_t	cntl;		/* see below cntl values */
+	u_int8_t	sg_head_qp;
+	u_int8_t	sg_list_cnt;
+	u_int8_t	sg_cur_list_cnt;
+} ASC_SG_LIST_Q;
+
+/* cntl values */
+#define ASC_QCSG_SG_XFER_LIST	0x02
+#define ASC_QCSG_SG_XFER_MORE	0x04
+#define ASC_QCSG_SG_XFER_END	0x08
+
+#define ASC_SGQ_B_SG_CNTL		4
+#define ASC_SGQ_B_SG_HEAD_QP		5
+#define ASC_SGQ_B_SG_LIST_CNT		6
+#define ASC_SGQ_B_SG_CUR_LIST_CNT	7
+#define ASC_SGQ_LIST_BEG		8
+
+
+typedef struct asc_risc_sg_list_q
+{
+	u_int8_t	fwd;
+	u_int8_t	bwd;
+	ASC_SG_LIST_Q	sg;
+	ASC_SG_LIST	sg_list[7];
+} ASC_RISC_SG_LIST_Q;
+
+
+#define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP  0x1000000UL
+#define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP  1024
+
+#define ASCQ_ERR_NO_ERROR		0x00
+#define ASCQ_ERR_IO_NOT_FOUND		0x01
+#define ASCQ_ERR_LOCAL_MEM		0x02
+#define ASCQ_ERR_CHKSUM			0x03
+#define ASCQ_ERR_START_CHIP		0x04
+#define ASCQ_ERR_INT_TARGET_ID		0x05
+#define ASCQ_ERR_INT_LOCAL_MEM		0x06
+#define ASCQ_ERR_HALT_RISC		0x07
+#define ASCQ_ERR_GET_ASPI_ENTRY		0x08
+#define ASCQ_ERR_CLOSE_ASPI		0x09
+#define ASCQ_ERR_HOST_INQUIRY		0x0A
+#define ASCQ_ERR_SAVED_CCB_BAD		0x0B
+#define ASCQ_ERR_QCNTL_SG_LIST		0x0C
+#define ASCQ_ERR_Q_STATUS		0x0D
+#define ASCQ_ERR_WR_SCSIQ		0x0E
+#define ASCQ_ERR_PC_ADDR		0x0F
+#define ASCQ_ERR_SYN_OFFSET		0x10
+#define ASCQ_ERR_SYN_XFER_TIME		0x11
+#define ASCQ_ERR_LOCK_DMA		0x12
+#define ASCQ_ERR_UNLOCK_DMA		0x13
+#define ASCQ_ERR_VDS_CHK_INSTALL	0x14
+#define ASCQ_ERR_MICRO_CODE_HALT	0x15
+#define ASCQ_ERR_SET_LRAM_ADDR		0x16
+#define ASCQ_ERR_CUR_QNG		0x17
+#define ASCQ_ERR_SG_Q_LINKS		0x18
+#define ASCQ_ERR_SCSIQ_PTR		0x19
+#define ASCQ_ERR_ISR_RE_ENTRY		0x1A
+#define ASCQ_ERR_CRITICAL_RE_ENTRY	0x1B
+#define ASCQ_ERR_ISR_ON_CRITICAL	0x1C
+#define ASCQ_ERR_SG_LIST_ODD_ADDRESS	0x1D
+#define ASCQ_ERR_XFER_ADDRESS_TOO_BIG	0x1E
+#define ASCQ_ERR_SCSIQ_NULL_PTR		0x1F
+#define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 	0x20
+#define ASCQ_ERR_GET_NUM_OF_FREE_Q	0x21
+#define ASCQ_ERR_SEND_SCSI_Q		0x22
+#define ASCQ_ERR_HOST_REQ_RISC_HALT 	0x23
+#define ASCQ_ERR_RESET_SDTR		0x24
+
+#define ASC_WARN_NO_ERROR		0x0000
+#define ASC_WARN_IO_PORT_ROTATE		0x0001
+#define ASC_WARN_EEPROM_CHKSUM		0x0002
+#define ASC_WARN_IRQ_MODIFIED		0x0004
+#define ASC_WARN_AUTO_CONFIG		0x0008
+#define ASC_WARN_CMD_QNG_CONFLICT	0x0010
+#define ASC_WARN_EEPROM_RECOVER		0x0020
+#define ASC_WARN_CFG_MSW_RECOVER	0x0040
+#define ASC_WARN_SET_PCI_CONFIG_SPACE	0x0080
+
+#define ASC_IERR_WRITE_EEPROM		0x0001
+#define ASC_IERR_MCODE_CHKSUM		0x0002
+#define ASC_IERR_SET_PC_ADDR		0x0004
+#define ASC_IERR_START_STOP_CHIP	0x0008
+#define ASC_IERR_IRQ_NO			0x0010
+#define ASC_IERR_SET_IRQ_NO		0x0020
+#define ASC_IERR_CHIP_VERSION		0x0040
+#define ASC_IERR_SET_SCSI_ID		0x0080
+#define ASC_IERR_GET_PHY_ADDR		0x0100
+#define ASC_IERR_BAD_SIGNATURE		0x0200
+#define ASC_IERR_NO_BUS_TYPE		0x0400
+#define ASC_IERR_SCAM			0x0800
+#define ASC_IERR_SET_SDTR		0x1000
+#define ASC_IERR_RW_LRAM		0x8000
+
+#define ASC_DEF_IRQ_NO			10
+#define ASC_MAX_IRQ_NO			15
+#define ASC_MIN_IRQ_NO			10
+#define ASC_MIN_REMAIN_Q		0x02
+#define ASC_DEF_MAX_TOTAL_QNG   0xF0
+#define ASC_MIN_TAG_Q_PER_DVC   0x04
+#define ASC_DEF_TAG_Q_PER_DVC   0x04
+#define ASC_MIN_FREE_Q		ASC_MIN_REMAIN_Q
+#define ASC_MIN_TOTAL_QNG	((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
+#define ASC_MAX_TOTAL_QNG	240
+#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG	16
+#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG		8
+#define ASC_MAX_PCI_INRAM_TOTAL_QNG		20
+#define ASC_MAX_INRAM_TAG_QNG	16
+#define ASC_IOADR_TABLE_MAX_IX	11
+#define ASC_IOADR_GAP			0x10
+#define ASC_SEARCH_IOP_GAP		0x10
+#define ASC_MIN_IOP_ADDR		0x0100
+#define ASC_MAX_IOP_ADDR		0x03F0
+
+#define ASC_IOADR_1			0x0110
+#define ASC_IOADR_2			0x0130
+#define ASC_IOADR_3			0x0150
+#define ASC_IOADR_4			0x0190
+#define ASC_IOADR_5			0x0210
+#define ASC_IOADR_6			0x0230
+#define ASC_IOADR_7			0x0250
+#define ASC_IOADR_8			0x0330
+
+#define ASC_IOADR_DEF			ASC_IOADR_8
+#define ASC_LIB_SCSIQ_WK_SP		256
+#define ASC_MAX_SYN_XFER_NO		16
+#define ASC_SYN_MAX_OFFSET		0x0F
+#define ASC_DEF_SDTR_OFFSET		0x0F
+#define ASC_DEF_SDTR_INDEX		0x00
+#define ASC_SDTR_ULTRA_PCI_10MB_INDEX	0x02
+
+
+/*
+ * This structure is used to handle internal messages
+ * during interrupt handling routine
+ */
+typedef struct ext_msg
+{
+	u_int8_t	msg_type;
+	u_int8_t	msg_len;
+	u_int8_t	msg_req;
+
+	union
+	{
+		struct
+		{
+			u_int8_t	sdtr_xfer_period;
+			u_int8_t	sdtr_req_ack_offset;
+		} sdtr;
+
+		struct
+		{
+			u_int8_t	wdtr_width;
+		} wdtr;
+
+		struct
+		{
+			u_int8_t	mdp_b3;
+			u_int8_t	mdp_b2;
+			u_int8_t	mdp_b1;
+			u_int8_t	mdp_b0;
+		} mdp;
+	} u_ext_msg;
+
+	u_int8_t	res;
+} EXT_MSG;
+
+#define xfer_period	u_ext_msg.sdtr.sdtr_xfer_period
+#define req_ack_offset	u_ext_msg.sdtr.sdtr_req_ack_offset
+#define wdtr_width	u_ext_msg.wdtr.wdtr_width
+#define mdp_b3		u_ext_msg.mdp_b3
+#define mdp_b2		u_ext_msg.mdp_b2
+#define mdp_b1		u_ext_msg.mdp_b1
+#define mdp_b0		u_ext_msg.mdp_b0
+
+
+#define ASC_DEF_DVC_CNTL		0xFFFF
+#define ASC_DEF_CHIP_SCSI_ID		7
+#define ASC_DEF_ISA_DMA_SPEED		4
+
+#define ASC_PCI_DEVICE_ID_REV_A		0x1100
+#define ASC_PCI_DEVICE_ID_REV_B		0x1200
+
+#define ASC_BUG_FIX_IF_NOT_DWB		0x0001
+#define ASC_BUG_FIX_ASYN_USE_SYN	0x0002
+
+#define ASYN_SDTR_DATA_FIX_PCI_REV_AB	0x41
+
+#define ASC_MIN_TAGGED_CMD	7
+
+#define ASC_MAX_SCSI_RESET_WAIT	30
+
+
+typedef struct asc_softc
+{
+	struct device		sc_dev;
+
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	bus_dma_tag_t		sc_dmat;
+	bus_dmamap_t		sc_dmamap_control; /* maps the control structures */
+	void			*sc_ih;
+
+	struct adv_control	*sc_control; /* control structures */
+	TAILQ_HEAD(, adv_ccb)	sc_free_ccb, sc_waiting_ccb;
+	struct scsi_link	sc_link;     /* prototype for devs */
+
+	LIST_HEAD(, scsi_xfer)	sc_queue;
+	struct scsi_xfer	*sc_queuelast;
+
+	u_int8_t		*overrun_buf;
+
+	u_int16_t		sc_flags;	/* see below sc_flags values */
+
+	u_int16_t		dvc_cntl;
+	u_int16_t		bug_fix_cntl;
+	u_int16_t		bus_type;
+
+	ulong			isr_callback;
+
+	ASC_SCSI_BIT_ID_TYPE	init_sdtr;
+	ASC_SCSI_BIT_ID_TYPE	sdtr_done;
+	ASC_SCSI_BIT_ID_TYPE	use_tagged_qng;
+	ASC_SCSI_BIT_ID_TYPE	unit_not_ready;
+	ASC_SCSI_BIT_ID_TYPE	queue_full_or_busy;
+	ASC_SCSI_BIT_ID_TYPE	start_motor;
+
+	ASC_SCSI_BIT_ID_TYPE	can_tagged_qng;
+	ASC_SCSI_BIT_ID_TYPE	cmd_qng_enabled;
+	ASC_SCSI_BIT_ID_TYPE	disc_enable;
+	ASC_SCSI_BIT_ID_TYPE	sdtr_enable;
+	u_int8_t		chip_scsi_id;
+	u_int8_t		isa_dma_speed;
+	u_int8_t		isa_dma_channel;
+	u_int8_t		chip_version;
+	u_int16_t		pci_device_id;
+	u_int16_t		lib_serial_no;
+	u_int16_t		lib_version;
+	u_int16_t		mcode_date;
+	u_int16_t		mcode_version;
+	u_int8_t		max_tag_qng[ASC_MAX_TID + 1];
+	u_int8_t		sdtr_period_offset[ASC_MAX_TID + 1];
+	u_int8_t		adapter_info[6];
+
+	u_int8_t		scsi_reset_wait;
+	u_int8_t		max_total_qng;
+	u_int8_t		cur_total_qng;
+	u_int8_t		irq_no;
+	u_int8_t		last_q_shortage;
+
+	u_int8_t		cur_dvc_qng[ASC_MAX_TID + 1];
+	u_int8_t		max_dvc_qng[ASC_MAX_TID + 1];
+	u_int8_t		sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
+	u_int8_t		sdtr_period_tbl_size;	/* see below */
+	u_int8_t		sdtr_data[ASC_MAX_TID+1];
+
+	u_int16_t		reqcnt[ASC_MAX_TID+1]; /* Starvation request count */
+
+	u_int32_t		max_dma_count;
+	ASC_SCSI_BIT_ID_TYPE	pci_fix_asyn_xfer;
+	ASC_SCSI_BIT_ID_TYPE	pci_fix_asyn_xfer_always;
+	u_int8_t		max_sdtr_index;
+	u_int8_t		host_init_sdtr_index;
+} ASC_SOFTC;
+
+/* sc_flags values */
+#define ASC_HOST_IN_RESET		0x01
+#define ASC_HOST_IN_ABORT		0x02
+#define ASC_WIDE_BOARD			0x04
+#define ASC_SELECT_QUEUE_DEPTHS		0x08
+
+/* sdtr_period_tbl_size values */
+#define SYN_XFER_NS_0		 25
+#define SYN_XFER_NS_1		 30
+#define SYN_XFER_NS_2		 35
+#define SYN_XFER_NS_3		 40
+#define SYN_XFER_NS_4		 50
+#define SYN_XFER_NS_5		 60
+#define SYN_XFER_NS_6		 70
+#define SYN_XFER_NS_7		 85
+
+#define SYN_ULTRA_XFER_NS_0	 12
+#define SYN_ULTRA_XFER_NS_1	 19
+#define SYN_ULTRA_XFER_NS_2	 25
+#define SYN_ULTRA_XFER_NS_3	 32
+#define SYN_ULTRA_XFER_NS_4	 38
+#define SYN_ULTRA_XFER_NS_5	 44
+#define SYN_ULTRA_XFER_NS_6	 50
+#define SYN_ULTRA_XFER_NS_7	 57
+#define SYN_ULTRA_XFER_NS_8	 63
+#define SYN_ULTRA_XFER_NS_9	 69
+#define SYN_ULTRA_XFER_NS_10	 75
+#define SYN_ULTRA_XFER_NS_11	 82
+#define SYN_ULTRA_XFER_NS_12	 88
+#define SYN_ULTRA_XFER_NS_13	 94
+#define SYN_ULTRA_XFER_NS_14	100
+#define SYN_ULTRA_XFER_NS_15	107
+
+
+/* second level interrupt callback type definition */
+typedef int (* ASC_ISR_CALLBACK) (ASC_SOFTC *, ASC_QDONE_INFO *);
+
+
+#define ASC_MCNTL_NO_SEL_TIMEOUT	0x0001
+#define ASC_MCNTL_NULL_TARGET		0x0002
+
+#define ASC_CNTL_INITIATOR		0x0001
+#define ASC_CNTL_BIOS_GT_1GB		0x0002
+#define ASC_CNTL_BIOS_GT_2_DISK		0x0004
+#define ASC_CNTL_BIOS_REMOVABLE		0x0008
+#define ASC_CNTL_NO_SCAM		0x0010
+#define ASC_CNTL_INT_MULTI_Q		0x0080
+#define ASC_CNTL_NO_LUN_SUPPORT		0x0040
+#define ASC_CNTL_NO_VERIFY_COPY		0x0100
+#define ASC_CNTL_RESET_SCSI		0x0200
+#define ASC_CNTL_INIT_INQUIRY	 	0x0400
+#define ASC_CNTL_INIT_VERBOSE		0x0800
+#define ASC_CNTL_SCSI_PARITY		0x1000
+#define ASC_CNTL_BURST_MODE		0x2000
+#define ASC_CNTL_SDTR_ENABLE_ULTRA	0x4000
+
+#define ASC_EEP_DVC_CFG_BEG_VL		 2
+#define ASC_EEP_MAX_DVC_ADDR_VL		15
+#define ASC_EEP_DVC_CFG_BEG		32
+#define ASC_EEP_MAX_DVC_ADDR		45
+#define ASC_EEP_DEFINED_WORDS		10
+#define ASC_EEP_MAX_ADDR		63
+#define ASC_EEP_RES_WORDS		 0
+#define ASC_EEP_MAX_RETRY		20
+#define ASC_MAX_INIT_BUSY_RETRY		 8
+#define ASC_EEP_ISA_PNP_WSIZE		16
+
+
+/*
+ * This structure is used to read/write EEProm configuration
+ */
+typedef struct asceep_config
+{
+	u_int16_t	cfg_lsw;
+	u_int16_t	cfg_msw;
+	u_int8_t	init_sdtr;
+	u_int8_t	disc_enable;
+	u_int8_t	use_cmd_qng;
+	u_int8_t	start_motor;
+	u_int8_t	max_total_qng;
+	u_int8_t	max_tag_qng;
+	u_int8_t	bios_scan;
+	u_int8_t	power_up_wait;
+	u_int8_t	no_scam;
+	u_int8_t	chip_scsi_id:4;
+	u_int8_t	isa_dma_speed:4;
+	u_int8_t	dos_int13_table[ASC_MAX_TID + 1];
+	u_int8_t	adapter_info[6];
+	u_int16_t	cntl;
+	u_int16_t	chksum;
+} ASCEEP_CONFIG;
+
+#define ASC_PCI_CFG_LSW_SCSI_PARITY	0x0800
+#define ASC_PCI_CFG_LSW_BURST_MODE	0x0080
+#define ASC_PCI_CFG_LSW_INTR_ABLE	0x0020
+
+#define ASC_EEP_CMD_READ		0x80
+#define ASC_EEP_CMD_WRITE		0x40
+#define ASC_EEP_CMD_WRITE_ABLE		0x30
+#define ASC_EEP_CMD_WRITE_DISABLE	0x00
+
+#define ASC_OVERRUN_BSIZE		0x00000048UL
+
+#define ASC_CTRL_BREAK_ONCE		0x0001
+#define ASC_CTRL_BREAK_STAY_IDLE	0x0002
+
+#define ASCV_MSGOUT_BEG			0x0000
+#define ASCV_MSGOUT_SDTR_PERIOD		(ASCV_MSGOUT_BEG+3)
+#define ASCV_MSGOUT_SDTR_OFFSET		(ASCV_MSGOUT_BEG+4)
+#define ASCV_BREAK_SAVED_CODE		0x0006
+#define ASCV_MSGIN_BEG			(ASCV_MSGOUT_BEG+8)
+#define ASCV_MSGIN_SDTR_PERIOD		(ASCV_MSGIN_BEG+3)
+#define ASCV_MSGIN_SDTR_OFFSET		(ASCV_MSGIN_BEG+4)
+#define ASCV_SDTR_DATA_BEG		(ASCV_MSGIN_BEG+8)
+#define ASCV_SDTR_DONE_BEG		(ASCV_SDTR_DATA_BEG+8)
+#define ASCV_MAX_DVC_QNG_BEG		0x0020
+#define ASCV_BREAK_ADDR		   	0x0028
+#define ASCV_BREAK_NOTIFY_COUNT 	0x002A
+#define ASCV_BREAK_CONTROL		0x002C
+#define ASCV_BREAK_HIT_COUNT		0x002E
+
+#define ASCV_ASCDVC_ERR_CODE_W		0x0030
+#define ASCV_MCODE_CHKSUM_W		0x0032
+#define ASCV_MCODE_SIZE_W		0x0034
+#define ASCV_STOP_CODE_B		0x0036
+#define ASCV_DVC_ERR_CODE_B		0x0037
+#define ASCV_OVERRUN_PADDR_D		0x0038
+#define ASCV_OVERRUN_BSIZE_D		0x003C
+#define ASCV_HALTCODE_W			0x0040
+#define ASCV_CHKSUM_W			0x0042
+#define ASCV_MC_DATE_W			0x0044
+#define ASCV_MC_VER_W			0x0046
+#define ASCV_NEXTRDY_B			0x0048
+#define ASCV_DONENEXT_B	  		0x0049
+#define ASCV_USE_TAGGED_QNG_B		0x004A
+#define ASCV_SCSIBUSY_B	 		0x004B
+#define ASCV_Q_DONE_IN_PROGRESS_B	0x004C
+#define ASCV_CURCDB_B			0x004D
+#define ASCV_RCLUN_B			0x004E
+#define ASCV_BUSY_QHEAD_B		0x004F
+#define ASCV_DISC1_QHEAD_B		0x0050
+#define ASCV_DISC_ENABLE_B		0x0052
+#define ASCV_CAN_TAGGED_QNG_B 		0x0053
+#define ASCV_HOSTSCSI_ID_B		0x0055
+#define ASCV_MCODE_CNTL_B		0x0056
+#define ASCV_NULL_TARGET_B		0x0057
+#define ASCV_FREE_Q_HEAD_W		0x0058
+#define ASCV_DONE_Q_TAIL_W		0x005A
+#define ASCV_FREE_Q_HEAD_B		(ASCV_FREE_Q_HEAD_W+1)
+#define ASCV_DONE_Q_TAIL_B		(ASCV_DONE_Q_TAIL_W+1)
+#define ASCV_HOST_FLAG_B		0x005D
+#define ASCV_TOTAL_READY_Q_B  		0x0064
+#define ASCV_VER_SERIAL_B	 	0x0065
+#define ASCV_HALTCODE_SAVED_W		0x0066
+#define ASCV_WTM_FLAG_B			0x0068
+#define ASCV_RISC_FLAG_B		0x006A
+#define ASCV_REQ_SG_LIST_QP		0x006B
+
+#define ASC_HOST_FLAG_IN_ISR		0x01
+#define ASC_HOST_FLAG_ACK_INT		0x02
+#define ASC_RISC_FLAG_GEN_INT		0x01
+#define ASC_RISC_FLAG_REQ_SG_LIST	0x02
+
+#define ASC_IOP_CTRL			0x0F
+#define ASC_IOP_STATUS			0x0E
+#define ASC_IOP_INT_ACK			ASC_IOP_STATUS
+#define ASC_IOP_REG_IFC			0x0D
+#define ASC_IOP_SYN_OFFSET		0x0B
+#define ASC_IOP_EXTRA_CONTROL	0x0D
+#define ASC_IOP_REG_PC			0x0C
+#define ASC_IOP_RAM_ADDR		0x0A
+#define ASC_IOP_RAM_DATA		0x08
+#define ASC_IOP_EEP_DATA		0x06
+#define ASC_IOP_EEP_CMD			0x07
+#define ASC_IOP_VERSION			0x03
+#define ASC_IOP_CONFIG_HIGH		0x04
+#define ASC_IOP_CONFIG_LOW		0x02
+#define ASC_IOP_SIG_BYTE		0x01
+#define ASC_IOP_SIG_WORD		0x00
+#define ASC_IOP_REG_DC1			0x0E
+#define ASC_IOP_REG_DC0			0x0C
+#define ASC_IOP_REG_SB			0x0B
+#define ASC_IOP_REG_DA1			0x0A
+#define ASC_IOP_REG_DA0			0x08
+#define ASC_IOP_REG_SC			0x09
+#define ASC_IOP_DMA_SPEED		0x07
+#define ASC_IOP_REG_FLAG		0x07
+#define ASC_IOP_FIFO_H			0x06
+#define ASC_IOP_FIFO_L			0x04
+#define ASC_IOP_REG_ID			0x05
+#define ASC_IOP_REG_QP			0x03
+#define ASC_IOP_REG_IH	 		0x02
+#define ASC_IOP_REG_IX	 		0x01
+#define ASC_IOP_REG_AX			0x00
+
+#define ASC_IFC_REG_LOCK		0x00
+#define ASC_IFC_REG_UNLOCK		0x09
+#define ASC_IFC_WR_EN_FILTER		0x10
+#define ASC_IFC_RD_NO_EEPROM		0x10
+#define ASC_IFC_SLEW_RATE		0x20
+#define ASC_IFC_ACT_NEG			0x40
+#define ASC_IFC_INP_FILTER		0x80
+#define ASC_IFC_INIT_DEFAULT	(ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK)
+
+#define SC_SEL	0x80
+#define SC_BSY	0x40
+#define SC_ACK	0x20
+#define SC_REQ	0x10
+#define SC_ATN	0x08
+#define SC_IO	0x04
+#define SC_CD	0x02
+#define SC_MSG	0x01
+
+#define SEC_SCSI_CTL		0x80
+#define SEC_ACTIVE_NEGATE	0x40
+#define SEC_SLEW_RATE		0x20
+#define SEC_ENABLE_FILTER	0x10
+
+#define ASC_HALT_EXTMSG_IN			0x8000
+#define ASC_HALT_CHK_CONDITION			0x8100
+#define ASC_HALT_SS_QUEUE_FULL			0x8200
+#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX	0x8300
+#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX	0x8400
+#define ASC_HALT_SDTR_REJECTED			0x4000
+
+#define ASC_MAX_QNO		0xF8
+
+#define ASC_DATA_SEC_BEG	0x0080
+#define ASC_DATA_SEC_END	0x0080
+#define ASC_CODE_SEC_BEG	0x0080
+#define ASC_CODE_SEC_END	0x0080
+#define ASC_QADR_BEG		(0x4000)
+#define ASC_QADR_USED		(ASC_MAX_QNO * 64)
+#define ASC_QADR_END		0x7FFF
+#define ASC_QLAST_ADR		0x7FC0
+#define ASC_QBLK_SIZE		0x40
+#define ASC_BIOS_DATA_QBEG	0xF8
+#define ASC_MIN_ACTIVE_QNO	0x01
+#define ASC_QLINK_END		0xFF
+#define ASC_EEPROM_WORDS	0x10
+#define ASC_MAX_MGS_LEN		0x10
+
+#define ASC_BIOS_ADDR_DEF	0xDC00
+#define ASC_BIOS_SIZE		0x3800
+#define ASC_BIOS_RAM_OFF	0x3800
+#define ASC_BIOS_RAM_SIZE 	0x800
+#define ASC_BIOS_MIN_ADDR	0xC000
+#define ASC_BIOS_MAX_ADDR	0xEC00
+#define ASC_BIOS_BANK_SIZE	0x0400
+
+#define ASC_MCODE_START_ADDR	0x0080
+
+#define ASC_CFG0_HOST_INT_ON	0x0020
+#define ASC_CFG0_BIOS_ON	0x0040
+#define ASC_CFG0_VERA_BURST_ON	0x0080
+#define ASC_CFG0_SCSI_PARITY_ON	0x0800
+#define ASC_CFG1_SCSI_TARGET_ON	0x0080
+#define ASC_CFG1_LRAM_8BITS_ON	0x0800
+#define ASC_CFG_MSW_CLR_MASK	0x3080
+
+#define ASC_CSW_TEST1			0x8000
+#define ASC_CSW_AUTO_CONFIG		0x4000
+#define ASC_CSW_RESERVED1		0x2000
+#define ASC_CSW_IRQ_WRITTEN		0x1000
+#define ASC_CSW_33MHZ_SELECTED		0x0800
+#define ASC_CSW_TEST2			0x0400
+#define ASC_CSW_TEST3			0x0200
+#define ASC_CSW_RESERVED2		0x0100
+#define ASC_CSW_DMA_DONE		0x0080
+#define ASC_CSW_FIFO_RDY		0x0040
+#define ASC_CSW_EEP_READ_DONE		0x0020
+#define ASC_CSW_HALTED			0x0010
+#define ASC_CSW_SCSI_RESET_ACTIVE	0x0008
+#define ASC_CSW_PARITY_ERR		0x0004
+#define ASC_CSW_SCSI_RESET_LATCH  	0x0002
+#define ASC_CSW_INT_PENDING		0x0001
+
+#define ASC_CIW_CLR_SCSI_RESET_INT	0x1000
+#define ASC_CIW_INT_ACK			0x0100
+#define ASC_CIW_TEST1			0x0200
+#define ASC_CIW_TEST2			0x0400
+#define ASC_CIW_SEL_33MHZ		0x0800
+#define ASC_CIW_IRQ_ACT			0x1000
+
+#define ASC_CC_CHIP_RESET	0x80
+#define ASC_CC_SCSI_RESET	0x40
+#define ASC_CC_HALT		0x20
+#define ASC_CC_SINGLE_STEP	0x10
+#define ASC_CC_DMA_ABLE		0x08
+#define ASC_CC_TEST		0x04
+#define ASC_CC_BANK_ONE		0x02
+#define ASC_CC_DIAG		0x01
+
+#define ASC_1000_ID0W		0x04C1
+#define ASC_1000_ID0W_FIX	0x00C1
+#define ASC_1000_ID1B		0x25
+
+#define ASC_EISA_BIG_IOP_GAP	(0x1C30-0x0C50)
+#define ASC_EISA_SMALL_IOP_GAP	(0x0020)
+#define ASC_EISA_MIN_IOP_ADDR	(0x0C30)
+#define ASC_EISA_MAX_IOP_ADDR	(0xFC50)
+#define ASC_EISA_REV_IOP_MASK	(0x0C83)
+#define ASC_EISA_PID_IOP_MASK	(0x0C80)
+#define ASC_EISA_CFG_IOP_MASK	(0x0C86)
+
+#define ASC_GET_EISA_SLOT(iop)	((iop) & 0xF000)
+
+#define ASC_EISA_ID_740	0x01745004UL
+#define ASC_EISA_ID_750	0x01755004UL
+
+#define ASC_INS_HALTINT		0x6281
+#define ASC_INS_HALT		0x6280
+#define ASC_INS_SINT		0x6200
+#define ASC_INS_RFLAG_WTM	0x7380
+
+
+/******************************************************************************/
+/*                                      Macro                                 */
+/******************************************************************************/
+
+/*
+ * These Macros are used to deal with board CPU Registers and LRAM
+ */
+
+#define ASC_GET_QDONE_IN_PROGRESS(iot, ioh)			AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B)
+#define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val)		AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val)
+#define ASC_GET_VAR_FREE_QHEAD(iot, ioh)			AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W)
+#define ASC_GET_VAR_DONE_QTAIL(iot, ioh)			AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W)
+#define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val)			AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val)
+#define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val)			AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val)
+#define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh)			AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B)
+#define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh)			AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B)
+#define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val)   		AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val)
+#define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val)   		AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val)
+#define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data)	AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ;
+#define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id)		AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ;
+#define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data)	AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ;
+#define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id)		AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ;
+#define ASC_SYN_INDEX_TO_PERIOD(sc, index)			(u_int8_t)((sc)->sdtr_period_tbl[ (index) ])
+#define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh)			bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE)
+#define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh)			bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD)
+#define ASC_GET_CHIP_VER_NO(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_VERSION)
+#define ASC_GET_CHIP_CFG_LSW(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW)
+#define ASC_GET_CHIP_CFG_MSW(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH)
+#define ASC_SET_CHIP_CFG_LSW(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data)
+#define ASC_SET_CHIP_CFG_MSW(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data)
+#define ASC_GET_CHIP_EEP_CMD(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD)
+#define ASC_SET_CHIP_EEP_CMD(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data)
+#define ASC_GET_CHIP_EEP_DATA(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA)
+#define ASC_SET_CHIP_EEP_DATA(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data)
+#define ASC_GET_CHIP_LRAM_ADDR(iot, ioh)			bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR)
+#define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr)			bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr)
+#define ASC_GET_CHIP_LRAM_DATA(iot, ioh)			bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
+#define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
+#if BYTE_ORDER == BIG_ENDIAN
+#define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh)		swap_bytes(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA))
+#define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data)		bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, swap_bytes(data))
+#else
+#define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh)		bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
+#define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data)		bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
+#endif
+#define ASC_GET_CHIP_IFC(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC)
+#define ASC_SET_CHIP_IFC(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data)
+#define ASC_GET_CHIP_STATUS(iot, ioh)				(u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS)
+#define ASC_SET_CHIP_STATUS(iot, ioh, cs_val)			bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val)
+#define ASC_GET_CHIP_CONTROL(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_CTRL)
+#define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val)			bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val)
+#define ASC_GET_CHIP_SYN(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET)
+#define ASC_SET_CHIP_SYN(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data)
+#define ASC_SET_PC_ADDR(iot, ioh, data)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data)
+#define ASC_GET_PC_ADDR(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC)
+#define ASC_IS_INT_PENDING(iot, ioh)				(ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH))
+#define ASC_GET_CHIP_SCSI_ID(iot, ioh)				((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID)
+#define ASC_GET_EXTRA_CONTROL(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL)
+#define ASC_SET_EXTRA_CONTROL(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data)
+#define ASC_READ_CHIP_AX(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX)
+#define ASC_WRITE_CHIP_AX(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data)
+#define ASC_READ_CHIP_IX(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX)
+#define ASC_WRITE_CHIP_IX(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data)
+#define ASC_READ_CHIP_IH(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH)
+#define ASC_WRITE_CHIP_IH(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data)
+#define ASC_READ_CHIP_QP(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP)
+#define ASC_WRITE_CHIP_QP(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data)
+#define ASC_READ_CHIP_FIFO_L(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L)
+#define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data)
+#define ASC_READ_CHIP_FIFO_H(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H)
+#define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data)
+#define ASC_READ_CHIP_DMA_SPEED(iot, ioh)			bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED)
+#define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data)		bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data)
+#define ASC_READ_CHIP_DA0(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0)
+#define ASC_WRITE_CHIP_DA0(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data)
+#define ASC_READ_CHIP_DA1(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1)
+#define ASC_WRITE_CHIP_DA1(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data)
+#define ASC_READ_CHIP_DC0(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0)
+#define ASC_WRITE_CHIP_DC0(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data)
+#define ASC_READ_CHIP_DC1(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1)
+#define ASC_WRITE_CHIP_DC1(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data)
+#define ASC_READ_CHIP_DVC_ID(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID)
+#define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data)
+
+
+/******************************************************************************/
+/*                                Exported functions                          */
+/******************************************************************************/
+
+
+void AscInitASC_SOFTC __P((ASC_SOFTC *));
+u_int16_t AscInitFromEEP __P((ASC_SOFTC *));
+u_int16_t AscInitFromASC_SOFTC __P((ASC_SOFTC *));
+int AscInitDriver __P((ASC_SOFTC *));
+void AscReInitLram __P((ASC_SOFTC *));
+int AscFindSignature __P((bus_space_tag_t, bus_space_handle_t));
+int AscISR __P((ASC_SOFTC *));
+int AscExeScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *));
+void AscInquiryHandling __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *));
+int AscAbortCCB __P((ASC_SOFTC *, u_int32_t));
+int AscResetBus __P((ASC_SOFTC *));
+int AscResetDevice __P((ASC_SOFTC *, u_char));
+
+
+/******************************************************************************/
+#endif	/* _ADVANSYS_LIBRARY_H_ */
diff --git a/sys/dev/ic/advmcode.c b/sys/dev/ic/advmcode.c
new file mode 100644
index 00000000000..9665dbea312
--- /dev/null
+++ b/sys/dev/ic/advmcode.c
@@ -0,0 +1,221 @@
+/*	$OpenBSD: advmcode.c,v 1.1 1998/09/27 03:36:14 downsj Exp $	*/
+/*      $NetBSD: advmcode.c,v 1.2 1998/08/29 13:45:57 dante Exp $        */
+
+/*
+ * Generic driver definitions and exported functions for the Advanced
+ * Systems Inc. SCSI controllers
+ * 
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Author: Baldassare Dante Profeta <dante@mclink.it>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    This product includes software developed by the NetBSD
+ *    Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Ported from:
+ */
+/*
+ * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
+ * 
+ * Copyright (c) 1995-1998 Advanced System Products, Inc.
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that redistributions of source
+ * code retain the above copyright notice and this comment without
+ * modification.
+ *
+ */
+
+
+#include <sys/param.h>
+
+
+/*
+ * This is the uCode for the Narrow board RISC cpu.
+ * This code is loaded into Lram during initializzation procedure.
+ */
+
+u_int8_t asc_mcode[] =
+{
+  0x01,  0x03,  0x01,  0x19,  0x0F,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
+  0x0F,  0x0F,  0x0F,  0x0F,  0x0F,  0x0F,  0x0F,  0x0F,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
+  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
+  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
+  0x00,  0x00,  0x00,  0x00,  0x91,  0x10,  0x0A,  0x05,  0x01,  0x00,  0x00,  0x00,  0x00,  0xFF,  0x00,  0x00,
+  0x00,  0x00,  0x00,  0x00,  0xFF,  0x80,  0xFF,  0xFF,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
+  0x00,  0x00,  0x00,  0x23,  0x00,  0x24,  0x00,  0x00,  0x00,  0x07,  0x00,  0xFF,  0x00,  0x00,  0x00,  0x00,
+  0xFF,  0xFF,  0xFF,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0xE2,  0x88,  0x00,  0x00,  0x00,  0x00,
+  0x80,  0x73,  0x48,  0x04,  0x36,  0x00,  0x00,  0xA2,  0xC2,  0x00,  0x80,  0x73,  0x03,  0x23,  0x36,  0x40,
+  0xB6,  0x00,  0x36,  0x00,  0x05,  0xD6,  0x0C,  0xD2,  0x12,  0xDA,  0x00,  0xA2,  0xC2,  0x00,  0x92,  0x80,
+  0x1E,  0x98,  0x50,  0x00,  0xF5,  0x00,  0x48,  0x98,  0xDF,  0x23,  0x36,  0x60,  0xB6,  0x00,  0x92,  0x80,
+  0x4F,  0x00,  0xF5,  0x00,  0x48,  0x98,  0xEF,  0x23,  0x36,  0x60,  0xB6,  0x00,  0x92,  0x80,  0x80,  0x62,
+  0x92,  0x80,  0x00,  0x46,  0x17,  0xEE,  0x13,  0xEA,  0x02,  0x01,  0x09,  0xD8,  0xCD,  0x04,  0x4D,  0x00,
+  0x00,  0xA3,  0xD6,  0x00,  0xA6,  0x97,  0x7F,  0x23,  0x04,  0x61,  0x84,  0x01,  0xE6,  0x84,  0xD2,  0xC1,
+  0x80,  0x73,  0xCD,  0x04,  0x4D,  0x00,  0x00,  0xA3,  0xE2,  0x01,  0xA6,  0x97,  0xCE,  0x81,  0x00,  0x33,
+  0x02,  0x00,  0xC0,  0x88,  0x80,  0x73,  0x80,  0x77,  0x00,  0x01,  0x01,  0xA1,  0x02,  0x01,  0x4F,  0x00,
+  0x84,  0x97,  0x07,  0xA6,  0x0C,  0x01,  0x00,  0x33,  0x03,  0x00,  0xC0,  0x88,  0x03,  0x03,  0x03,  0xDE,
+  0x00,  0x33,  0x05,  0x00,  0xC0,  0x88,  0xCE,  0x00,  0x69,  0x60,  0xCE,  0x00,  0x02,  0x03,  0x4A,  0x60,
+  0x00,  0xA2,  0x80,  0x01,  0x80,  0x63,  0x07,  0xA6,  0x2C,  0x01,  0x80,  0x81,  0x03,  0x03,  0x80,  0x63,
+  0xE2,  0x00,  0x07,  0xA6,  0x3C,  0x01,  0x00,  0x33,  0x04,  0x00,  0xC0,  0x88,  0x03,  0x07,  0x02,  0x01,
+  0x04,  0xCA,  0x0D,  0x23,  0x68,  0x98,  0x4D,  0x04,  0x04,  0x85,  0x05,  0xD8,  0x0D,  0x23,  0x68,  0x98,
+  0xCD,  0x04,  0x15,  0x23,  0xF6,  0x88,  0xFB,  0x23,  0x02,  0x61,  0x82,  0x01,  0x80,  0x63,  0x02,  0x03,
+  0x06,  0xA3,  0x6A,  0x01,  0x00,  0x33,  0x0A,  0x00,  0xC0,  0x88,  0x4E,  0x00,  0x07,  0xA3,  0x76,  0x01,
+  0x00,  0x33,  0x0B,  0x00,  0xC0,  0x88,  0xCD,  0x04,  0x36,  0x2D,  0x00,  0x33,  0x1A,  0x00,  0xC0,  0x88,
+  0x50,  0x04,  0x90,  0x81,  0x06,  0xAB,  0x8A,  0x01,  0x90,  0x81,  0x4E,  0x00,  0x07,  0xA3,  0x9A,  0x01,
+  0x50,  0x00,  0x00,  0xA3,  0x44,  0x01,  0x00,  0x05,  0x84,  0x81,  0x46,  0x97,  0x02,  0x01,  0x05,  0xC6,
+  0x04,  0x23,  0xA0,  0x01,  0x15,  0x23,  0xA1,  0x01,  0xC6,  0x81,  0xFD,  0x23,  0x02,  0x61,  0x82,  0x01,
+  0x0A,  0xDA,  0x4A,  0x00,  0x06,  0x61,  0x00,  0xA0,  0xBC,  0x01,  0x80,  0x63,  0xCD,  0x04,  0x36,  0x2D,
+  0x00,  0x33,  0x1B,  0x00,  0xC0,  0x88,  0x06,  0x23,  0x68,  0x98,  0xCD,  0x04,  0xE6,  0x84,  0x06,  0x01,
+  0x00,  0xA2,  0xDC,  0x01,  0x57,  0x60,  0x00,  0xA0,  0xE2,  0x01,  0xE6,  0x84,  0x80,  0x23,  0xA0,  0x01,
+  0xE6,  0x84,  0x80,  0x73,  0x4B,  0x00,  0x06,  0x61,  0x00,  0xA2,  0x08,  0x02,  0x04,  0x01,  0x0C,  0xDE,
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+  0x07,  0x00,  0xC0,  0x88,  0x80,  0x05,  0x81,  0x05,  0x04,  0x01,  0x11,  0xC8,  0x48,  0x00,  0xB0,  0x01,
+  0xB1,  0x01,  0x08,  0x23,  0xB2,  0x01,  0x05,  0x01,  0x48,  0x04,  0x00,  0x43,  0x00,  0xA2,  0xE4,  0x07,
+  0x00,  0x05,  0xDA,  0x87,  0x00,  0x01,  0xC8,  0x00,  0xFF,  0x23,  0x80,  0x01,  0x05,  0x05,  0x00,  0x63,
+  0xF7,  0x04,  0x1A,  0x09,  0xF6,  0x08,  0x6E,  0x04,  0x00,  0x02,  0x80,  0x43,  0x76,  0x08,  0x80,  0x02,
+  0x77,  0x04,  0x00,  0x63,  0xF7,  0x04,  0x1A,  0x09,  0xF6,  0x08,  0x6E,  0x04,  0x00,  0x02,  0x00,  0xA0,
+  0x14,  0x08,  0x16,  0x88,  0x00,  0x43,  0x76,  0x08,  0x80,  0x02,  0x77,  0x04,  0x00,  0x63,  0xF3,  0x04,
+  0x00,  0x23,  0xF4,  0x00,  0x74,  0x00,  0x80,  0x43,  0xF4,  0x00,  0xCF,  0x40,  0x00,  0xA2,  0x44,  0x08,
+  0x74,  0x04,  0x02,  0x01,  0xF7,  0xC9,  0xF6,  0xD9,  0x00,  0x01,  0x01,  0xA1,  0x24,  0x08,  0x04,  0x98,
+  0x26,  0x95,  0x24,  0x88,  0x73,  0x04,  0x00,  0x63,  0xF3,  0x04,  0x75,  0x04,  0x5A,  0x88,  0x02,  0x01,
+  0x04,  0xD8,  0x46,  0x97,  0x04,  0x98,  0x26,  0x95,  0x4A,  0x88,  0x75,  0x00,  0x00,  0xA3,  0x64,  0x08,
+  0x00,  0x05,  0x4E,  0x88,  0x73,  0x04,  0x00,  0x63,  0x80,  0x7B,  0x80,  0x63,  0x06,  0xA6,  0x76,  0x08,
+  0x00,  0x33,  0x3E,  0x00,  0xC0,  0x88,  0x80,  0x67,  0x83,  0x03,  0x80,  0x63,  0x00,  0x63,  0x38,  0x2B,
+  0x9C,  0x88,  0x38,  0x2B,  0x92,  0x88,  0x32,  0x09,  0x31,  0x05,  0x92,  0x98,  0x05,  0x05,  0xB2,  0x09,
+  0x00,  0x63,  0x00,  0x32,  0x00,  0x36,  0x00,  0x3A,  0x00,  0x3E,  0x00,  0x63,  0x80,  0x32,  0x80,  0x36,
+  0x80,  0x3A,  0x80,  0x3E,  0x00,  0x63,  0x38,  0x2B,  0x40,  0x32,  0x40,  0x36,  0x40,  0x3A,  0x40,  0x3E,
+  0x00,  0x63,  0x5A,  0x20,  0xC9,  0x40,  0x00,  0xA0,  0xB2,  0x08,  0x5D,  0x00,  0xFE,  0xC3,  0x00,  0x63,
+  0x80,  0x73,  0xE6,  0x20,  0x02,  0x23,  0xE8,  0x00,  0x82,  0x73,  0xFF,  0xFD,  0x80,  0x73,  0x13,  0x23,
+  0xF6,  0x88,  0x66,  0x20,  0xC0,  0x20,  0x04,  0x23,  0xA0,  0x01,  0xA1,  0x23,  0xA1,  0x01,  0x81,  0x62,
+  0xE0,  0x88,  0x80,  0x73,  0x80,  0x77,  0x68,  0x00,  0x00,  0xA2,  0x80,  0x00,  0x03,  0xC2,  0xF1,  0xC7,
+  0x41,  0x23,  0xF6,  0x88,  0x11,  0x23,  0xA1,  0x01,  0x04,  0x23,  0xA0,  0x01,  0xE6,  0x84,
+};
+
+u_int16_t asc_mcode_size = sizeof(asc_mcode);
+
+/*
+ * This checksum is used to compare with that one that will be calculated
+ * at run time.
+ * This is performed to ensure the uCode is correctly loaded into the Lram.
+ */
+u_int32_t asc_mcode_chksum = 0x012B5442UL;
diff --git a/sys/dev/ic/advmcode.h b/sys/dev/ic/advmcode.h
new file mode 100644
index 00000000000..fece7325d67
--- /dev/null
+++ b/sys/dev/ic/advmcode.h
@@ -0,0 +1,49 @@
+/*	$OpenBSD: advmcode.h,v 1.1 1998/09/27 03:36:14 downsj Exp $	*/
+/*      $NetBSD: advmcode.h,v 1.2 1998/08/29 13:45:57 dante Exp $        */
+
+/*
+ * Generic driver definitions and exported functions for the Advanced
+ * Systems Inc. SCSI controllers
+ * 
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Author: Baldassare Dante Profeta <dante@mclink.it>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    This product includes software developed by the NetBSD
+ *    Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ADV_MCODE_H
+#define ADV_MCODE_H
+
+extern u_int8_t asc_mcode[];
+extern u_int16_t asc_mcode_size;
+extern u_int32_t asc_mcode_chksum;
+
+#endif	/* ADV_MCODE_H */