cleanup the printf/DPRINTF mess.

use proper debug levels for diagnostic messages such that we don't
spam the logs when athn_debug is low.

4 files changed, 23 insertions, 23 deletions

diff --git a/sys/dev/ic/ar5416.c b/sys/dev/ic/ar5416.c
index f75421d98d0..b9b6a55b07b 100644
--- a/sys/dev/ic/ar5416.c
+++ b/sys/dev/ic/ar5416.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5416.c,v 1.3 2009/11/15 14:04:02 damien Exp $	*/
+/*	$OpenBSD: ar5416.c,v 1.4 2009/11/17 19:32:22 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -207,7 +207,7 @@ ar5416_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 	chansel = athn_reverse_bits(chansel, 8);
 	phy |= chansel << 8 | 1 << 5 | 1;
-	DPRINTF(("AR_PHY(0x37)=0x%08x\n", phy));
+	DPRINTFN(4, ("AR_PHY(0x37)=0x%08x\n", phy));
 	AR_WRITE(sc, AR_PHY(0x37), phy);
 	return (0);
 }
@@ -682,7 +682,7 @@ ar5416_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 	if (i == AR_EEPROM_MODAL_SPURS)
 		return; /* XXX disable if it was enabled! */
-	DPRINTF(("enabling spur mitigation\n"));
+	DPRINTFN(2, ("enabling spur mitigation\n"));
 
 	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
 	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
@@ -889,7 +889,7 @@ ar9160_rw_addac(struct athn_softc *sc, struct ieee80211_channel *c,
 		bias = modal->xpaBiasLvl & 0x3;
 
 	bias = athn_reverse_bits(bias, 2);	/* Put in host bit-order. */
-	DPRINTF(("bias level=%d\n", bias));
+	DPRINTFN(4, ("bias level=%d\n", bias));
 	if (IEEE80211_IS_CHAN_2GHZ(c))
 		ar5416_rw_rfbits(addac, 0, 60, bias, 2);
 	else
diff --git a/sys/dev/ic/ar9280.c b/sys/dev/ic/ar9280.c
index bd034c1acdd..b61fe59cec2 100644
--- a/sys/dev/ic/ar9280.c
+++ b/sys/dev/ic/ar9280.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9280.c,v 1.2 2009/11/15 14:04:02 damien Exp $	*/
+/*	$OpenBSD: ar9280.c,v 1.3 2009/11/17 19:32:22 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -201,7 +201,7 @@ ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
 			AR_WRITE(sc, AR_AN_SYNTH9, reg);
 		}
 	}
-	DPRINTF(("AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy));
+	DPRINTFN(4, ("AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy));
 	AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
 	return (0);
 }
@@ -454,7 +454,7 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 	if (i == AR_EEPROM_MODAL_SPURS)
 		return;	/* XXX disable if it was enabled! */
-	DPRINTF(("enabling spur mitigation\n"));
+	DPRINTFN(2, ("enabling spur mitigation\n"));
 
 	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
 	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
@@ -555,7 +555,7 @@ ar9280_2_0_olpc_temp_compensation(struct athn_softc *sc)
 
 	reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
 	pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
-	DPRINTF(("PD Avg Out=%d\n", pdadc));
+	DPRINTFN(3, ("PD Avg Out=%d\n", pdadc));
 
 	if (sc->pdadc == 0 || pdadc == 0)
 		return;	/* No frames transmitted yet. */
@@ -566,7 +566,7 @@ ar9280_2_0_olpc_temp_compensation(struct athn_softc *sc)
 		tcomp = (pdadc - sc->pdadc + 4) / 8;
 	else
 		tcomp = (pdadc - sc->pdadc + 5) / 10;
-	DPRINTF(("OLPC temp compensation=%d\n", tcomp));
+	DPRINTFN(3, ("OLPC temp compensation=%d\n", tcomp));
 
 	if (tcomp == sc->tcomp)
 		return;	/* Don't rewrite the same values. */
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c
index 239a53b1093..a738d17163f 100644
--- a/sys/dev/ic/ar9287.c
+++ b/sys/dev/ic/ar9287.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9287.c,v 1.3 2009/11/15 14:04:02 damien Exp $	*/
+/*	$OpenBSD: ar9287.c,v 1.4 2009/11/17 19:32:22 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -546,7 +546,7 @@ ar9287_olpc_temp_compensation(struct athn_softc *sc)
 
 	reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
 	pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
-	DPRINTF(("PD Avg Out=%d\n", pdadc));
+	DPRINTFN(3, ("PD Avg Out=%d\n", pdadc));
 
 	if (sc->pdadc == 0 || pdadc == 0)
 		return;	/* No frames transmitted yet. */
@@ -560,7 +560,7 @@ ar9287_olpc_temp_compensation(struct athn_softc *sc)
 		tcomp = ((pdadc - sc->pdadc) * 4) / slope;
 	else
 		tcomp = 0;
-	DPRINTF(("OLPC temp compensation=%d\n", tcomp));
+	DPRINTFN(3, ("OLPC temp compensation=%d\n", tcomp));
 
 	/* Write compensation value for both Tx chains. */
 	reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index 5e21e99795a..c71f3805185 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: athn.c,v 1.8 2009/11/17 18:46:35 damien Exp $	*/
+/*	$OpenBSD: athn.c,v 1.9 2009/11/17 19:32:22 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -64,7 +64,7 @@
 #include <dev/ic/athnvar.h>
 
 #ifdef ATHN_DEBUG
-int athn_debug = 4;
+int athn_debug = 1;
 #endif
 
 void		athn_radiotap_attach(struct athn_softc *);
@@ -1280,7 +1280,7 @@ athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c,
 
 	/* If band or bandwidth changes, we need to do a full reset. */
 	if (c->ic_flags != ic->ic_bss->ni_chan->ic_flags) {
-		DPRINTF(("channel band switch\n"));
+		DPRINTFN(2, ("channel band switch\n"));
 		goto reset;
 	}
 	error = athn_set_power_awake(sc);
@@ -1290,7 +1290,7 @@ athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c,
 	error = athn_set_chan(sc, c, extc);
 	if (error != 0) {
  reset:		/* Error found, try a full reset. */
-		DPRINTF(("needs a full reset\n"));
+		DPRINTFN(3, ("needs a full reset\n"));
 		error = athn_hw_reset(sc, c, extc);
 		if (error != 0)	/* Hopeless case. */
 			return (error);
@@ -1698,8 +1698,8 @@ athn_rfsilent_init(struct athn_softc *sc)
 	/* Get polarity of hardware radio switch. */
 	if (base->rfSilent & AR_EEP_RFSILENT_POLARITY)
 		sc->flags |= ATHN_FLAG_RFSILENT_REVERSED;
-	printf("%s: Found RF switch connected to GPIO pin %d\n",
-	    sc->sc_dev.dv_xname, sc->rfsilent_pin);
+	DPRINTFN(2, ("%s: Found RF switch connected to GPIO pin %d\n",
+	    sc->rfsilent_pin));
 
 	/* Configure hardware radio switch. */
 	AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
@@ -1825,7 +1825,7 @@ athn_calib_iq(struct athn_softc *sc)
 		else if (q_coff <= -16)
 			q_coff = 16;
 
-		DPRINTF(("IQ calibration for chain %d\n", i));
+		DPRINTFN(2, ("IQ calibration for chain %d\n", i));
 		reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
@@ -1869,7 +1869,7 @@ athn_calib_adc_gain(struct athn_softc *sc)
 		gain_mismatch_q =
 		    (cal->pwr_meas_odd_q * 32) / cal->pwr_meas_even_q;
 
-		DPRINTF(("ADC gain calibration for chain %d\n", i));
+		DPRINTFN(2, ("ADC gain calibration for chain %d\n", i));
 		reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
@@ -1913,7 +1913,7 @@ athn_calib_adc_dc_off(struct athn_softc *sc)
 		dc_offset_mismatch_q =
 		    (cal->pwr_meas_odd_q - cal->pwr_meas_even_q * 2) / count;
 
-		DPRINTF(("ADC DC offset calibration for chain %d\n", i));
+		DPRINTFN(2, ("ADC DC offset calibration for chain %d\n", i));
 		reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
 		    dc_offset_mismatch_q);
@@ -3949,7 +3949,7 @@ athn_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
 		else
 			pvals = ini->vals_5g20;
 	}
-	DPRINTF(("writing per-mode init vals\n"));
+	DPRINTFN(4, ("writing per-mode init vals\n"));
 	for (i = 0; i < ini->nregs; i++) {
 		AR_WRITE(sc, ini->regs[i], pvals[i]);
 		if (AR_IS_ANALOG_REG(ini->regs[i]))
@@ -3965,7 +3965,7 @@ athn_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
 		ar9280_reset_tx_gain(sc, c);
 
 	/* Second initialization step (common to all channels). */
-	DPRINTF(("writing common init vals\n"));
+	DPRINTFN(4, ("writing common init vals\n"));
 	for (i = 0; i < ini->ncmregs; i++) {
 		AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
 		if (AR_IS_ANALOG_REG(ini->cmregs[i]))