diff options
author | Jonathan Gray <jsg@cvs.openbsd.org> | 2024-02-02 03:39:57 +0000 |
---|---|---|
committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2024-02-02 03:39:57 +0000 |
commit | 693750f079392be9b2e44c60c73db12ec450a7cf (patch) | |
tree | 2cd6101a8837b40f81f60b634786d5d3367b7533 /sys/dev | |
parent | 7a204deaa963d8bd379b8b188ffa64b4a007ba56 (diff) |
drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs
From Alex Deucher
b59ea95e72e051fe53a5c978222d65b80ca2ef96 in linux-6.6.y/6.6.15
03ff6d7238b77e5fb2b85dc5fe01d2db9eb893bd in mainline linux
Diffstat (limited to 'sys/dev')
-rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c | 2 | ||||
-rw-r--r-- | sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c index 965c86cc311..8e9e703199b 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c @@ -6572,7 +6572,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, #ifdef __BIG_ENDIAN tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); #endif - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); diff --git a/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 8b7fed91352..22cbfa1bdad 100644 --- a/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); |