diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2017-07-23 10:11:28 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2017-07-23 10:11:28 +0000 |
| commit | 429d76352955b5ab348af5dbba58142f1ab0b963 (patch) | |
| tree | a479c23edfe9edec8d38e21ebff49dfc79278c22 /sys/miscfs | |
| parent | f360a4859b2023bb9c7eb0c335fa0076dc79707f (diff) | |
Replace CPWAIT with an isb instruction, which is the proper way to make sure
CP15 updates are visible. Also add an isb instruction before switching on
the MMU to make sure that all the MMU-related CP15 registers updates are
visible.
Makes booting on a Cortex-A12/A17 get a bit further.
ok drahn@, jsg@
Diffstat (limited to 'sys/miscfs')
0 files changed, 0 insertions, 0 deletions