Edge cases can trigger a TLB miss exception instead of an invalid TLB

exception on early R5000 revisions. Despite this bug being supposedly
fixed in R5000 revision 2 onwards, it nevertheless occurs quite frequently
on matthieu's revision 2.1 R5000.

Servicing the TLB miss exception would cause a duplicate TLB to be inserted,
which causes the processor operation to become unpredictable (but lethal to
the kernel, ten times out of nine).

More details about the problem can be found in:
  http://www.linux-mips.org/archives/linux-mips/2000-02/msg00040.html

We work around the issue by checking for an existing TLB entry, and handling
this as an invalid TLB exception (as it was intended to be), in this case.

Unfortunately this causes a measurable 1% slowdown on ``safe'' processors,
so we'll work on providing different tlb handler flavours in the near future
to recover from this.

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