diff options
| author | Theo de Raadt <deraadt@cvs.openbsd.org> | 1996-09-29 11:36:54 +0000 |
|---|---|---|
| committer | Theo de Raadt <deraadt@cvs.openbsd.org> | 1996-09-29 11:36:54 +0000 |
| commit | 15c8c1e274911de0184fcc6791b41e7540984933 (patch) | |
| tree | 739ec1e6d56089abbb97c8eaf138852304305050 /sys | |
| parent | e3daada1407f62d2b3ee023a41a2537d81ec76b0 (diff) | |
merge mips back into pmax; by graichen
Diffstat (limited to 'sys')
51 files changed, 7072 insertions, 452 deletions
diff --git a/sys/arch/pmax/conf/MINIROOT b/sys/arch/pmax/conf/MINIROOT deleted file mode 100644 index fadaa97bcb2..00000000000 --- a/sys/arch/pmax/conf/MINIROOT +++ /dev/null @@ -1,184 +0,0 @@ -# -# DECstation (3100 or 5000/xxx) -# -# Generic config.new configuration for NetBSD/pmax -# $NetBSD: MINIROOT,v 1.1 1995/12/28 16:11:31 jonathan Exp $ -# -include "std.pmax" - -maxusers 8 - -# enables fudging of swap blocks to swap after a miniroot -# in the b partition, and make the kernel call setconf() to ask -# what the root device is. -options GENERIC - - -# replaces "cpu ds5k/240" -options DS5000 # generic TC support and 3MAX support -options DS5000_240 # 3MAXPLUS (kn03) support -options DS5000_100 # 3MIN (kn02ba/kmin) support -options DS5000_25 # MAXINE (kn02ca/xine) support -options DS5000_200 # 3MAX (kn02) support, one day - - -options DS3100 # PMAX (kn01) DECstation 2100, 3100 - - -# You need to set this locally, but it doesn't do much outside the kernel. -# Set up /etc/localtime instead. -options TIMEZONE="0" # minutes west of GMT (for) -options DST=0 # use daylight savings rules - - -# Standard system options -options SWAPPAGER # swap pager (anonymous and swap space) -options DEVPAGER # device pager (mapped devices) -#options DIAGNOSTIC # extra kernel debugging checks -options DEBUG # extra kernel debugging support -options "COMPAT_43" # compatibility with 4.3BSD binaries -options KTRACE # system call tracing support -options "NKMEMCLUSTERS=1024" # 4K pages in kernel malloc pool - -#options KGDB # support for kernel gdb -#options "KGDBRATE=19200" # kernel gdb port rate (default 9600) -#options "KGDBDEV=15*256+0" # device for kernel gdb - -# Filesystem options -options FIFO # POSIX fifo support (in all filesystems) -options FFS,QUOTA # fast filesystem with user and group quotas -options MFS # memory-based filesystem -options NFSCLIENT # Sun NFS-compatible filesystem (client) -options NFSSERVER # Sun NFS-compatible filesystem (server) -options KERNFS # kernel data-structure filesystem -#options FDESC # user file descriptor filesystem -#options UMAPFS # uid/gid remapping filesystem -options NULLFS # null layer filesystem -#options LFS # Log-based filesystem (still experimental) -#options PORTAL # portal filesystem (still experimental) - -# Networking options -options INET # Internet protocols -options "TCP_COMPAT_42" # compatibility with 4.2BSD TCP/IP -options GATEWAY # IP packet forwarding -#options MULTICAST # Multicast support -#options MROUTING # Multicast routing support -#options ISO # OSI networking -#options TPIP -#options EON - -options COMPAT_10 # Pre-NetBSD 1.1 compatibility - -# pmax specific -options COMPAT_ULTRIX # ultrix compatibility - -# Note that this configuration is unlikely to work, yet... -config gennetbsd swap generic - - -######################################################################## -# # -# DECstation Turbochannel configuration and options # -# # -######################################################################## - -tc* at mainbus0 # All but PMAXes have a turbochannel - - -######################################################################## -# Common configuration for machines with IO ASIC chips # -# (3MIN, MAXINE, 3MAXPLUS) # -######################################################################## -ioasic0 at tc? -clock0 at ioasic? # RTC -asc0 at ioasic? # system SCSI subslot -scc0 at ioasic? -le0 at ioasic? # tc onboard lance -scc1 at ioasic? # Not present on Maxine - -######################################################################## -# MAXINE-only baseboard devices and on-baseboard "options" # -######################################################################## -xcfb0 at tc? # TC framebuffer "option" -dtop0 at ioasic0 -#isdn at ioasic0 -#fdc at ioasic0 # floppy disk - - -######################################################################## -# Configuration for 3MAX (5000/200) which has turbochannel but no ASIC.# -# 3MAX (5000/200) baseboard devices and on-baseboard "options" # -######################################################################## -clock0 at mainbus0 # RTC -dc0 at mainbus0 -le0 at tc? #slot ? offset ? # TC ether "option" on baseboard -asc0 at tc? # TC scsi "option" on baseboard -# For now, pretend this machine has an IOASIC. -dc0 at ioasic? # dc7083 four-port DZ device - -######################################################################## -# Supported turbochannel option cards # -######################################################################## -cfb0 at tc? -mfb0 at tc? -sfb0 at tc? -#sfb1 at tc? -le* at tc? #slot ? offset ? # TC ether option -#tt0 at tc? #slot? offset ? - - -######################################################################## -# Decstation 2100/3100 (aka PMAX aka KN01) configuration. # -# (these don't really have any options except a framebuffer.) # -######################################################################## -clock0 at mainbus0 # RTC -pm0 at mainbus0 # 3100 onboard fb -dc0 at mainbus0 # dc7083 four-port DZ device -le0 at mainbus0 # 3100 onboard lance -sii0 at mainbus0 # onboard scsi - - -######################################################################## -# SCSI configuration # -######################################################################## - -# -# SCSI configuration for new-config machine-independent SCSI driver -# -scsibus* at sii? -scsibus* at asc? - -sd* at scsibus? target ? lun ? -st* at scsibus? target ? lun ? -cd* at scsibus? target ? lun ? - - -# -# SCSI configuration for old DECstation SCSI driver -# -oldscsibus* at sii? -oldscsibus* at asc? - -rz0 at oldscsibus? target ? drive ? -rz1 at oldscsibus? target ? drive ? -rz2 at oldscsibus? target ? drive ? -rz3 at oldscsibus? target ? drive ? -rz4 at oldscsibus? target ? drive ? -rz5 at oldscsibus? target ? drive ? -tz0 at oldscsibus? target? drive ? -tz1 at oldscsibus? target? drive ? - - -# -# pseudo-devices -# - -pseudo-device sl 4 # serial-line IP ports -pseudo-device pty 64 # pseudo ptys -pseudo-device bpfilter 16 # packet filter ports -pseudo-device loop -pseudo-device vnd 4 # virtual disk ick - -#pseudo-device ether # From old config. what does it mean? -pseudo-device rasterconsole 1 # NB: raster console requires "fb" -pseudo-device fb 3 # up to 3 framebuffers diff --git a/sys/arch/pmax/conf/Makefile.pmax b/sys/arch/pmax/conf/Makefile.pmax index 2830beeaf6d..d3122845a7b 100644 --- a/sys/arch/pmax/conf/Makefile.pmax +++ b/sys/arch/pmax/conf/Makefile.pmax @@ -110,7 +110,7 @@ assym.h: genassym genassym: genassym.o ${CC} -o $@ genassym.o -genassym.o: ${S}/arch/mips/mips/genassym.c +genassym.o: ${S}/arch/pmax/pmax/genassym.c ${NORMAL_C_C} param.c: $S/conf/param.c @@ -156,7 +156,7 @@ depend:: .depend mkdep ${AFLAGS} ${CPPFLAGS} ${PMAX}/pmax/locore.S ${PMAX}/pmax/fp.S mkdep -a ${CFLAGS} ${CPPFLAGS} param.c ioconf.c ${CFILES} mkdep -a ${AFLAGS} ${CPPFLAGS} ${SFILES} - mkdep -a ${CFLAGS} ${CPPFLAGS} ${PARAM} ${S}/arch/mips/mips/genassym.c + mkdep -a ${CFLAGS} ${CPPFLAGS} ${PARAM} ${S}/arch/pmax/pmax/genassym.c # depend on root or device configuration diff --git a/sys/arch/pmax/conf/NEWCONF b/sys/arch/pmax/conf/NEWCONF deleted file mode 100644 index 5daf259b4aa..00000000000 --- a/sys/arch/pmax/conf/NEWCONF +++ /dev/null @@ -1,185 +0,0 @@ -# -# DECstation (3100 or 5000/xxx) -# -# Generic config.new configuration for NetBSD/pmax -# $NetBSD: NEWCONF,v 1.6.4.2 1996/06/17 05:14:26 jonathan Exp $ -# -include "std.pmax" - -maxusers 8 - -# does not really do anything anymore, but this replaces "ident GENERIC" -# (actually, it enables fudging of swap blocks to swap after a miniroot -# in the b partition, and make the kernel call setconf() to ask -# what the root device is.) -#options GENERIC - -options CPU_R3000 # R2000/R3000 support - -# replaces "cpu ds5k/240" -options DS5000_240 # 3MAXPLUS (kn03) support -options DS5000_100 # 3MIN (kn02ba/kmin) support -options DS5000_25 # MAXINE (kn02ca/xine) support -options DS5000_200 # 3MAX (kn02) support, one day - - -options DS3100 # PMAX (kn01) DECstation 2100, 3100 - - -# You need to set this locally, but it doesn't do much outside the kernel. -# Set up /etc/localtime instead. -options TIMEZONE="8*60" # minutes west of GMT (for) -options DST=1 # use daylight savings rules - - -# Standard system options -options SWAPPAGER # swap pager (anonymous and swap space) -options DEVPAGER # device pager (mapped devices) -#options DIAGNOSTIC # extra kernel debugging checks -options DEBUG # extra kernel debugging support -options "COMPAT_43" # compatibility with 4.3BSD binaries -options KTRACE # system call tracing support -options "NKMEMCLUSTERS=1024" # 4K pages in kernel malloc pool -#options KGDB # support for kernel gdb -#options "KGDBRATE=19200" # kernel gdb port rate (default 9600) -#options "KGDBDEV=15*256+0" # device for kernel gdb - -# Filesystem options -options FIFO # POSIX fifo support (in all filesystems) -options FFS,QUOTA # fast filesystem with user and group quotas -options MFS # memory-based filesystem -options NFSCLIENT # Sun NFS-compatible filesystem (client) -options NFSSERVER # Sun NFS-compatible filesystem (server) -options KERNFS # kernel data-structure filesystem -#options FDESC # user file descriptor filesystem -#options UMAPFS # uid/gid remapping filesystem -options NULLFS # null layer filesystem -#options LFS # Log-based filesystem (still experimental) -#options PORTAL # portal filesystem (still experimental) - -# Networking options -options INET # Internet protocols -options "TCP_COMPAT_42" # compatibility with 4.2BSD TCP/IP -options GATEWAY # IP packet forwarding -#options MULTICAST # Multicast support -#options MROUTING # Multicast routing support -#options ISO # OSI networking -#options TPIP -#options EON - -# pmax specific -options COMPAT_ULTRIX # ultrix compatibility -options "HZ=256" # RTC rate required - -# Note that this configuration is unlikely to work, yet... -config netbsd root on rz0a swap on rz0b and rz1b dumps on rz0b -config rz1netbsd root on rz1a swap on rz0b and rz1b dumps on rz0b -#config gennetbsd swap generic - - -######################################################################## -# # -# DECstation Turbochannel configuration and options # -# # -######################################################################## - -tc* at mainbus0 # All but PMAXes have a turbochannel - - -######################################################################## -# Common configuration for machines with IO ASIC chips # -# (3MIN, MAXINE, 3MAXPLUS) # -######################################################################## -ioasic0 at tc? -clock0 at ioasic? # RTC -asc0 at ioasic? # system SCSI subslot -scc0 at ioasic? -le0 at ioasic? # tc onboard lance -scc1 at ioasic? # Not present on Maxine - -######################################################################## -# MAXINE-only baseboard devices and on-baseboard "options" # -######################################################################## -xcfb0 at tc? # TC framebuffer "option" -dtop0 at ioasic0 -#isdn at ioasic0 -#fdc at ioasic0 # floppy disk - - -######################################################################## -# Configuration for 3MAX (5000/200) which has turbochannel but no ASIC.# -# 3MAX (5000/200) baseboard devices and on-baseboard "options" # -######################################################################## -clock0 at mainbus0 # RTC -dc0 at mainbus0 -le0 at tc? #slot ? offset ? # TC ether "option" on baseboard -asc0 at tc? # TC scsi "option" on baseboard -# For now, pretend this machine has an IOASIC. -dc0 at ioasic? # dc7083 four-port DZ device - -######################################################################## -# Supported turbochannel option cards # -######################################################################## -cfb0 at tc? -mfb0 at tc? -sfb0 at tc? -#sfb1 at tc? -le* at tc? #slot ? offset ? # TC ether option -#tt0 at tc? #slot? offset ? - - -######################################################################## -# Decstation 2100/3100 (aka PMAX aka KN01) configuration. # -# (these don't really have any options except a framebuffer.) # -######################################################################## -clock0 at mainbus0 # RTC -pm0 at mainbus0 # 3100 onboard fb -dc0 at mainbus0 # dc7083 four-port DZ device -le0 at mainbus0 # 3100 onboard lance -sii0 at mainbus0 # onboard scsi - - -######################################################################## -# SCSI configuration # -######################################################################## - -# -# SCSI configuration for new-config machine-independent SCSI driver -# -scsibus* at sii? -scsibus* at asc? - -sd* at scsibus? target ? lun ? -st* at scsibus? target ? lun ? -cd* at scsibus? target ? lun ? - - -# -# SCSI configuration for old DECstation SCSI driver -# -oldscsibus* at sii? -oldscsibus* at asc? - -rz0 at oldscsibus? target ? drive ? -rz1 at oldscsibus? target ? drive ? -rz2 at oldscsibus? target ? drive ? -rz3 at oldscsibus? target ? drive ? -rz4 at oldscsibus? target ? drive ? -rz5 at oldscsibus? target ? drive ? -tz0 at oldscsibus? target? drive ? -tz1 at oldscsibus? target? drive ? - - -# -# pseudo-devices -# - -pseudo-device sl 4 # serial-line IP ports -pseudo-device pty 64 # pseudo ptys -pseudo-device bpfilter 16 # packet filter ports -pseudo-device loop -pseudo-device vnd 4 # virtual disk ick - -#pseudo-device ether # From old config. what does it mean? -pseudo-device rasterconsole 1 # NB: raster console requires "fb" -pseudo-device fb 3 # up to 3 framebuffers diff --git a/sys/arch/pmax/conf/PLUTO b/sys/arch/pmax/conf/PLUTO new file mode 100644 index 00000000000..cbb5c2fc308 --- /dev/null +++ b/sys/arch/pmax/conf/PLUTO @@ -0,0 +1,54 @@ +# +# PLUTO - specific config(8) file for pluto +# + +machine pmax + +options CPU_R3000 +options DS3100 +options HZ=256 +options NKMEMCLUSTERS=1024 +options TIMEZONE=0 +options DST=0 + +maxusers 8 + +options SWAPPAGER +options VNODEPAGER +options DEVPAGER + +options COMPAT_43 +options NATIVE_ELF +options FFS +options FIFO +options INET +options NFSCLIENT +options NFSSERVER +options KTRACE + +config netbsd root on rz0a swap on rz0b dumps on rz0b + +mainbus0 at root + +cpu* at mainbus0 +clock0 at mainbus0 +pm0 at mainbus0 +dc0 at mainbus0 +le0 at mainbus0 +sii0 at mainbus0 +oldscsibus* at sii? +rz0 at oldscsibus? target ? drive ? +rz1 at oldscsibus? target ? drive ? +rz2 at oldscsibus? target ? drive ? +rz3 at oldscsibus? target ? drive ? +rz4 at oldscsibus? target ? drive ? +rz5 at oldscsibus? target ? drive ? +tz0 at oldscsibus? target ? drive ? +tz1 at oldscsibus? target ? drive ? + +pseudo-device loop +pseudo-device rasterconsole 1 +pseudo-device fb 1 +pseudo-device sl 1 +pseudo-device bpfilter 8 +pseudo-device pty 32 diff --git a/sys/arch/pmax/conf/files.pmax b/sys/arch/pmax/conf/files.pmax index 8d4c4d4255b..df0a35a0fcf 100644 --- a/sys/arch/pmax/conf/files.pmax +++ b/sys/arch/pmax/conf/files.pmax @@ -215,3 +215,6 @@ file arch/pmax/pmax/conf-glue.c include "../../../compat/ultrix/files.ultrix" # Configs +file arch/pmax/pmax/cpu_exec.c +file arch/pmax/pmax/mem.c +file arch/pmax/pmax/process_machdep.c diff --git a/sys/arch/pmax/conf/std.pmax b/sys/arch/pmax/conf/std.pmax deleted file mode 100644 index 601b5ec883d..00000000000 --- a/sys/arch/pmax/conf/std.pmax +++ /dev/null @@ -1,6 +0,0 @@ -# $NetBSD: std.pmax,v 1.0 1995/04/28 03:10:41 jonathan Exp -# standard pmax info - -machine pmax mips -mainbus0 at root -cpu* at mainbus0 diff --git a/sys/arch/pmax/include/ansi.h b/sys/arch/pmax/include/ansi.h index 607e3ce3021..d60ce969212 100644 --- a/sys/arch/pmax/include/ansi.h +++ b/sys/arch/pmax/include/ansi.h @@ -1,3 +1,75 @@ -/* $NetBSD: ansi.h,v 1.7 1996/03/19 11:00:16 jonathan Exp $ */ +/* $NetBSD: ansi.h,v 1.6 1996/03/16 01:32:00 jtc Exp $ */ -#include <mips/ansi.h> +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ansi.h 8.2 (Berkeley) 1/4/94 + */ + +#ifndef _ANSI_H_ +#define _ANSI_H_ + +/* + * Types which are fundamental to the implementation and may appear in + * more than one standard header are defined here. Standard headers + * then use: + * #ifdef _BSD_SIZE_T_ + * typedef _BSD_SIZE_T_ size_t; + * #undef _BSD_SIZE_T_ + * #endif + */ +#define _BSD_CLOCK_T_ unsigned long /* clock() */ +#define _BSD_PTRDIFF_T_ int /* ptr1 - ptr2 */ +#define _BSD_SIZE_T_ unsigned int /* sizeof() */ +#define _BSD_SSIZE_T_ int /* byte count or error */ +#define _BSD_TIME_T_ long /* time() */ +#define _BSD_VA_LIST_ char * /* va_list */ + +/* + * Runes (wchar_t) is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use _RUNE_T_ instead of int. By changing it here, you + * lose a bit of ANSI conformance, but your programs will still work. + * + * Note that _WCHAR_T_ and _RUNE_T_ must be of the same type. When wchar_t + * and rune_t are typedef'd, _WCHAR_T_ will be undef'd, but _RUNE_T remains + * defined for ctype.h. + */ +#define _BSD_WCHAR_T_ int /* wchar_t */ +#define _BSD_WINT_T_ int /* wint_t */ +#define _BSD_RUNE_T_ int /* rune_t */ + +#endif /* _ANSI_H_ */ diff --git a/sys/arch/pmax/include/asm.h b/sys/arch/pmax/include/asm.h new file mode 100644 index 00000000000..b31981eb962 --- /dev/null +++ b/sys/arch/pmax/include/asm.h @@ -0,0 +1,182 @@ +/* $NetBSD: asm.h,v 1.8 1996/03/25 02:50:50 jonathan Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * machAsmDefs.h -- + * + * Macros used when writing assembler programs. + * + * Copyright (C) 1989 Digital Equipment Corporation. + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies. + * Digital Equipment Corporation makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, + * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) + */ + +#ifndef _MIPS_ASM_H +#define _MIPS_ASM_H + +#include <machine/regdef.h> + +/* + * Define -pg profile entry code. + */ +#if defined(GPROF) || defined(PROF) +#define MCOUNT .set noreorder; \ + .set noat; \ + move $1,$31; \ + jal _mcount; \ + subu sp,sp,8; \ + .set reorder; \ + .set at; +#else +#define MCOUNT +#endif + +#ifdef __NO_LEADING_UNDERSCORES__ +# define _C_LABEL(x) x +#else +# ifdef __STDC__ +# define _C_LABEL(x) _ ## x +# else +# define _C_LABEL(x) _/**/x +# endif +#endif + +/* + * LEAF(x) + * + * Declare a leaf routine. + */ +#define LEAF(x) \ + .globl _C_LABEL(x); \ + .ent _C_LABEL(x), 0; \ +_C_LABEL(x): ; \ + .frame sp, 0, ra; \ + MCOUNT + +/* + * NLEAF(x) + * + * Declare a non-profiled leaf routine. + */ +#define NLEAF(x) \ + .globl _C_LABEL(x); \ + .ent _C_LABEL(x), 0; \ +_C_LABEL(x): ; \ + .frame sp, 0, ra + +/* + * ALEAF -- declare alternate entry to a leaf routine. + */ +#ifdef USE_AENT +#define AENT(x) \ + .aent x, 0 +#else +#define AENT(x) +#endif +#define ALEAF(x) \ + .globl _C_LABEL(x); \ + AENT (_C_LABEL(x)) \ +_C_LABEL(x): + +/* + * NON_LEAF(x) + * + * Declare a non-leaf routine (a routine that makes other C calls). + */ +#define NON_LEAF(x, fsize, retpc) \ + .globl _C_LABEL(x); \ + .ent _C_LABEL(x), 0; \ +_C_LABEL(x): ; \ + .frame sp, fsize, retpc; \ + MCOUNT + +/* + * NNON_LEAF(x) + * + * Declare a non-profiled non-leaf routine + * (a routine that makes other C calls). + */ +#define NNON_LEAF(x, fsize, retpc) \ + .globl _C_LABEL(x); \ + .ent _C_LABEL(x), 0; \ +_C_LABEL(x): ; \ + .frame sp, fsize, retpc + +/* + * END(x) + * + * Mark end of a procedure. + */ +#define END(x) \ + .end _C_LABEL(x) + +#define STAND_FRAME_SIZE 24 +#define STAND_RA_OFFSET 20 + +/* + * Macros to panic and printf from assembly language. + */ +#define PANIC(msg) \ + la a0, 9f; \ + jal _C_LABEL(panic); \ + MSG(msg) + +#define PRINTF(msg) \ + la a0, 9f; \ + jal _C_LABEL(printf); \ + MSG(msg) + +#define MSG(msg) \ + .rdata; \ +9: .asciiz msg; \ + .text + +#define ASMSTR(str) \ + .asciiz str; \ + .align 2 + +#endif /* _MIPS_ASM_H */ diff --git a/sys/arch/pmax/include/bsd-aout.h b/sys/arch/pmax/include/bsd-aout.h index 1d98a19d7ab..5d496ff1d09 100644 --- a/sys/arch/pmax/include/bsd-aout.h +++ b/sys/arch/pmax/include/bsd-aout.h @@ -1,7 +1,33 @@ -/* $NetBSD: bsd-aout.h,v 1.3 1996/03/19 03:06:28 jonathan Exp $ */ - /* bsd-aout.h 4.4bsd a.out format, for backwards compatibility... */ -#include <mips/bsd-aout.h> +#ifndef __MACHINE_BSD_AOUT_H__ +#define __MACHINE_BSD_AOUT_H__ +#define BSD_OMAGIC 0407 /* old impure format */ +#define BSD_NMAGIC 0410 /* read-only text */ +#define BSD_ZMAGIC 0413 /* demand load format */ + +struct bsd_aouthdr { +#if BYTE_ORDER == BIG_ENDIAN + u_short a_mid; /* machine ID */ + u_short a_magic; /* magic number */ +#else + u_short a_magic; /* magic number */ + u_short a_mid; /* machine ID */ +#endif + + u_long a_text; /* text segment size */ + u_long a_data; /* initialized data size */ + u_long a_bss; /* uninitialized data size */ + u_long a_syms; /* symbol table size */ + u_long a_entry; /* entry point */ + u_long a_trsize; /* text relocation size */ + u_long a_drsize; /* data relocation size */ +}; + +#ifndef _KERNEL +#define _AOUT_INCLUDE_ +#include <nlist.h> +#endif /* _KERNEL */ +#endif /* __MACHINE_BSD_AOUT_H__ */ diff --git a/sys/arch/pmax/include/cdefs.h b/sys/arch/pmax/include/cdefs.h index ece6d966740..47499b695ea 100644 --- a/sys/arch/pmax/include/cdefs.h +++ b/sys/arch/pmax/include/cdefs.h @@ -1,3 +1,45 @@ -/* $NetBSD: cdefs.h,v 1.5 1996/03/19 04:39:03 jonathan Exp $ */ +/* $NetBSD: cdefs.h,v 1.4 1995/12/15 01:17:04 jonathan Exp $ */ -#include <mips/cdefs.h> +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#ifndef _MACHINE_CDEFS_H_ +#define _MACHINE_CDEFS_H_ + +#define _C_LABEL(x) _STRING(x) + +#define __indr_references(sym,msg) /* nothing */ + +#if defined __GNUC__ && defined __STDC__ +#define __warn_references(sym, msg) \ + static const char __evoke_link_warning_##sym[] \ + __attribute__ ((section (".gnu.warning." #sym))) = msg; +#else +#define __warn_references(sym,msg) /* nothing */ +#endif + +#endif /* !_MACHINE_CDEFS_H_ */ diff --git a/sys/arch/pmax/include/cpu.h b/sys/arch/pmax/include/cpu.h index a185964ac80..4b169358773 100644 --- a/sys/arch/pmax/include/cpu.h +++ b/sys/arch/pmax/include/cpu.h @@ -1,16 +1,207 @@ -/* $NetBSD: cpu.h,v 1.15 1996/05/19 01:28:47 jonathan Exp $ */ +/* $NetBSD: cpu.h,v 1.15 1996/03/23 20:28:19 jonathan Exp $ */ -#include <mips/cpu.h> -#include <mips/cpuregs.h> /* XXX */ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell and Rick Macklem. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cpu.h 8.4 (Berkeley) 1/4/94 + */ -#define CLKF_USERMODE(framep) CLKF_USERMODE_R3K(framep) -#define CLKF_BASEPRI(framep) CLKF_BASEPRI_R3K(framep) +#ifndef _CPU_H_ +#define _CPU_H_ + +#include <machine/machConst.h> + +/* + * Exported definitions unique to NetBSD/mips cpu support. + */ + +/* + * definitions of cpu-dependent requirements + * referenced in generic code + */ +#define cpu_wait(p) /* nothing */ +#define cpu_set_init_frame(p, fp) /* nothing */ +#define cpu_swapout(p) panic("cpu_swapout: can't get here"); + +/* + * Arguments to hardclock and gatherstats encapsulate the previous + * machine state in an opaque clockframe. + */ +struct clockframe { + int pc; /* program counter at time of interrupt */ + int sr; /* status register at time of interrupt */ +}; + +/* + * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use + * in machine-independent code. These differ on r4000 and r3000 systems; + * provide them in the port-dependent file that includes this one, using + * the macros below. + */ + +/* r3000 versions */ +#define CLKF_USERMODE_R3K(framep) ((framep)->sr & MACH_SR_KU_PREV) +#define CLKF_BASEPRI_R3K(framep) \ + ((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) == 0) + +/* r4000 versions */ +#define CLKF_USERMODE_R4K(framep) ((framep)->sr & MACH_SR_KSU_USER) +#define CLKF_BASEPRI_R4K(framep) \ + ((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENAB)) == 0) + +#define CLKF_PC(framep) ((framep)->pc) +#define CLKF_INTR(framep) (0) + +/* + * Preempt the current process if in interrupt from user mode, + * or after the current trap/syscall if in system mode. + */ +#define need_resched() { want_resched = 1; aston(); } + +/* + * Give a profiling tick to the current process when the user profiling + * buffer pages are invalid. On the MIPS, request an ast to send us + * through trap, marking the proc as needing a profiling tick. + */ +#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } + +/* + * Notify the current process (p) that it has a signal pending, + * process as soon as possible. + */ +#define signotify(p) aston() + +#define aston() (astpending = 1) + +int astpending; /* need to trap before returning to user mode */ +int want_resched; /* resched() was called */ + +/* + * CPU identification, from PRID register. + */ +union cpuprid { + int cpuprid; + struct { +#if BYTE_ORDER == BIG_ENDIAN + u_int pad1:16; /* reserved */ + u_int cp_imp:8; /* implementation identifier */ + u_int cp_majrev:4; /* major revision identifier */ + u_int cp_minrev:4; /* minor revision identifier */ +#else + u_int cp_minrev:4; /* minor revision identifier */ + u_int cp_majrev:4; /* major revision identifier */ + u_int cp_imp:8; /* implementation identifier */ + u_int pad1:16; /* reserved */ +#endif + } cpu; +}; + +/* + * CTL_MACHDEP definitions. + */ +#define CPU_CONSDEV 1 /* dev_t: console terminal device */ +#define CPU_MAXID 2 /* number of valid machdep ids */ + +#define CTL_MACHDEP_NAMES { \ + { 0, 0 }, \ + { "console_device", CTLTYPE_STRUCT }, \ +} + + +/* + * MIPS CPU types (cp_imp). + */ +#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ +#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ +#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ +#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ +#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ +#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ +#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ +#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ +#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ +#define MIPS_UNKC1 0x0b /* unnanounced product cpu ISA III */ +#define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */ +#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ +#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ +#define MIPS_R3SONY 0x21 /* Sony R3000 based CPU ISA I */ +#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ +#define MIPS_R3NKK 0x23 /* NKK R3000 based CPU ISA I */ + + +/* + * MIPS FPU types + */ +#define MIPS_SOFT 0x00 /* Software emulation ISA I */ +#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ +#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ +#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ +#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ +#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ +#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ +#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ +#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ +#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ +#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ +#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ +#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ +#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ +#define MIPS_R3NKK 0x23 /* NKK R3000 based FPU ISA I */ + +/* + * XXX port-dependent code should define cpu_id and fpu_id variables + * and machine-dependent cache descriptor variables. + */ + +/* + * Enable realtime clock (always enabled). + */ +#define enablertclock() + +#include <pmax/cpuregs.h> /* XXX */ + +#define CLKF_USERMODE(framep) CLKF_USERMODE_R3K(framep) +#define CLKF_BASEPRI(framep) CLKF_BASEPRI_R3K(framep) #ifdef _KERNEL -union cpuprid cpu_id; -union cpuprid fpu_id; -u_int machDataCacheSize; -u_int machInstCacheSize; -extern struct intr_tab intr_tab[]; +union cpuprid cpu_id; +union cpuprid fpu_id; +u_int machDataCacheSize; +u_int machInstCacheSize; +extern struct intr_tab intr_tab[]; #endif + +#endif /* _CPU_H_ */ diff --git a/sys/arch/pmax/include/cpuregs.h b/sys/arch/pmax/include/cpuregs.h new file mode 100644 index 00000000000..2ac0b9825ee --- /dev/null +++ b/sys/arch/pmax/include/cpuregs.h @@ -0,0 +1,584 @@ +/* $NetBSD: cpuregs.h,v 1.5 1996/03/28 11:34:05 jonathan Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell and Rick Macklem. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)machConst.h 8.1 (Berkeley) 6/10/93 + * + * machConst.h -- + * + * Machine dependent constants. + * + * Copyright (C) 1989 Digital Equipment Corporation. + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies. + * Digital Equipment Corporation makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, + * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, + * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) + * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, + * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) + */ + +#ifndef _MACHCONST +#define _MACHCONST + +#define MACH_KUSEG_ADDR 0x0 +#define MACH_CACHED_MEMORY_ADDR 0x80000000 +#define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 +#define MACH_KSEG2_ADDR 0xc0000000 +#define MACH_MAX_MEM_ADDR 0xbe000000 +#define MACH_RESERVED_ADDR 0xbfc80000 + +#define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) +#define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) +#define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) +#define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) + +/* Map virtual address to index in r4k virtually-indexed cache */ +#define MIPS_R4K_VA_TO_CINDEX(x) \ + ((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR) + +/* XXX compatibility with Pica port */ +#define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x) + + +/* + * XXX + * Port-specific constants: + * Kernel virtual address at which kernel is loaded, and + * Kernel virtual address for user page table entries + * (i.e., the address for the context register). + */ +#ifdef pmax +#define MACH_CODE_START 0x80030000 +#define VMMACH_PTE_BASE 0xFFC00000 +#endif /* pmax */ + +#ifdef pica +#define MACH_CODE_START 0x80080000 +#define VMMACH_PTE_BASE 0xFF800000 +#endif /* pica */ + + + +/* + * The bits in the cause register. + * + * Bits common to r3000 and r4000: + * + * MACH_CR_BR_DELAY Exception happened in branch delay slot. + * MACH_CR_COP_ERR Coprocessor error. + * MACH_CR_IP Interrupt pending bits defined below. + * (same meaning as in CAUSE register). + * MACH_CR_EXC_CODE The exception type (see exception codes below). + * + * Differences: + * r3k has 4 bits of execption type, r4k has 5 bits. + */ +#define MACH_CR_BR_DELAY 0x80000000 +#define MACH_CR_COP_ERR 0x30000000 +#define MIPS_3K_CR_EXC_CODE 0x0000003C +#define MIPS_4K_CR_EXC_CODE 0x0000007C +#define MACH_CR_IP 0x0000FF00 +#define MACH_CR_EXC_CODE_SHIFT 2 + +#ifdef pmax /* XXX not used any more, only to satisfy regression tests */ +#define MACH_CR_EXC_CODE MIPS_3K_CR_EXC_CODE +#endif /* pmax */ +#ifdef pica +#define MACH_CR_EXC_CODE MIPS_4K_CR_EXC_CODE +#endif /* pica */ + + +/* + * The bits in the status register. All bits are active when set to 1. + * + * R3000 status register fields: + * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. + * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. + * MACH_SR_TLB_SHUTDOWN TLB disabled. + * + * MIPS_SR_INT_IE Master (current) interrupt enable bit. + * + * Differences: + * r3k has cache control is via frobbing SR register bits, whereas the + * r4k cache control is via explicit instructions. + * r3k has a 3-entry stack of kernel/user bits, whereas the + * r4k has kernel/supervisor/user. + */ +#define MACH_SR_COP_USABILITY 0xf0000000 +#define MACH_SR_COP_0_BIT 0x10000000 +#define MACH_SR_COP_1_BIT 0x20000000 + + /* r4k and r3k differences, see below */ + +#define MACH_SR_BOOT_EXC_VEC 0x00400000 +#define MACH_SR_TLB_SHUTDOWN 0x00200000 + + /* r4k and r3k differences, see below */ + +#define MIPS_SR_INT_IE 0x00000001 +/*#define MACH_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ +/*#define MACH_SR_INT_MASK 0x0000ff00*/ + +#define MACH_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */ +#define MACH_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */ + + + +/* + * The R2000/R3000-specific status register bit definitions. + * all bits are active when set to 1. + * + * MACH_SR_PARITY_ERR Parity error. + * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. + * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. + * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. + * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. + * Interrupt enable bits defined below. + * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. + * MACH_SR_INT_ENA_OLD Old interrupt enable bit. + * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. + * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. + * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. + */ + +#define MIPS_3K_PARITY_ERR 0x00100000 +#define MIPS_3K_CACHE_MISS 0x00080000 +#define MIPS_3K_PARITY_ZERO 0x00040000 +#define MIPS_3K_SWAP_CACHES 0x00020000 +#define MIPS_3K_ISOL_CACHES 0x00010000 + +#define MIPS_3K_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ +#define MIPS_3K_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ +#define MIPS_3K_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ +#define MIPS_3K_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ +#define MIPS_3K_SR_KU_CUR 0x00000002 /* current KU */ + +/* backwards compatibility */ +#define MACH_SR_PARITY_ERR MIPS_3K_PARITY_ERR +#define MACH_SR_CACHE_MISS MIPS_3K_CACHE_MISS +#define MACH_SR_PARITY_ZERO MIPS_3K_PARITY_ZERO +#define MACH_SR_SWAP_CACHES MIPS_3K_SWAP_CACHES +#define MACH_SR_ISOL_CACHES MIPS_3K_ISOL_CACHES + +#define MACH_SR_KU_OLD MIPS_3K_SR_KU_OLD +#define MACH_SR_INT_ENA_OLD MIPS_3K_SR_INT_ENA_OLD +#define MACH_SR_KU_PREV MIPS_3K_SR_KU_PREV +#define MACH_SR_KU_CUR MIPS_3K_SR_KU_CUR +#define MACH_SR_INT_ENA_PREV MIPS_3K_SR_INT_ENA_PREV + + +/* + * R4000 status register bit definitons, + * where different from r2000/r3000. + */ +#define MIPS_4K_SR_RP 0x08000000 +#define MIPS_4K_SR_FR_32 0x04000000 +#define MIPS_4K_SR_RE 0x02000000 + +#define MIPS_4K_SR_SOFT_RESET 0x00100000 +#define MIPS_4K_SR_DIAG_CH 0x00040000 +#define MIPS_4K_SR_DIAG_CE 0x00020000 +#define MIPS_4K_SR_DIAG_PE 0x00010000 +#define MIPS_4K_SR_KX 0x00000080 +#define MIPS_4K_SR_SX 0x00000040 +#define MIPS_4K_SR_UX 0x00000020 +#define MIPS_4K_SR_KSU_MASK 0x00000018 +#define MIPS_4K_SR_KSU_USER 0x00000010 +#define MIPS_4K_SR_KSU_SUPER 0x00000008 +#define MIPS_4K_SR_KSU_KERNEL 0x00000000 +#define MIPS_4K_SR_ERL 0x00000004 +#define MIPS_4K_SR_EXL 0x00000002 + +/* backwards compatibility with names used in Pica port */ +#define MACH_SR_RP MIPS_4K_SR_RP +#define MACH_SR_FR_32 MIPS_4K_SR_FR_32 +#define MACH_SR_RE MIPS_4K_SR_RE + +#define MACH_SR_SOFT_RESET MIPS_4K_SR_SOFT_RESET +#define MACH_SR_DIAG_CH MIPS_4K_SR_DIAG_CH +#define MACH_SR_DIAG_CE MIPS_4K_SR_DIAG_CE +#define MACH_SR_DIAG_PE MIPS_4K_SR_DIAG_PE +#define MACH_SR_KX MIPS_4K_SR_KX +#define MACH_SR_SX MIPS_4K_SR_SX +#define MACH_SR_UX MIPS_4K_SR_UX + +#define MACH_SR_KSU_MASK MIPS_4K_SR_KSU_MASK +#define MACH_SR_KSU_USER MIPS_4K_SR_KSU_USER +#define MACH_SR_KSU_SUPER MIPS_4K_SR_KSU_SUPER +#define MACH_SR_KSU_KERNEL MIPS_4K_SR_KSU_KERNEL +#define MACH_SR_ERL MIPS_4K_SR_ERL +#define MACH_SR_EXL MIPS_4K_SR_EXL + + +/* + * The interrupt masks. + * If a bit in the mask is 1 then the interrupt is enabled (or pending). + */ +#define MIPS_INT_MASK 0xff00 +#define MACH_INT_MASK_5 0x8000 +#define MACH_INT_MASK_4 0x4000 +#define MACH_INT_MASK_3 0x2000 +#define MACH_INT_MASK_2 0x1000 +#define MACH_INT_MASK_1 0x0800 +#define MACH_INT_MASK_0 0x0400 +#define MIPS_HARD_INT_MASK 0xfc00 +#define MACH_SOFT_INT_MASK_1 0x0200 +#define MACH_SOFT_INT_MASK_0 0x0100 + +#ifdef pmax +#define MACH_INT_MASK MIPS_INT_MASK +#define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK +#endif + +/* r4000 has on-chip timer at INT_MASK_5 */ +#ifdef pica +#define MACH_INT_MASK (MIPS_INT_MASK & ~MACH_INT_MASK_5) +#define MACH_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5) +#endif + + + +/* + * The bits in the context register. + */ +#define MIPS_3K_CNTXT_PTE_BASE 0xFFE00000 +#define MIPS_3K_CNTXT_BAD_VPN 0x001FFFFC + +#define MIPS_4K_CNTXT_PTE_BASE 0xFF800000 +#define MIPS_4K_CNTXT_BAD_VPN2 0x007FFFF0 + +/* + * Backwards compatbility -- XXX more thought + */ +#ifdef pmax +#define MACH_CNTXT_PTE_BASE MIPS_3K_CNTXT_PTE_BASE +#define MACH_CNTXT_BAD_VPN MIPS_3K_CNTXT_BAD_VPN +#endif /* pmax */ + +#ifdef pica +#define MACH_CNTXT_PTE_BASE MIPS_4K_CNTXT_PTE_BASE +#define MACH_CNTXT_BAD_VPN2 MIPS_4K_CNTXT_BAD_VPN2 +#endif /* pica */ + + + +/* + * Location of exception vectors. + * + * Common vectors: reset and UTLB miss. + */ +#define MACH_RESET_EXC_VEC 0xBFC00000 +#define MACH_UTLB_MISS_EXC_VEC 0x80000000 + +/* + * R3000 general exception vector (everything else) + */ +#define MIPS_3K_GEN_EXC_VEC 0x80000080 + +/* + * R4000 MIPS-III exception vectors + */ +#define MIPS_4K_XTLB_MISS_EXC_VEC 0x80000080 +#define MIPS_4K_CACHE_ERR_EXC_VEC 0x80000100 +#define MIPS_4K_GEN_EXC_VEC 0x80000180 + +/* + * Backwards compatbility -- XXX more thought + */ +#ifdef pmax +#define MACH_GEN_EXC_VEC MIPS_3K_GEN_EXC_VEC +#endif /* pmax */ + +#ifdef pica +#define MACH_GEN_EXC_VEC MIPS_4K_GEN_EXC_VEC +#define MACH_TLB_MISS_EXC_VEC MACH_UTLB_MISS_EXC_VEC /* locore compat */ +#define MACH_XTLB_MISS_EXC_VEC MIPS_4K_XTLB_MISS_EXC_VEC +#define MACH_CACHE_ERR_EXC_VEC MIPS_4K_CACHE_ERR_EXC_VEC +#endif /* pica */ + + + +/* + * Coprocessor 0 registers: + * + * MACH_COP_0_TLB_INDEX TLB index. + * MACH_COP_0_TLB_RANDOM TLB random. + * MACH_COP_0_TLB_LOW r3k TLB entry low. + * MACH_COP_0_TLB_LO0 r4k TLB entry low. + * MACH_COP_0_TLB_LO1 r4k TLB entry low, extended. + * MACH_COP_0_TLB_CONTEXT TLB context. + * MACH_COP_0_BAD_VADDR Bad virtual address. + * MACH_COP_0_TLB_HI TLB entry high. + * MACH_COP_0_STATUS_REG Status register. + * MACH_COP_0_CAUSE_REG Exception cause register. + * MACH_COP_0_EXC_PC Exception PC. + * MACH_COP_0_PRID Processor revision identifier. + */ +#define MACH_COP_0_TLB_INDEX $0 +#define MACH_COP_0_TLB_RANDOM $1 + /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ + +#define MACH_COP_0_TLB_CONTEXT $4 + /* $5 and $6 new with MIPS-III */ +#define MACH_COP_0_BAD_VADDR $8 +#define MACH_COP_0_TLB_HI $10 +#define MACH_COP_0_STATUS_REG $12 +#define MACH_COP_0_CAUSE_REG $13 +#define MACH_COP_0_EXC_PC $14 +#define MACH_COP_0_PRID $15 + + +/* r3k-specific */ +#define MACH_COP_0_TLB_LOW $2 + +/* MIPS-III additions */ +#define MACH_COP_0_TLB_LO0 $2 +#define MACH_COP_0_TLB_LO1 $3 + +#define MACH_COP_0_TLB_PG_MASK $5 +#define MACH_COP_0_TLB_WIRED $6 + +#define MACH_COP_0_CONFIG $16 +#define MACH_COP_0_LLADDR $17 +#define MACH_COP_0_WATCH_LO $18 +#define MACH_COP_0_WATCH_HI $19 +#define MACH_COP_0_TLB_XCONTEXT $20 +#define MACH_COP_0_ECC $26 +#define MACH_COP_0_CACHE_ERR $27 +#define MACH_COP_0_TAG_LO $28 +#define MACH_COP_0_TAG_HI $29 +#define MACH_COP_0_ERROR_PC $30 + + + +/* + * Values for the code field in a break instruction. + */ +#define MACH_BREAK_INSTR 0x0000000d +#define MACH_BREAK_VAL_MASK 0x03ff0000 +#define MACH_BREAK_VAL_SHIFT 16 +#define MACH_BREAK_KDB_VAL 512 +#define MACH_BREAK_SSTEP_VAL 513 +#define MACH_BREAK_BRKPT_VAL 514 +#define MACH_BREAK_SOVER_VAL 515 +#define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ + (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) +#define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ + (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) +#define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ + (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) +#define MACH_BREAK_SOVER (MACH_BREAK_INSTR | \ + (MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT)) + +/* + * Mininum and maximum cache sizes. + */ +#define MACH_MIN_CACHE_SIZE (16 * 1024) +#define MACH_MAX_CACHE_SIZE (256 * 1024) + +/* + * The floating point version and status registers. + */ +#define MACH_FPC_ID $0 +#define MACH_FPC_CSR $31 + +/* + * The floating point coprocessor status register bits. + */ +#define MACH_FPC_ROUNDING_BITS 0x00000003 +#define MACH_FPC_ROUND_RN 0x00000000 +#define MACH_FPC_ROUND_RZ 0x00000001 +#define MACH_FPC_ROUND_RP 0x00000002 +#define MACH_FPC_ROUND_RM 0x00000003 +#define MACH_FPC_STICKY_BITS 0x0000007c +#define MACH_FPC_STICKY_INEXACT 0x00000004 +#define MACH_FPC_STICKY_UNDERFLOW 0x00000008 +#define MACH_FPC_STICKY_OVERFLOW 0x00000010 +#define MACH_FPC_STICKY_DIV0 0x00000020 +#define MACH_FPC_STICKY_INVALID 0x00000040 +#define MACH_FPC_ENABLE_BITS 0x00000f80 +#define MACH_FPC_ENABLE_INEXACT 0x00000080 +#define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 +#define MACH_FPC_ENABLE_OVERFLOW 0x00000200 +#define MACH_FPC_ENABLE_DIV0 0x00000400 +#define MACH_FPC_ENABLE_INVALID 0x00000800 +#define MACH_FPC_EXCEPTION_BITS 0x0003f000 +#define MACH_FPC_EXCEPTION_INEXACT 0x00001000 +#define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 +#define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 +#define MACH_FPC_EXCEPTION_DIV0 0x00008000 +#define MACH_FPC_EXCEPTION_INVALID 0x00010000 +#define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 +#define MACH_FPC_COND_BIT 0x00800000 +#define MACH_FPC_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ +#define MIPS_3K_FPC_MBZ_BITS 0xff7c0000 +#define MIPS_4K_FPC_MBZ_BITS 0xfe7c0000 + + +/* + * Constants to determine if have a floating point instruction. + */ +#define MACH_OPCODE_SHIFT 26 +#define MACH_OPCODE_C1 0x11 + + + +/* + * The low part of the TLB entry. + */ +#define VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT 12 +#define VMMACH_MIPS_3K_TLB_PF_NUM 0xfffff000 +#define VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT 0x00000800 +#define VMMACH_MIPS_3K_TLB_MOD_BIT 0x00000400 +#define VMMACH_MIPS_3K_TLB_VALID_BIT 0x00000200 +#define VMMACH_MIPS_3K_TLB_GLOBAL_BIT 0x00000100 + +#define VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT 6 +#define VMMACH_MIPS_4K_TLB_PF_NUM 0x3fffffc0 +#define VMMACH_MIPS_4K_TLB_ATTR_MASK 0x00000038 +#define VMMACH_MIPS_4K_TLB_MOD_BIT 0x00000004 +#define VMMACH_MIPS_4K_TLB_VALID_BIT 0x00000002 +#define VMMACH_MIPS_4K_TLB_GLOBAL_BIT 0x00000001 + + +#ifdef pmax /* XXX */ +#define VMMACH_TLB_PHYS_PAGE_SHIFT VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT +#define VMMACH_TLB_PF_NUM VMMACH_MIPS_3K_TLB_PF_NUM +#define VMMACH_TLB_NON_CACHEABLE_BIT VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT +#define VMMACH_TLB_MOD_BIT VMMACH_MIPS_3K_TLB_MOD_BIT +#define VMMACH_TLB_VALID_BIT VMMACH_MIPS_3K_TLB_VALID_BIT +#define VMMACH_TLB_GLOBAL_BIT VMMACH_MIPS_3K_TLB_GLOBAL_BIT +#endif /* pmax */ + +#ifdef pica /* XXX */ +#define VMMACH_TLB_PHYS_PAGE_SHIFT VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT +#define VMMACH_TLB_PF_NUM VMMACH_MIPS_4K_TLB_PF_NUM +#define VMMACH_TLB_ATTR_MASK VMMACH_MIPS_4K_TLB_ATTR_MASK +#define VMMACH_TLB_MOD_BIT VMMACH_MIPS_4K_TLB_MOD_BIT +#define VMMACH_TLB_VALID_BIT VMMACH_MIPS_4K_TLB_VALID_BIT +#define VMMACH_TLB_GLOBAL_BIT VMMACH_MIPS_4K_TLB_GLOBAL_BIT +#endif /* pica */ + + + +/* + * The high part of the TLB entry. + */ +#define VMMACH_TLB_VIRT_PAGE_SHIFT 12 + +#define VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM 0xfffff000 +#define VMMACH_TLB_MIPS_3K_PID 0x00000fc0 +#define VMMACH_TLB_MIPS_3K_PID_SHIFT 6 + +#define VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM 0xffffe000 +#define VMMACH_TLB_MIPS_4K_PID 0x000000ff +#define VMMACH_TLB_MIPS_4K_PID_SHIFT 0 + +/* XXX needs more thought */ +/* + * backwards XXX needs more thought, should support runtime decisions. + */ + +#ifdef pmax +#define VMMACH_TLB_VIRT_PAGE_NUM VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM +#define VMMACH_TLB_PID VMMACH_TLB_MIPS_3K_PID +#define VMMACH_TLB_PID_SHIFT VMMACH_TLB_MIPS_3K_PID_SHIFT +#endif + +#ifdef pica +#define VMMACH_TLB_VIRT_PAGE_NUM VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM +#define VMMACH_TLB_PID VMMACH_TLB_MIPS_4K_PID +#define VMMACH_TLB_PID_SHIFT VMMACH_TLB_MIPS_4K_PID_SHIFT +#endif + +/* + * r3000: shift count to put the index in the right spot. + * (zero on r4000?) + */ +#define VMMACH_TLB_INDEX_SHIFT 8 + + +/* + * The number of TLB entries and the first one that write random hits. + */ +#define VMMACH_MIPS_3K_NUM_TLB_ENTRIES 64 +#define VMMACH_MIPS_3K_FIRST_RAND_ENTRY 8 + +#define VMMACH_MIPS_4K_NUM_TLB_ENTRIES 48 +#define VMMACH_MIPS_4K_WIRED_ENTRIES 8 + +/* compatibility with existing locore -- XXX more thought */ +#ifdef pmax +#define VMMACH_NUM_TLB_ENTRIES VMMACH_MIPS_3K_NUM_TLB_ENTRIES +#define VMMACH_FIRST_RAND_ENTRY VMMACH_MIPS_3K_FIRST_RAND_ENTRY +#endif /* pmax */ + +#ifdef pica +#define VMMACH_NUM_TLB_ENTRIES VMMACH_MIPS_4K_NUM_TLB_ENTRIES +#define VMMACH_WIRED_ENTRIES VMMACH_MIPS_4K_WIRED_ENTRIES +#endif /* pica */ + + +/* + * The number of process id entries. + */ +#define VMMACH_MIPS_3K_NUM_PIDS 64 +#define VMMACH_MIPS_4K_NUM_PIDS 256 + +#ifdef pmax +#define VMMACH_NUM_PIDS VMMACH_MIPS_3K_NUM_PIDS +#endif /* pmax */ +#ifdef pica +#define VMMACH_NUM_PIDS VMMACH_MIPS_4K_NUM_PIDS +#endif /* pica */ + + +/* + * TLB probe return codes. + */ +#define VMMACH_TLB_NOT_FOUND 0 +#define VMMACH_TLB_FOUND 1 +#define VMMACH_TLB_FOUND_WITH_PATCH 2 +#define VMMACH_TLB_PROBE_ERROR 3 + +#endif /* _MACHCONST */ diff --git a/sys/arch/pmax/include/ecoff.h b/sys/arch/pmax/include/ecoff.h index 91631b47cf9..ceee6c6a420 100644 --- a/sys/arch/pmax/include/ecoff.h +++ b/sys/arch/pmax/include/ecoff.h @@ -1,3 +1,46 @@ -/* $NetBSD: ecoff.h,v 1.5 1996/03/19 03:17:24 jonathan Exp $ */ +/* $NetBSD: ecoff.h,v 1.5 1996/05/09 23:46:18 cgd Exp $ */ -#include <mips/ecoff.h> +/* + * Copyright (c) 1994 Adam Glass + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Adam Glass. + * 4. The name of the Author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Adam Glass BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define ECOFF_LDPGSZ 4096 + +#define ECOFF_PAD + +#define ECOFF_MACHDEP \ + u_long gprmask; \ + u_long cprmask[4]; \ + u_long gp_value + +#define ECOFF_MAGIC_MIPSEL 0x0162 +#define ECOFF_BADMAG(ep) ((ep)->f.f_magic != ECOFF_MAGIC_MIPSEL) + +#define ECOFF_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16) diff --git a/sys/arch/pmax/include/elf.h b/sys/arch/pmax/include/elf.h index ab305c5df17..b14ddc36640 100644 --- a/sys/arch/pmax/include/elf.h +++ b/sys/arch/pmax/include/elf.h @@ -1,3 +1,137 @@ -/* $NetBSD: elf.h,v 1.3 1996/03/19 03:06:41 jonathan Exp $ */ +/* $NetBSD: elf.h,v 1.3.4.1 1996/06/26 06:39:09 jtc Exp $ */ -#include <mips/elf.h> +/* + * Copyright (c) 1994 Ted Lemon + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __MACHINE_ELF_H__ +#define __MACHINE_ELF_H__ + +/* ELF executable header... */ +struct ehdr { + char elf_magic [4]; /* Elf magic number... */ + unsigned long magic [3]; /* Magic number... */ + unsigned short type; /* Object file type... */ + unsigned short machine; /* Machine ID... */ + unsigned long version; /* File format version... */ + unsigned long entry; /* Entry point... */ + unsigned long phoff; /* Program header table offset... */ + unsigned long shoff; /* Section header table offset... */ + unsigned long flags; /* Processor-specific flags... */ + unsigned short ehsize; /* Elf header size in bytes... */ + unsigned short phsize; /* Program header size... */ + unsigned short phcount; /* Program header count... */ + unsigned short shsize; /* Section header size... */ + unsigned short shcount; /* Section header count... */ + unsigned short shstrndx; /* Section header string table index... */ +}; + +/* Program header... */ +struct phdr { + unsigned long type; /* Segment type... */ + unsigned long offset; /* File offset... */ + unsigned long vaddr; /* Virtual address... */ + unsigned long paddr; /* Physical address... */ + unsigned long filesz; /* Size of segment in file... */ + unsigned long memsz; /* Size of segment in memory... */ + unsigned long flags; /* Segment flags... */ + unsigned long align; /* Alighment, file and memory... */ +}; + +/* Section header... */ +struct shdr { + unsigned long name; /* Offset into string table of section name */ + unsigned long type; /* Type of section... */ + unsigned long flags; /* Section flags... */ + unsigned long addr; /* Section virtual address at execution... */ + unsigned long offset; /* Section file offset... */ + unsigned long size; /* Section size... */ + unsigned long link; /* Link to another section... */ + unsigned long info; /* Additional section info... */ + unsigned long align; /* Section alignment... */ + unsigned long esize; /* Entry size if section holds table... */ +}; + +/* Symbol table entry... */ +struct sym { + unsigned long name; /* Index into strtab of symbol name. */ + unsigned long value; /* Section offset, virt addr or common align. */ + unsigned long size; /* Size of object referenced. */ + unsigned type : 4; /* Symbol type (e.g., function, data)... */ + unsigned binding : 4; /* Symbol binding (e.g., global, local)... */ + unsigned char other; /* Unused. */ + unsigned short shndx; /* Section containing symbol. */ +}; + +/* Values for program header type field */ + +#define PT_NULL 0 /* Program header table entry unused */ +#define PT_LOAD 1 /* Loadable program segment */ +#define PT_DYNAMIC 2 /* Dynamic linking information */ +#define PT_INTERP 3 /* Program interpreter */ +#define PT_NOTE 4 /* Auxiliary information */ +#define PT_SHLIB 5 /* Reserved, unspecified semantics */ +#define PT_PHDR 6 /* Entry for header table itself */ +#define PT_LOPROC 0x70000000 /* Processor-specific */ +#define PT_HIPROC 0x7FFFFFFF /* Processor-specific */ +#define PT_MIPS_REGINFO PT_LOPROC /* Mips reginfo section... */ + +/* Program segment permissions, in program header flags field */ + +#define PF_X (1 << 0) /* Segment is executable */ +#define PF_W (1 << 1) /* Segment is writable */ +#define PF_R (1 << 2) /* Segment is readable */ +#define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */ + +/* Reserved section indices... */ +#define SHN_UNDEF 0 +#define SHN_ABS 0xfff1 +#define SHN_COMMON 0xfff2 +#define SHN_MIPS_ACOMMON 0xfff0 + +/* Symbol bindings... */ +#define STB_LOCAL 0 +#define STB_GLOBAL 1 +#define STB_WEAK 2 + +/* Symbol types... */ +#define STT_NOTYPE 0 +#define STT_OBJECT 1 +#define STT_FUNC 2 +#define STT_SECTION 3 +#define STT_FILE 4 + +#define MIPS_ELF_HDR_SIZE (sizeof (struct ehdr)) +#ifdef _KERNEL +int mips_elf_makecmds __P((struct proc *, struct exec_package *)); +#endif /* _KERNEL */ +#endif /* __MACHINE_ELF_H__ */ diff --git a/sys/arch/pmax/include/endian.h b/sys/arch/pmax/include/endian.h index 60f1fef7fca..33ecdafd7b5 100644 --- a/sys/arch/pmax/include/endian.h +++ b/sys/arch/pmax/include/endian.h @@ -1,3 +1,97 @@ -/* $NetBSD: endian.h,v 1.5 1996/03/19 03:06:50 jonathan Exp $ */ +/* $NetBSD: endian.h,v 1.5.4.1 1996/06/05 23:53:20 jonathan Exp $ */ -#include <mips/endian.h> +/* + * Copyright (c) 1987, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)endian.h 8.1 (Berkeley) 6/11/93 + */ + +#ifndef _ENDIAN_H_ +#define _ENDIAN_H_ + +/* + * Define _NOQUAD if the compiler does NOT support 64-bit integers. + */ +/* #define _NOQUAD */ + +/* + * Define the order of 32-bit words in 64-bit words. + */ +#define _QUAD_HIGHWORD 1 +#define _QUAD_LOWWORD 0 + +#ifndef _POSIX_SOURCE +/* + * Definitions for byte order, according to byte significance from low + * address to high. + */ +#define LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ +#define BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ +#define PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */ + +#define BYTE_ORDER LITTLE_ENDIAN + +#include <sys/cdefs.h> +#include <pmax/types.h> + +__BEGIN_DECLS +u_int32_t htonl __P((u_int32_t)); + + +u_int16_t htons __P((u_int16_t)); +u_int32_t ntohl __P((u_int32_t)); +u_int16_t ntohs __P((u_int16_t)); +__END_DECLS + +/* + * Macros for network/external number representation conversion. + */ +#if BYTE_ORDER == BIG_ENDIAN && !defined(lint) +#define ntohl(x) (x) +#define ntohs(x) (x) +#define htonl(x) (x) +#define htons(x) (x) + +#define NTOHL(x) (x) +#define NTOHS(x) (x) +#define HTONL(x) (x) +#define HTONS(x) (x) + +#else + +#define NTOHL(x) (x) = ntohl((u_int32_t)x) +#define NTOHS(x) (x) = ntohs((u_int16_t)x) +#define HTONL(x) (x) = htonl((u_int32_t)x) +#define HTONS(x) (x) = htons((u_int16_t)x) +#endif +#endif /* ! _POSIX_SOURCE */ +#endif /* !_ENDIAN_H_ */ diff --git a/sys/arch/pmax/include/exec.h b/sys/arch/pmax/include/exec.h index bf90c5ce358..5325a407c92 100644 --- a/sys/arch/pmax/include/exec.h +++ b/sys/arch/pmax/include/exec.h @@ -1,3 +1,57 @@ -/* $NetBSD: exec.h,v 1.6 1996/03/19 03:07:02 jonathan Exp $ */ +/* $OpenBSD: exec.h,v 1.4 1996/09/29 11:36:27 deraadt Exp $ */ +/* $NetBSD: exec.h,v 1.5 1994/10/26 21:09:39 cgd Exp $ */ + +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)exec.h 8.1 (Berkeley) 6/10/93 + */ + +#define __LDPGSZ 4096 + +/* + * Define what exec "formats" we should handle. + */ +#define NATIVE_EXEC_ELF +#define EXEC_SCRIPT + +#define ELF_TARG_CLASS ELFCLASS32 +#define ELF_TARG_DATA ELFDATA2LSB +#define ELF_TARG_MACH EM_MIPS + +/* + * This is what we want nlist(3) to handle. + */ +#define DO_AOUT /* support a.out */ +#define DO_ELF /* support ELF */ +#define DO_ECOFF /* support ECOFF */ -#include <mips/exec.h> diff --git a/sys/arch/pmax/include/float.h b/sys/arch/pmax/include/float.h index 5c78fe23f21..2e4e7079a70 100644 --- a/sys/arch/pmax/include/float.h +++ b/sys/arch/pmax/include/float.h @@ -1,3 +1,80 @@ -/* $NetBSD: float.h,v 1.9 1996/03/19 03:07:19 jonathan Exp $ */ +/* $NetBSD: float.h,v 1.8 1996/03/18 22:40:22 jonathan Exp $ */ -#include <mips/float.h> +/* + * Copyright (c) 1989, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)float.h 8.1 (Berkeley) 6/10/93 + */ + +#ifndef _MIPS_FLOAT_H_ +#define _MIPS_FLOAT_H_ + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds(); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#define FLT_ROUNDS __flt_rounds() + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP -125 /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP -37 /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP -1021 +#define DBL_MIN 2.225073858507201E-308 +#define DBL_MIN_10_EXP -307 +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.797693134862316E+308 +#define DBL_MAX_10_EXP 308 + +#define LDBL_MANT_DIG DBL_MANT_DIG +#define LDBL_EPSILON DBL_EPSILON +#define LDBL_DIG DBL_DIG +#define LDBL_MIN_EXP DBL_MIN_EXP +#define LDBL_MIN DBL_MIN +#define LDBL_MIN_10_EXP DBL_MIN_10_EXP +#define LDBL_MAX_EXP DBL_MAX_EXP +#define LDBL_MAX DBL_MAX +#define LDBL_MAX_10_EXP DBL_MAX_10_EXP + +#endif /* _MIPS_FLOAT_H_ */ diff --git a/sys/arch/pmax/include/ieeefp.h b/sys/arch/pmax/include/ieeefp.h index 51bdb4564a5..65ea3fed16c 100644 --- a/sys/arch/pmax/include/ieeefp.h +++ b/sys/arch/pmax/include/ieeefp.h @@ -3,4 +3,21 @@ * Public domain. */ -#include <mips/ieeefp.h> +#ifndef _MIPS_IEEEFP_H_ +#define _MIPS_IEEEFP_H_ + +typedef int fp_except; +#define FP_X_IMP 0x01 /* imprecise (loss of precision) */ +#define FP_X_UFL 0x02 /* underflow exception */ +#define FP_X_OFL 0x04 /* overflow exception */ +#define FP_X_DZ 0x08 /* divide-by-zero exception */ +#define FP_X_INV 0x10 /* invalid operation exception */ + +typedef enum { + FP_RN=0, /* round to nearest representable number */ + FP_RZ=1, /* round to zero (truncate) */ + FP_RP=2, /* round toward positive infinity */ + FP_RM=3 /* round toward negative infinity */ +} fp_rnd; + +#endif /* _MIPS_IEEEFP_H_ */ diff --git a/sys/arch/pmax/include/kdbparam.h b/sys/arch/pmax/include/kdbparam.h index 320bf53e779..9104c87aa3c 100644 --- a/sys/arch/pmax/include/kdbparam.h +++ b/sys/arch/pmax/include/kdbparam.h @@ -1,3 +1,74 @@ -/* $NetBSD: kdbparam.h,v 1.5 1996/03/19 04:39:08 jonathan Exp $ */ +/* $NetBSD: kdbparam.h,v 1.4 1994/10/26 21:09:42 cgd Exp $ */ -#include <mips/kdbparam.h> +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)kdbparam.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * Machine dependent definitions for kdb. + */ + +#if BYTE_ORDER == LITTLE_ENDIAN +#define kdbshorten(w) ((w) & 0xFFFF) +#define kdbbyte(w) ((w) & 0xFF) +#define kdbitol(a,b) ((long)(((b) << 16) | ((a) & 0xFFFF))) +#define kdbbtol(a) ((long)(a)) +#endif + +#define LPRMODE "%R" +#define OFFMODE "+%R" + +#define SETBP(ins) MACH_BREAK_BRKPT + +/* return the program counter value modified if we are in a delay slot */ +#define kdbgetpc(pcb) (kdbvar[kdbvarchk('t')] < 0 ? \ + (pcb).pcb_regs[34] + 4 : (pcb).pcb_regs[34]) +#define kdbishiddenreg(p) ((p) >= &kdbreglist[33]) +#define kdbisbreak(type) (((type) & MACH_CR_EXC_CODE) == 0x24) + +/* check for address wrap around */ +#define kdbaddrwrap(addr,newaddr) (((addr)^(newaddr)) >> 31) + +/* declare machine dependent routines defined in kadb.c */ +void kdbprinttrap __P((unsigned, unsigned)); +void kdbsetsstep __P((void)); +void kdbclrsstep __P((void)); +void kdbreadc __P((char *)); +void kdbwrite __P((char *, int)); +void kdbprintins __P((int, long)); +void kdbstacktrace __P((int)); +char *kdbmalloc __P((int)); diff --git a/sys/arch/pmax/include/limits.h b/sys/arch/pmax/include/limits.h index 0d0f743ff27..f1d28a3701c 100644 --- a/sys/arch/pmax/include/limits.h +++ b/sys/arch/pmax/include/limits.h @@ -1,7 +1,99 @@ -/* $NetBSD: limits.h,v 1.10 1996/03/19 03:09:03 jonathan Exp $ */ +/* $NetBSD: limits.h,v 1.9 1996/03/19 02:45:48 jonathan Exp $ */ -#include <mips/limits.h> +/* + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)limits.h 8.3 (Berkeley) 1/4/94 + */ +#define CHAR_BIT 8 /* number of bits in a char */ +#define MB_LEN_MAX 6 /* Allow 31 bit UTF2 */ + +/* + * According to ANSI (section 2.2.4.2), the values below must be usable by + * #if preprocessing directives. Additionally, the expression must have the + * same type as would an expression that is an object of the corresponding + * type converted according to the integral promotions. The subtraction for + * INT_MIN and LONG_MIN is so the value is not unsigned; 2147483648 is an + * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). + * These numbers work for pcc as well. The UINT_MAX and ULONG_MAX values + * are written as hex so that GCC will be quiet about large integer constants. + */ +#define SCHAR_MAX 127 /* min value for a signed char */ +#define SCHAR_MIN (-128) /* max value for a signed char */ + +#define UCHAR_MAX 255 /* max value for an unsigned char */ +#define CHAR_MAX 127 /* max value for a char */ +#define CHAR_MIN (-128) /* min value for a char */ + +#define USHRT_MAX 65535 /* max value for an unsigned short */ +#define SHRT_MAX 32767 /* max value for a short */ +#define SHRT_MIN (-32768) /* min value for a short */ + +#define UINT_MAX 0xffffffff /* max value for an unsigned int */ +#define INT_MAX 2147483647 /* max value for an int */ +#define INT_MIN (-2147483647-1) /* min value for an int */ + +#define ULONG_MAX 0xffffffff /* max value for an unsigned long */ +#define LONG_MAX 2147483647 /* max value for a long */ +#define LONG_MIN (-2147483647-1) /* min value for a long */ + +#if !defined(_ANSI_SOURCE) +#define SSIZE_MAX INT_MAX /* max value for a ssize_t */ + +#if !defined(_POSIX_SOURCE) && !defined(_XOPEN_SOURCE) +#define SIZE_T_MAX UINT_MAX /* max value for a size_t */ + +/* GCC requires that quad constants be written as expressions. */ +#define UQUAD_MAX ((u_quad_t)0-1) /* max value for a uquad_t */ + /* max value for a quad_t */ +#define QUAD_MAX ((quad_t)(UQUAD_MAX >> 1)) +#define QUAD_MIN (-QUAD_MAX-1) /* min value for a quad_t */ + +#endif /* !_POSIX_SOURCE && !_XOPEN_SOURCE */ +#endif /* !_ANSI_SOURCE */ + +#if (!defined(_ANSI_SOURCE)&&!defined(_POSIX_SOURCE)) || defined(_XOPEN_SOURCE) +#define LONG_BIT 32 +#define WORD_BIT 32 + +#define DBL_DIG 15 +#define DBL_MAX 1.797693134862316E+308 +#define DBL_MIN 2.225073858507201E-308 + +#define FLT_DIG 6 +#define FLT_MAX 3.40282347E+38F +#define FLT_MIN 1.17549435E-38F +#endif #ifdef _KERNEL #define CLK_TCK 60 /* ticks per second */ #endif diff --git a/sys/arch/pmax/include/locore.h b/sys/arch/pmax/include/locore.h index c837262a72d..dda4f72c628 100644 --- a/sys/arch/pmax/include/locore.h +++ b/sys/arch/pmax/include/locore.h @@ -1,4 +1,4 @@ -/* $NetBSD: locore.h,v 1.2 1996/05/20 23:49:11 jonathan Exp $ */ +/* $NetBSD: locore.h,v 1.2 1996/05/20 23:38:26 jonathan Exp $ */ /* * Copyright 1996 The Board of Trustees of The Leland Stanford @@ -11,8 +11,118 @@ * makes no representations about the suitability of this * software for any purpose. It is provided "as is" without * express or implied warranty. + */ + +/* + * Jump table for MIPS cpu locore functions that are implemented + * differently on different generations, or instruction-level + * archtecture (ISA) level, the Mips family. + * The following functions must be provided for each mips ISA level: + * + * + * MachConfigCache + * MachFlushCache + * MachFlushDCache + * MachFlushICache + * MachForceCacheUpdate + * MachSetPID + * MachTLBFlush + * MachTLBFlushAddr __P() + * MachTLBUpdate (u_int, (pt_entry_t?) u_int); + * MachTLBWriteIndexed * - * This file contributed by Jonathan Stone + * We currently provide support for: + * + * r2000 and r3000 (mips ISA-I) + * r4000 and r4400 in 32-bit mode (mips ISA-III?) + */ + +#ifndef _MIPS_LOCORE_H +#define _MIPS_LOCORE_H + +/* + * locore functions used by vm_machdep.c. + * These are not yet CPU-model specific. + */ + +struct user; +extern int copykstack __P((struct user *up)); +extern void MachSaveCurFPState __P((struct proc *p)); +extern int switch_exit __P((void)); /* XXX never really returns? */ + +/* MIPS-generic locore functions used by trap.c */ + extern void MachFPTrap __P((u_int statusReg, u_int CauseReg, u_int pc)); + +/* + * locore service routine for exeception vectors. Used outside locore + * only to print them by name in stack tracebacks + */ + +extern void mips_r2000_KernIntr __P(()); + +extern void mips_r2000_ConfigCache __P((void)); +extern void mips_r2000_FlushCache __P((void)); +extern void mips_r2000_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); +extern void mips_r2000_FlushICache __P((vm_offset_t addr, vm_offset_t len)); +extern void mips_r2000_ForceCacheUpdate __P((void)); +extern void mips_r2000_SetPID __P((int pid)); +extern void mips_r2000_TLBFlush __P((void)); +extern void mips_r2000_TLBFlushAddr __P( /* XXX Really pte highpart ? */ + (vm_offset_t addr)); +extern void mips_r2000_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); +extern void mips_r2000_TLBWriteIndexed __P((u_int index, u_int high, + u_int low)); + +extern void mips_r4000_ConfigCache __P((void)); +extern void mips_r4000_FlushCache __P((void)); +extern void mips_r4000_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); +extern void mips_r4000_FlushICache __P((vm_offset_t addr, vm_offset_t len)); +extern void mips_r4000_ForceCacheUpdate __P((void)); +extern void mips_r4000_SetPID __P((int pid)); +extern void mips_r4000_TLBFlush __P((void)); +extern void mips_r4000_TLBFlushAddr __P( /* XXX Really pte highpart ? */ + (vm_offset_t addr)); +extern void mips_r4000_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); +extern void mips_r4000_TLBWriteIndexed __P((u_int index, u_int high, + u_int low)); + +/* + * A vector with an entry for each mips-ISA-level dependent + * locore function, and macros which jump through it. + * XXX the macro names are chosen to be compatible with the old + * Sprite coding-convention names used in 4.4bsd/pmax. */ +typedef struct { + void (*configCache) __P((void)); + void (*flushCache) __P((void)); + void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len)); + void (*flushICache) __P((vm_offset_t addr, vm_offset_t len)); + void (*forceCacheUpdate) __P((void)); + void (*setTLBpid) __P((int pid)); + void (*tlbFlush) __P((void)); + void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */ + void (*tlbUpdate) __P((u_int highreg, u_int lowreg)); + void (*tlbWriteIndexed) __P((u_int, u_int, u_int)); +} mips_locore_jumpvec_t; + + +/* + * The "active" locore-fuction vector, and + + */ +extern mips_locore_jumpvec_t mips_locore_jumpvec; +extern mips_locore_jumpvec_t r2000_locore_vec; +extern mips_locore_jumpvec_t r4000_locore_vec; + +#define MachConfigCache (*(mips_locore_jumpvec.configCache)) +#define MachFlushCache (*(mips_locore_jumpvec.flushCache)) +#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) +#define MachFlushICache (*(mips_locore_jumpvec.flushICache)) +#define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) +#define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) +#define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush)) +#define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) +#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) +#define MachTLBWriteIndexed (*(mips_locore_jumpvec.tlbWriteIndexed)) -#include <mips/locore.h> +#endif /* _MIPS_LOCORE_H */ diff --git a/sys/arch/pmax/include/machAsmDefs.h b/sys/arch/pmax/include/machAsmDefs.h index 8f6c09b0a18..a6c6e932020 100644 --- a/sys/arch/pmax/include/machAsmDefs.h +++ b/sys/arch/pmax/include/machAsmDefs.h @@ -1,3 +1,3 @@ /* $NetBSD: machAsmDefs.h,v 1.8 1996/03/25 02:55:18 jonathan Exp $ */ -#include <mips/asm.h> +#include <pmax/asm.h> diff --git a/sys/arch/pmax/include/mips_opcode.h b/sys/arch/pmax/include/mips_opcode.h index 44b968860db..7234040770f 100644 --- a/sys/arch/pmax/include/mips_opcode.h +++ b/sys/arch/pmax/include/mips_opcode.h @@ -1,8 +1,261 @@ -/* $NetBSD: mips_opcode.h,v 1.6 1996/03/23 19:10:06 jonathan Exp $ */ +/* $NetBSD: mips_opcode.h,v 1.5 1996/03/23 18:49:29 jonathan Exp $ */ + +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93 + */ /* * Define the instruction formats and opcode values for the * MIPS instruction set. */ -#include <mips/mips_opcode.h> +/* + * Define the instruction formats. + */ +typedef union { + unsigned word; + +#if BYTE_ORDER == LITTLE_ENDIAN + struct { + unsigned imm: 16; + unsigned rt: 5; + unsigned rs: 5; + unsigned op: 6; + } IType; + + struct { + unsigned target: 26; + unsigned op: 6; + } JType; + + struct { + unsigned func: 6; + unsigned shamt: 5; + unsigned rd: 5; + unsigned rt: 5; + unsigned rs: 5; + unsigned op: 6; + } RType; + + struct { + unsigned func: 6; + unsigned fd: 5; + unsigned fs: 5; + unsigned ft: 5; + unsigned fmt: 4; + unsigned : 1; /* always '1' */ + unsigned op: 6; /* always '0x11' */ + } FRType; +#endif +} InstFmt; + +/* + * Values for the 'op' field. + */ +#define OP_SPECIAL 000 +#define OP_BCOND 001 +#define OP_J 002 +#define OP_JAL 003 +#define OP_BEQ 004 +#define OP_BNE 005 +#define OP_BLEZ 006 +#define OP_BGTZ 007 + +#define OP_ADDI 010 +#define OP_ADDIU 011 +#define OP_SLTI 012 +#define OP_SLTIU 013 +#define OP_ANDI 014 +#define OP_ORI 015 +#define OP_XORI 016 +#define OP_LUI 017 + +#define OP_COP0 020 +#define OP_COP1 021 +#define OP_COP2 022 +#define OP_COP3 023 +#define OP_BEQL 024 /* MIPS-II, for r4000 port */ +#define OP_BNEL 025 /* MIPS-II, for r4000 port */ +#define OP_BLEZL 026 /* MIPS-II, for r4000 port */ +#define OP_BGTZL 027 /* MIPS-II, for r4000 port */ + +#define OP_DADDI 030 /* MIPS-II, for r4000 port */ +#define OP_DADDIU 031 /* MIPS-II, for r4000 port */ +#define OP_LDL 032 /* MIPS-II, for r4000 port */ +#define OP_LDR 033 /* MIPS-II, for r4000 port */ + +#define OP_LB 040 +#define OP_LH 041 +#define OP_LWL 042 +#define OP_LW 043 +#define OP_LBU 044 +#define OP_LHU 045 +#define OP_LWR 046 +#define OP_LHU 045 +#define OP_LWR 046 +#define OP_LWU 047 /* MIPS-II, for r4000 port */ + +#define OP_SB 050 +#define OP_SH 051 +#define OP_SWL 052 +#define OP_SW 053 +#define OP_SDL 054 /* MIPS-II, for r4000 port */ +#define OP_SDR 055 /* MIPS-II, for r4000 port */ +#define OP_SWR 056 +#define OP_CACHE 057 /* MIPS-II, for r4000 port */ + +#define OP_LL 060 +#define OP_LWC0 OP_LL /* backwards source compatibility */ +#define OP_LWC1 061 +#define OP_LWC2 062 +#define OP_LWC3 063 +#define OP_LLD 064 /* MIPS-II, for r4000 port */ +#define OP_LD 067 /* MIPS-II, for r4000 port */ + +#define OP_SC 070 +#define OP_SWC0 OP_SC /* backwards source compatibility */ +#define OP_SWC1 071 +#define OP_SWC2 072 +#define OP_SWC3 073 +#define OP_SCD 074 /* MIPS-II, for r4000 port */ +#define OP_SD 077 /* MIPS-II, for r4000 port */ + +/* + * Values for the 'func' field when 'op' == OP_SPECIAL. + */ +#define OP_SLL 000 +#define OP_SRL 002 +#define OP_SRA 003 +#define OP_SLLV 004 +#define OP_SRLV 006 +#define OP_SRAV 007 + +#define OP_JR 010 +#define OP_JALR 011 +#define OP_SYSCALL 014 +#define OP_BREAK 015 +#define OP_SYNC 017 /* MIPS-II, for r4000 port */ + +#define OP_MFHI 020 +#define OP_MTHI 021 +#define OP_MFLO 022 +#define OP_MTLO 023 +#define OP_DSLLV 024 /* MIPS-II, for r4000 port */ +#define OP_DSRLV 026 /* MIPS-II, for r4000 port */ +#define OP_DSRAV 027 /* MIPS-II, for r4000 port */ + +#define OP_MULT 030 +#define OP_MULTU 031 +#define OP_DIV 032 +#define OP_DIVU 033 +#define OP_DMULT 034 /* MIPS-II, for r4000 port */ +#define OP_DMULTU 035 /* MIPS-II, for r4000 port */ +#define OP_DDIV 036 /* MIPS-II, for r4000 port */ +#define OP_DDIVU 037 /* MIPS-II, for r4000 port */ + +#define OP_ADD 040 +#define OP_ADDU 041 +#define OP_SUB 042 +#define OP_SUBU 043 +#define OP_AND 044 +#define OP_OR 045 +#define OP_XOR 046 +#define OP_NOR 047 + +#define OP_SLT 052 +#define OP_SLTU 053 +#define OP_DADD 054 /* MIPS-II, for r4000 port */ +#define OP_DADDU 055 /* MIPS-II, for r4000 port */ +#define OP_DSUB 056 /* MIPS-II, for r4000 port */ +#define OP_DSUBU 057 /* MIPS-II, for r4000 port */ + +#define OP_TGE 060 /* MIPS-II, for r4000 port */ +#define OP_TGEU 061 /* MIPS-II, for r4000 port */ +#define OP_TLT 062 /* MIPS-II, for r4000 port */ +#define OP_TLTU 063 /* MIPS-II, for r4000 port */ +#define OP_TEQ 064 /* MIPS-II, for r4000 port */ +#define OP_TNE 066 /* MIPS-II, for r4000 port */ + +#define OP_DSLL 070 /* MIPS-II, for r4000 port */ +#define OP_DSRL 072 /* MIPS-II, for r4000 port */ +#define OP_DSRA 073 /* MIPS-II, for r4000 port */ +#define OP_DSLL32 074 /* MIPS-II, for r4000 port */ +#define OP_DSRL32 076 /* MIPS-II, for r4000 port */ +#define OP_DSRA32 077 /* MIPS-II, for r4000 port */ + +/* + * Values for the 'func' field when 'op' == OP_BCOND. + */ +#define OP_BLTZ 000 +#define OP_BGEZ 001 +#define OP_BLTZL 002 /* MIPS-II, for r4000 port */ +#define OP_BGEZL 003 /* MIPS-II, for r4000 port */ + +#define OP_TGEI 010 /* MIPS-II, for r4000 port */ +#define OP_TGEIU 011 /* MIPS-II, for r4000 port */ +#define OP_TLTI 012 /* MIPS-II, for r4000 port */ +#define OP_TLTIU 013 /* MIPS-II, for r4000 port */ +#define OP_TEQI 014 /* MIPS-II, for r4000 port */ +#define OP_TNEI 016 /* MIPS-II, for r4000 port */ + +#define OP_BLTZAL 020 +#define OP_BLTZAL 020 /* MIPS-II, for r4000 port */ +#define OP_BGEZAL 021 +#define OP_BLTZALL 022 +#define OP_BGEZALL 023 + +/* + * Values for the 'rs' field when 'op' == OP_COPz. + */ +#define OP_MF 000 +#define OP_DMF 001 /* MIPS-II, for r4000 port */ +#define OP_MT 004 +#define OP_DMT 005 /* MIPS-II, for r4000 port */ +#define OP_BCx 010 +#define OP_BCy 014 +#define OP_CF 002 +#define OP_CT 006 + +/* + * Values for the 'rt' field when 'op' == OP_COPz. + */ +#define COPz_BC_TF_MASK 0x01 +#define COPz_BC_TRUE 0x01 +#define COPz_BC_FALSE 0x00 +#define COPz_BCL_TF_MASK 0x02 /* MIPS-II, for r4000 port */ +#define COPz_BCL_TRUE 0x02 /* MIPS-II, for r4000 port */ +#define COPz_BCL_FALSE 0x00 /* MIPS-II, for r4000 port */ diff --git a/sys/arch/pmax/include/mips_param.h b/sys/arch/pmax/include/mips_param.h new file mode 100644 index 00000000000..9c3ad6736be --- /dev/null +++ b/sys/arch/pmax/include/mips_param.h @@ -0,0 +1,82 @@ +/* $NetBSD: mips_param.h,v 1.1 1996/05/19 17:52:18 jonathan Exp $ */ + +/* + * Round p (pointer or byte index) up to a correctly-aligned value for all + * data types (int, long, ...). The result is u_int and must be cast to + * any desired pointer type. + */ +#define ALIGNBYTES 7 +#define ALIGN(p) (((u_int)(p) + ALIGNBYTES) &~ ALIGNBYTES) + +#define NBPG 4096 /* bytes/page */ +#define PGOFSET (NBPG-1) /* byte offset into page */ +#define PGSHIFT 12 /* LOG2(NBPG) */ +#define NPTEPG (NBPG/4) + +#define NBSEG 0x400000 /* bytes/segment */ +#define SEGOFSET (NBSEG-1) /* byte offset into segment */ +#define SEGSHIFT 22 /* LOG2(NBSEG) */ + +/* + * Size of kernel malloc arena in CLBYTES-sized logical pages + */ +#ifndef NKMEMCLUSTERS +#define NKMEMCLUSTERS (512*1024/CLBYTES) +#endif + +/* pages ("clicks") (4096 bytes) to disk blocks */ +#define ctod(x) ((x) << (PGSHIFT - DEV_BSHIFT)) +#define dtoc(x) ((x) >> (PGSHIFT - DEV_BSHIFT)) + +/* pages to bytes */ +#define ctob(x) ((x) << PGSHIFT) +#define btoc(x) (((x) + PGOFSET) >> PGSHIFT) + +/* bytes to disk blocks */ +#define btodb(x) ((x) >> DEV_BSHIFT) +#define dbtob(x) ((x) << DEV_BSHIFT) + +/* + * Map a ``block device block'' to a file system block. + * This should be device dependent, and should use the bsize + * field from the disk label. + * For now though just use DEV_BSIZE. + */ +#define bdbtofsb(bn) ((bn) / (BLKDEV_IOSIZE/DEV_BSIZE)) + +/* + * Mach derived conversion macros + */ +#define mips_round_page(x) ((((unsigned)(x)) + NBPG - 1) & ~(NBPG-1)) +#define mips_trunc_page(x) ((unsigned)(x) & ~(NBPG-1)) +#define mips_btop(x) ((unsigned)(x) >> PGSHIFT) +#define mips_ptob(x) ((unsigned)(x) << PGSHIFT) + +#ifdef _KERNEL +#ifndef _LOCORE +typedef int spl_t; +extern spl_t splx __P((spl_t)); +extern spl_t splsoftnet __P((void)), splsoftclock __P((void)); +extern spl_t splhigh __P((void)); +extern spl_t spl0 __P((void)); /* XXX should not enable TC on 3min */ + +extern void setsoftnet __P((void)), clearsoftnet __P((void)); +extern void setsoftclock __P((void)), clearsoftclock __P((void)); + + +extern int (*Mach_splnet) __P((void)), (*Mach_splbio) __P((void)), + (*Mach_splimp) __P((void)), (*Mach_spltty) __P((void)), + (*Mach_splclock) __P((void)), (*Mach_splstatclock) __P((void)), + (*Mach_splnone) __P((void)); +#define splnet() ((*Mach_splnet)()) +#define splbio() ((*Mach_splbio)()) +#define splimp() ((*Mach_splimp)()) +#define spltty() ((*Mach_spltty)()) +#define splclock() ((*Mach_splclock)()) +#define splstatclock() ((*Mach_splstatclock)()) + +extern void wbflush __P ((void)); /* XXX */ +extern void delay __P((int n)); + +#endif /* _LOCORE */ +#endif /* _KERNEL */ diff --git a/sys/arch/pmax/include/param.h b/sys/arch/pmax/include/param.h index 69e3cbff851..33eb0c3dc82 100644 --- a/sys/arch/pmax/include/param.h +++ b/sys/arch/pmax/include/param.h @@ -46,7 +46,7 @@ * Machine-dependent constants (VM, etc) common across MIPS cpus */ -#include <mips/mips_param.h> +#include <pmax/mips_param.h> /* * Machine dependent constants for DEC Station 3100. diff --git a/sys/arch/pmax/include/pcb.h b/sys/arch/pmax/include/pcb.h index 8de6211784c..2225ba81d83 100644 --- a/sys/arch/pmax/include/pcb.h +++ b/sys/arch/pmax/include/pcb.h @@ -1,3 +1,62 @@ -/* $NetBSD: pcb.h,v 1.7 1996/03/19 03:07:49 jonathan Exp $ */ +/* $NetBSD: pcb.h,v 1.6 1996/03/19 02:12:05 jonathan Exp $ */ -#include <mips/pcb.h> +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah Hdr: pcb.h 1.13 89/04/23 + * + * @(#)pcb.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * MIPS process control block + */ +struct pcb +{ + int pcb_regs[71]; /* saved CPU and floating point registers */ + label_t pcb_context; /* kernel context for resume */ + int pcb_onfault; /* for copyin/copyout faults */ + void *pcb_segtab; /* copy of pmap pm_segtab */ +}; + +/* + * The pcb is augmented with machine-dependent additional data for + * core dumps. For the MIPS, there is nothing to add. + */ +struct md_coredump { + long md_pad[8]; +}; diff --git a/sys/arch/pmax/include/pmap.h b/sys/arch/pmax/include/pmap.h index fba34a17110..4c5b9ca5b7e 100644 --- a/sys/arch/pmax/include/pmap.h +++ b/sys/arch/pmax/include/pmap.h @@ -1,6 +1,107 @@ -/* $NetBSD: pmap.h,v 1.10 1996/03/19 04:39:05 jonathan Exp $ */ +/* $NetBSD: pmap.h,v 1.9 1996/03/19 04:15:15 jonathan Exp $ */ -#include <mips/pmap.h> +/* + * Copyright (c) 1987 Carnegie-Mellon University + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)pmap.h 8.1 (Berkeley) 6/10/93 + */ +#ifndef _PMAP_MACHINE_ +#define _PMAP_MACHINE_ + +/* + * The user address space is 2Gb (0x0 - 0x80000000). + * User programs are laid out in memory as follows: + * address + * USRTEXT 0x00001000 + * USRDATA USRTEXT + text_size + * USRSTACK 0x7FFFFFFF + * + * The user address space is mapped using a two level structure where + * virtual address bits 30..22 are used to index into a segment table which + * points to a page worth of PTEs (4096 page can hold 1024 PTEs). + * Bits 21..12 are then used to index a PTE which describes a page within + * a segment. + * + * The wired entries in the TLB will contain the following: + * 0-1 (UPAGES) for curproc user struct and kernel stack. + * + * Note: The kernel doesn't use the same data structures as user programs. + * All the PTE entries are stored in a single array in Sysmap which is + * dynamically allocated at boot time. + */ + +#define mips_trunc_seg(x) ((vm_offset_t)(x) & ~SEGOFSET) +#define mips_round_seg(x) (((vm_offset_t)(x) + SEGOFSET) & ~SEGOFSET) +#define pmap_segmap(m, v) ((m)->pm_segtab->seg_tab[((v) >> SEGSHIFT)]) + +#define PMAP_SEGTABSIZE 512 + +union pt_entry; + +struct segtab { + union pt_entry *seg_tab[PMAP_SEGTABSIZE]; +}; + +/* + * Machine dependent pmap structure. + */ +typedef struct pmap { + int pm_count; /* pmap reference count */ + simple_lock_data_t pm_lock; /* lock on pmap */ + struct pmap_statistics pm_stats; /* pmap statistics */ + int pm_tlbpid; /* address space tag */ + u_int pm_tlbgen; /* TLB PID generation number */ + struct segtab *pm_segtab; /* pointers to pages of PTEs */ +} *pmap_t; + +/* + * Defines for pmap_attributes[phys_mach_page]; + */ +#define PMAP_ATTR_MOD 0x01 /* page has been modified */ +#define PMAP_ATTR_REF 0x02 /* page has been referenced */ + +#ifdef _KERNEL +char *pmap_attributes; /* reference and modify bits */ +struct pmap kernel_pmap_store; + +#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) +#define pmap_kernel() (&kernel_pmap_store) +#endif /* _KERNEL */ + +#endif /* _PMAP_MACHINE_ */ #define pmax_trunc_seg(a) mips_trunc_seg(a) #define pmax_round_seg(a) mips_round_seg(a) diff --git a/sys/arch/pmax/include/proc.h b/sys/arch/pmax/include/proc.h index b722ad6088b..202d9562314 100644 --- a/sys/arch/pmax/include/proc.h +++ b/sys/arch/pmax/include/proc.h @@ -1,3 +1,53 @@ -/* $NetBSD: proc.h,v 1.5 1996/03/19 03:08:08 jonathan Exp $ */ +/* $NetBSD: proc.h,v 1.4 1994/10/26 21:09:52 cgd Exp $ */ -#include <mips/proc.h> +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)proc.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * Machine-dependent part of the proc structure for DEC Station. + */ +struct mdproc { + int *md_regs; /* registers on current frame */ + int md_flags; /* machine-dependent flags */ + int md_upte[UPAGES]; /* ptes for mapping u page */ + int md_ss_addr; /* single step address for ptrace */ + int md_ss_instr; /* single step instruction for ptrace */ +}; + +/* md_flags */ +#define MDP_FPUSED 0x0001 /* floating point coprocessor used */ diff --git a/sys/arch/pmax/include/profile.h b/sys/arch/pmax/include/profile.h index 2a57a4d45c2..dc30bfdcf01 100644 --- a/sys/arch/pmax/include/profile.h +++ b/sys/arch/pmax/include/profile.h @@ -1,3 +1,79 @@ -/* $NetBSD: profile.h,v 1.7 1996/03/19 03:08:27 jonathan Exp $ */ +/* $NetBSD: profile.h,v 1.6 1995/05/31 00:25:06 jonathan Exp $ */ -#include <mips/profile.h> +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)profile.h 8.1 (Berkeley) 6/10/93 + */ + +#define _MCOUNT_DECL static void __mcount + +#define MCOUNT \ + asm(".globl _mcount;" \ + "_mcount:;" \ + ".set noreorder;" \ + ".set noat;" \ + "sw $4,8($29);" \ + "sw $5,12($29);" \ + "sw $6,16($29);" \ + "sw $7,20($29);" \ + "sw $1,0($29);" \ + "sw $31,4($29);" \ + "move $5,$31;" \ + "jal ___mcount;" \ + "move $4,$1;" \ + "lw $4,8($29);" \ + "lw $5,12($29);" \ + "lw $6,16($29);" \ + "lw $7,20($29);" \ + "lw $31,4($29);" \ + "lw $1,0($29);" \ + "addu $29,$29,8;" \ + "j $31;" \ + "move $31,$1;" \ + ".set reorder;" \ + ".set at"); + +#ifdef _KERNEL +/* + * The following two macros do splhigh and splx respectively. + * They have to be defined this way because these are real + * functions on the PMAX, and we do not want to invoke mcount + * recursively. + */ +#define MCOUNT_ENTER s = _splhigh() + +#define MCOUNT_EXIT _splx(s) +#endif /* _KERNEL */ diff --git a/sys/arch/pmax/include/ptrace.h b/sys/arch/pmax/include/ptrace.h index fbf8a1aac7d..f3ce907933e 100644 --- a/sys/arch/pmax/include/ptrace.h +++ b/sys/arch/pmax/include/ptrace.h @@ -1,3 +1,50 @@ -/* $NetBSD: ptrace.h,v 1.7 1996/03/19 04:39:01 jonathan Exp $ */ +/* $NetBSD: ptrace.h,v 1.6 1995/12/21 09:28:36 jonathan Exp $ */ -#include <mips/ptrace.h> +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ptrace.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * Mips-dependent ptrace definitions. + * + */ + +/*#define PT_STEP (PT_FIRSTMACH + 0)*/ +#define PT_GETREGS (PT_FIRSTMACH + 1) +#define PT_SETREGS (PT_FIRSTMACH + 2) + +#ifdef notyet +#define PT_GETFPREGS (PT_FIRSTMACH + 3) +#define PT_SETFPREGS (PT_FIRSTMACH + 4) +#endif diff --git a/sys/arch/pmax/include/reg.h b/sys/arch/pmax/include/reg.h index dd0ab28e08e..f91820dc359 100644 --- a/sys/arch/pmax/include/reg.h +++ b/sys/arch/pmax/include/reg.h @@ -1,3 +1,62 @@ -/* $NetBSD: reg.h,v 1.7 1996/03/19 03:08:36 jonathan Exp $ */ +/* $NetBSD: reg.h,v 1.6 1995/12/20 02:00:27 jonathan Exp $ */ -#include <mips/reg.h> +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah Hdr: reg.h 1.1 90/07/09 + * + * @(#)reg.h 8.2 (Berkeley) 1/11/94 + */ + +#ifndef _MACHINE_REG_H_ +#define _MACHINE_REG_H_ +/* + * Location of the users' stored + * registers relative to ZERO. + * Usage is p->p_regs[XX]. + * + * must be visible to assembly code. + */ +#include <machine/regnum.h> + +/* + * Register set accessible via /proc/$pid/reg + */ +struct reg { + int r_regs[71]; /* numbered as above */ +}; +#endif /*_MACHINE_REG_H_*/ diff --git a/sys/arch/pmax/include/regdef.h b/sys/arch/pmax/include/regdef.h index 848ddfab9d6..46216b57d00 100644 --- a/sys/arch/pmax/include/regdef.h +++ b/sys/arch/pmax/include/regdef.h @@ -1,3 +1,73 @@ -/* $NetBSD: regdef.h,v 1.5 1996/03/19 03:08:41 jonathan Exp $ */ +/* $NetBSD: regdef.h,v 1.4 1994/10/26 21:09:58 cgd Exp $ */ -#include <mips/regdef.h> +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. This file is derived from the MIPS RISC + * Architecture book by Gerry Kane. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)regdef.h 8.1 (Berkeley) 6/10/93 + */ + +#define zero $0 /* always zero */ +#define AT $at /* assembler temp */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* temp registers (not saved across subroutine calls) */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* saved across subroutine calls (callee saved) */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* two more temp registers */ +#define t9 $25 +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define s8 $30 /* one more callee saved */ +#define ra $31 /* return address */ diff --git a/sys/arch/pmax/include/regnum.h b/sys/arch/pmax/include/regnum.h index f62b9ce04e5..d93043fe883 100644 --- a/sys/arch/pmax/include/regnum.h +++ b/sys/arch/pmax/include/regnum.h @@ -1,3 +1,136 @@ -/* $NetBSD: regnum.h,v 1.3 1996/03/20 09:49:30 jonathan Exp $ */ +/* $NetBSD: regnum.h,v 1.2 1996/03/19 15:20:39 jonathan Exp $ */ -#include <mips/regnum.h> +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah Hdr: reg.h 1.1 90/07/09 + * + * @(#)reg.h 8.2 (Berkeley) 1/11/94 + */ + +/* + * Location of the users' stored + * registers relative to ZERO. + * Usage is p->p_regs[XX]. + */ +#define ZERO 0 +#define AST 1 +#define V0 2 +#define V1 3 +#define A0 4 +#define A1 5 +#define A2 6 +#define A3 7 +#define T0 8 +#define T1 9 +#define T2 10 +#define T3 11 +#define T4 12 +#define T5 13 +#define T6 14 +#define T7 15 +#define S0 16 +#define S1 17 +#define S2 18 +#define S3 19 +#define S4 20 +#define S5 21 +#define S6 22 +#define S7 23 +#define T8 24 +#define T9 25 +#define K0 26 +#define K1 27 +#define GP 28 +#define SP 29 +#define S8 30 +#define RA 31 +#define SR 32 +#define PS SR /* alias for SR */ +#define MULLO 33 +#define MULHI 34 +#define BADVADDR 35 +#define CAUSE 36 +#define PC 37 + +#define FPBASE 38 +#define F0 (FPBASE+0) +#define F1 (FPBASE+1) +#define F2 (FPBASE+2) +#define F3 (FPBASE+3) +#define F4 (FPBASE+4) +#define F5 (FPBASE+5) +#define F6 (FPBASE+6) +#define F7 (FPBASE+7) +#define F8 (FPBASE+8) +#define F9 (FPBASE+9) +#define F10 (FPBASE+10) +#define F11 (FPBASE+11) +#define F12 (FPBASE+12) +#define F13 (FPBASE+13) +#define F14 (FPBASE+14) +#define F15 (FPBASE+15) +#define F16 (FPBASE+16) +#define F17 (FPBASE+17) +#define F18 (FPBASE+18) +#define F19 (FPBASE+19) +#define F20 (FPBASE+20) +#define F21 (FPBASE+21) +#define F22 (FPBASE+22) +#define F23 (FPBASE+23) +#define F24 (FPBASE+24) +#define F25 (FPBASE+25) +#define F26 (FPBASE+26) +#define F27 (FPBASE+27) +#define F28 (FPBASE+28) +#define F29 (FPBASE+29) +#define F30 (FPBASE+30) +#define F31 (FPBASE+31) +#define FSR (FPBASE+32) + +#ifdef IPCREG +#define NIPCREG (FSR + 1) +int ipcreg[NIPCREG] = { + ZERO, AST, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, + S0, S1, S2, S3, S4, S5, S6, S7, T8, T9, K0, K1, GP, SP, S8, RA, + SR, MULLO, MULHI, BADVADDR, CAUSE, PC, + F0, F1, F2, F3, F4, F5, F6, F7, + F8, F9, F10, F11, F12, F13, F14, F15, + F16, F17, F18, F19, F20, F21, F22, F23, + F24, F25, F26, F27, F28, F29, F30, F31, FSR, +}; +#endif diff --git a/sys/arch/pmax/include/reloc.h b/sys/arch/pmax/include/reloc.h index a352fe1ec87..1a91b52c46b 100644 --- a/sys/arch/pmax/include/reloc.h +++ b/sys/arch/pmax/include/reloc.h @@ -1,5 +1,75 @@ -/* $NetBSD: reloc.h,v 1.6 1996/03/20 09:49:29 jonathan Exp $ */ +/* $NetBSD: reloc.h,v 1.5 1996/03/19 22:18:45 jonathan Exp $ */ -#include <mips/reloc.h> +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)reloc.h 8.1 (Berkeley) 6/10/93 + * + * from: Header: reloc.h,v 1.6 92/06/20 09:59:37 torek Exp + */ +/* + * MIPS relocation types. + */ +enum reloc_type { + MIPS_RELOC_32, /* 32-bit absolute */ + MIPS_RELOC_JMP, /* 26-bit absolute << 2 | high 4 bits of pc */ + MIPS_RELOC_WDISP16, /* 16-bit signed pc-relative << 2 */ + MIPS_RELOC_HI16, /* 16-bit absolute << 16 */ + MIPS_RELOC_HI16_S, /* 16-bit absolute << 16 (+1 if needed) */ + MIPS_RELOC_LO16, /* 16-bit absolute */ +}; + +/* + * MIPS relocation info. + * + * Symbol-relative relocation is done by: + * 1. start with the value r_addend, + * 2. locate the appropriate symbol and if defined, add symbol value, + * 3. if pc relative, subtract pc, + * 4. if the reloc_type is MIPS_RELOC_HI16_S and the result bit 15 is set, + * add 0x00010000, + * 5. shift down 2 or 16 if necessary. + * The resulting value is then to be stuffed into the appropriate bits + * in the object (the low 16, or the low 26 bits). + */ +struct reloc_info_mips { + u_long r_address; /* relocation addr (offset in segment) */ + u_int r_index:24, /* segment (r_extern==0) or symbol index */ + r_extern:1, /* if set, r_index is symbol index */ + :2; /* unused */ + enum reloc_type r_type:5; /* relocation type, from above */ + long r_addend; /* value to add to symbol value */ +}; + +#define relocation_info reloc_info_mips #define relocation_info_pmax reloc_info_mips diff --git a/sys/arch/pmax/include/setjmp.h b/sys/arch/pmax/include/setjmp.h index bcfa694662a..c50d15c79b5 100644 --- a/sys/arch/pmax/include/setjmp.h +++ b/sys/arch/pmax/include/setjmp.h @@ -1,3 +1,7 @@ -/* $NetBSD: setjmp.h,v 1.2 1996/03/19 03:08:46 jonathan Exp $ */ +/* $NetBSD: setjmp.h,v 1.1 1994/12/20 10:37:05 cgd Exp $ */ -#include <mips/setjmp.h> +/* + * machine/setjmp.h: machine dependent setjmp-related information. + */ + +#define _JBLEN 83 /* size, in longs, of a jmp_buf */ diff --git a/sys/arch/pmax/include/signal.h b/sys/arch/pmax/include/signal.h index 350de4fbf11..b17ab5b9c54 100644 --- a/sys/arch/pmax/include/signal.h +++ b/sys/arch/pmax/include/signal.h @@ -1,3 +1,67 @@ -/* $NetBSD: signal.h,v 1.8 1996/03/19 04:39:07 jonathan Exp $ */ +/* $NetBSD: signal.h,v 1.7 1996/03/19 04:22:04 jonathan Exp $ */ -#include <mips/signal.h> +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)signal.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * Machine-dependent signal definitions + */ + +typedef int sig_atomic_t; + +#ifndef _ANSI_SOURCE +/* + * Information pushed on stack when a signal is delivered. + * This is used by the kernel to restore state following + * execution of the signal handler. It is also made available + * to the handler to allow it to restore state properly if + * a non-standard exit is performed. + */ +struct sigcontext { + int sc_onstack; /* sigstack state to restore */ + int sc_mask; /* signal mask to restore */ + int sc_pc; /* pc at time of signal */ + int sc_regs[32]; /* processor regs 0 to 31 */ + int mullo, mulhi; /* mullo and mulhi registers... */ + int sc_fpused; /* fp has been used */ + int sc_fpregs[33]; /* fp regs 0 to 31 and csr */ + int sc_fpc_eir; /* floating point exception instruction reg */ + int sc_xxx[8]; /* XXX reserved */ +}; + +#endif /* !_ANSI_SOURCE */ diff --git a/sys/arch/pmax/include/stdarg.h b/sys/arch/pmax/include/stdarg.h index 2bb98006638..1049e7ba9ec 100644 --- a/sys/arch/pmax/include/stdarg.h +++ b/sys/arch/pmax/include/stdarg.h @@ -1,3 +1,64 @@ -/* $NetBSD: stdarg.h,v 1.12 1996/03/19 03:08:51 jonathan Exp $ */ +/* $NetBSD: stdarg.h,v 1.11 1996/02/26 23:29:08 jonathan Exp $ */ -#include <mips/stdarg.h> +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdarg.h 8.1 (Berkeley) 6/10/93 + */ + +#ifndef _PMAX_STDARG_H_ +#define _PMAX_STDARG_H_ + +#include <machine/ansi.h> + +typedef _BSD_VA_LIST_ va_list; + +#define __va_promote(type) \ + (((sizeof(type) + sizeof(int) - 1) / sizeof(int)) * sizeof(int)) + +#define va_start(ap, last) \ + (ap = ((char *)&(last) + __va_promote(last))) + +#ifdef _KERNEL +#define va_arg(ap, type) \ + ((type *)(ap += sizeof(type)))[-1] +#else +#define va_arg(ap, type) \ + ((type *)(ap += sizeof(type) == sizeof(int) ? sizeof(type) : \ + sizeof(type) > sizeof(int) ? \ + (-(int)(ap) & (sizeof(type) - 1)) + sizeof(type) : \ + (abort(), 0)))[-1] +#endif + +#define va_end(ap) ((void) 0) + +#endif /* !_PMAX_STDARG_H_ */ diff --git a/sys/arch/pmax/include/tc_machdep.h b/sys/arch/pmax/include/tc_machdep.h index 44e620ea4a2..1d41e5d8e03 100644 --- a/sys/arch/pmax/include/tc_machdep.h +++ b/sys/arch/pmax/include/tc_machdep.h @@ -60,7 +60,7 @@ #ifndef __MACHINE_TC_MACHDEP_H__ #define __MACHINE_TC_MACHDEP_H__ -#include <mips/cpuregs.h> /* defines MACH_PHYS_TO_UNCACHED */ +#include <pmax/cpuregs.h> /* defines MACH_PHYS_TO_UNCACHED */ typedef int32_t tc_addr_t; typedef int32_t tc_offset_t; diff --git a/sys/arch/pmax/include/trap.h b/sys/arch/pmax/include/trap.h index 0ae8075953b..56deedb7b41 100644 --- a/sys/arch/pmax/include/trap.h +++ b/sys/arch/pmax/include/trap.h @@ -1,3 +1,73 @@ -/* $NetBSD: trap.h,v 1.7 1996/03/24 08:17:06 jonathan Exp $ */ +/* $NetBSD: trap.h,v 1.6 1996/03/24 08:12:53 jonathan Exp $ */ -#include <mips/trap.h> +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah Hdr: trap.h 1.1 90/07/09 + * + * @(#)trap.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * Trap codes + * also known in trap.c for name strings + */ + +#define T_INT 0 /* Interrupt pending */ +#define T_TLB_MOD 1 /* TLB modified fault */ +#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */ +#define T_TLB_ST_MISS 3 /* TLB miss on a store */ +#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */ +#define T_ADDR_ERR_ST 5 /* Address error on a store */ +#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */ +#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */ +#define T_SYSCALL 8 /* System call */ +#define T_BREAK 9 /* Breakpoint */ +#define T_RES_INST 10 /* Reserved instruction exception */ +#define T_COP_UNUSABLE 11 /* Coprocessor unusable */ +#define T_OVFLOW 12 /* Arithmetic overflow */ + +/* + * Trap definitions added for r4000 port. + */ +#define T_TRAP 13 /* Trap instruction */ +#define T_VCEI 14 /* Virtual coherency instruction */ +#define T_FPE 15 /* Floating point exception */ +#define T_WATCH 23 /* Watch address reference */ +#define T_VCED 31 /* Virtual coherency data */ + +#define T_USER 0x20 /* user-mode flag or'ed with type */ diff --git a/sys/arch/pmax/include/types.h b/sys/arch/pmax/include/types.h index f35e61528d2..cab9865caa3 100644 --- a/sys/arch/pmax/include/types.h +++ b/sys/arch/pmax/include/types.h @@ -1,3 +1,78 @@ -/* $NetBSD: types.h,v 1.12 1996/03/19 05:18:26 jonathan Exp $ */ +/* $NetBSD: types.h,v 1.12 1996/04/09 20:54:08 jonathan Exp $ */ -#include <mips/types.h> +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)types.h 8.3 (Berkeley) 1/5/94 + */ + +#ifndef _MACHTYPES_H_ +#define _MACHTYPES_H_ + +#include <sys/cdefs.h> + +#if !defined(_ANSI_SOURCE) && !defined(_POSIX_SOURCE) +typedef struct _physadr { + int r[1]; +} *physadr; + +typedef struct label_t { + int val[12]; +} label_t; +#endif + +typedef unsigned long vm_offset_t; +typedef unsigned long vm_size_t; + +/* + * Basic integral types. Omit the typedef if + * not possible for a machine/compiler combination. + */ +#define __BIT_TYPES_DEFINED__ +typedef __signed char int8_t; +typedef unsigned char u_int8_t; +typedef short int16_t; +typedef unsigned short u_int16_t; +typedef int int32_t; +typedef unsigned int u_int32_t; +typedef long long int64_t; +typedef unsigned long long u_int64_t; + +typedef int32_t register_t; + +#define __SWAP_BROKEN +#define __FORK_BRAINDAMAGE + +#endif /* _MACHTYPES_H_ */ diff --git a/sys/arch/pmax/include/varargs.h b/sys/arch/pmax/include/varargs.h index f5427bc90c1..d34b69f1967 100644 --- a/sys/arch/pmax/include/varargs.h +++ b/sys/arch/pmax/include/varargs.h @@ -1,3 +1,68 @@ -/* $NetBSD: varargs.h,v 1.14 1996/03/20 09:49:31 jonathan Exp $ */ +/* $NetBSD: varargs.h,v 1.13 1996/02/26 23:29:05 jonathan Exp $ */ -#include <mips/varargs.h> +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)varargs.h 8.2 (Berkeley) 3/22/94 + */ + +#ifndef _PMAX_VARARGS_H_ +#define _PMAX_VARARGS_H_ + +#include <machine/ansi.h> + +typedef _BSD_VA_LIST_ va_list; + +#define va_dcl int va_alist; + +#define va_start(ap) \ + ap = (char *)&va_alist + +#ifdef _KERNEL +#define va_arg(ap, type) \ + ((type *)(ap += sizeof(type)))[-1] +#else +#define va_arg(ap, type) \ + ((type *)(ap += sizeof(type) == sizeof(int) ? sizeof(type) : \ + sizeof(type) > sizeof(int) ? \ + (-(int)(ap) & (sizeof(type) - 1)) + sizeof(type) : \ + (abort(), 0)))[-1] +#endif + +#define va_end(ap) ((void) 0) + +#endif /* !_PMAX_VARARGS_H_ */ diff --git a/sys/arch/pmax/include/vmparam.h b/sys/arch/pmax/include/vmparam.h index aa4e5cbc9f1..6215614fcf1 100644 --- a/sys/arch/pmax/include/vmparam.h +++ b/sys/arch/pmax/include/vmparam.h @@ -1,6 +1,241 @@ -/* $NetBSD: vmparam.h,v 1.6 1996/03/19 03:08:56 jonathan Exp $ */ +/* $NetBSD: vmparam.h,v 1.5 1994/10/26 21:10:10 cgd Exp $ */ -#include <mips/vmparam.h> +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah Hdr: vmparam.h 1.16 91/01/18 + * + * @(#)vmparam.h 8.2 (Berkeley) 4/22/94 + */ + +/* + * Machine dependent constants for DEC Station 3100. + */ +/* + * USRTEXT is the start of the user text/data space, while USRSTACK + * is the top (end) of the user stack. LOWPAGES and HIGHPAGES are + * the number of pages from the beginning of the P0 region to the + * beginning of the text and from the beginning of the P1 region to the + * beginning of the stack respectively. + */ +#define USRTEXT 0x00001000 +#define USRSTACK 0x80000000 /* Start of user stack */ +#define BTOPUSRSTACK 0x80000 /* btop(USRSTACK) */ +#define LOWPAGES 0x00001 +#define HIGHPAGES 0 + +/* + * Virtual memory related constants, all in bytes + */ +#ifndef MAXTSIZ +#define MAXTSIZ (24*1024*1024) /* max text size */ +#endif +#ifndef DFLDSIZ +#define DFLDSIZ (32*1024*1024) /* initial data size limit */ +#endif +#ifndef MAXDSIZ +#define MAXDSIZ (32*1024*1024) /* max data size */ +#endif +#ifndef DFLSSIZ +#define DFLSSIZ (1024*1024) /* initial stack size limit */ +#endif +#ifndef MAXSSIZ +#define MAXSSIZ MAXDSIZ /* max stack size */ +#endif + +/* + * Default sizes of swap allocation chunks (see dmap.h). + * The actual values may be changed in vminit() based on MAXDSIZ. + * With MAXDSIZ of 16Mb and NDMAP of 38, dmmax will be 1024. + * DMMIN should be at least ctod(1) so that vtod() works. + * vminit() insures this. + */ +#define DMMIN 32 /* smallest swap allocation */ +#define DMMAX 4096 /* largest potential swap allocation */ + +/* + * Sizes of the system and user portions of the system page table. + */ +/* SYSPTSIZE IS SILLY; (really number of buffers for I/O) */ +#define SYSPTSIZE 1228 +#define USRPTSIZE 1024 + +/* + * PTEs for mapping user space into the kernel for phyio operations. + * 16 pte's are enough to cover 8 disks * MAXBSIZE. + */ +#ifndef USRIOSIZE +#define USRIOSIZE 32 +#endif + +/* + * PTEs for system V style shared memory. + * This is basically slop for kmempt which we actually allocate (malloc) from. + */ +#ifndef SHMMAXPGS +#define SHMMAXPGS 1024 /* 4mb */ +#endif + +/* + * Boundary at which to place first MAPMEM segment if not explicitly + * specified. Should be a power of two. This allows some slop for + * the data segment to grow underneath the first mapped segment. + */ +#define MMSEG 0x200000 + +/* + * The size of the clock loop. + */ +#define LOOPPAGES (maxfree - firstfree) + +/* + * The time for a process to be blocked before being very swappable. + * This is a number of seconds which the system takes as being a non-trivial + * amount of real time. You probably shouldn't change this; + * it is used in subtle ways (fractions and multiples of it are, that is, like + * half of a ``long time'', almost a long time, etc.) + * It is related to human patience and other factors which don't really + * change over time. + */ +#define MAXSLP 20 + +/* + * A swapped in process is given a small amount of core without being bothered + * by the page replacement algorithm. Basically this says that if you are + * swapped in you deserve some resources. We protect the last SAFERSS + * pages against paging and will just swap you out rather than paging you. + * Note that each process has at least UPAGES+CLSIZE pages which are not + * paged anyways (this is currently 8+2=10 pages or 5k bytes), so this + * number just means a swapped in process is given around 25k bytes. + * Just for fun: current memory prices are 4600$ a megabyte on VAX (4/22/81), + * so we loan each swapped in process memory worth 100$, or just admit + * that we don't consider it worthwhile and swap it out to disk which costs + * $30/mb or about $0.75. + */ +#define SAFERSS 4 /* nominal ``small'' resident set size + protected against replacement */ + +/* + * DISKRPM is used to estimate the number of paging i/o operations + * which one can expect from a single disk controller. + */ +#define DISKRPM 60 + +/* + * Klustering constants. Klustering is the gathering + * of pages together for pagein/pageout, while clustering + * is the treatment of hardware page size as though it were + * larger than it really is. + * + * KLMAX gives maximum cluster size in CLSIZE page (cluster-page) + * units. Note that ctod(KLMAX*CLSIZE) must be <= DMMIN in dmap.h. + * ctob(KLMAX) should also be less than MAXPHYS (in vm_swp.c) + * unless you like "big push" panics. + */ + +#ifdef notdef /* XXX */ +#define KLMAX (4/CLSIZE) +#define KLSEQL (2/CLSIZE) /* in klust if vadvise(VA_SEQL) */ +#define KLIN (4/CLSIZE) /* default data/stack in klust */ +#define KLTXT (4/CLSIZE) /* default text in klust */ +#define KLOUT (4/CLSIZE) +#else +#define KLMAX (1/CLSIZE) +#define KLSEQL (1/CLSIZE) +#define KLIN (1/CLSIZE) +#define KLTXT (1/CLSIZE) +#define KLOUT (1/CLSIZE) +#endif + +/* + * KLSDIST is the advance or retard of the fifo reclaim for sequential + * processes data space. + */ +#define KLSDIST 3 /* klusters advance/retard for seq. fifo */ + +/* + * Paging thresholds (see vm_sched.c). + * Strategy of 1/19/85: + * lotsfree is 512k bytes, but at most 1/4 of memory + * desfree is 200k bytes, but at most 1/8 of memory + */ +#define LOTSFREE (512 * 1024) +#define LOTSFREEFRACT 4 +#define DESFREE (200 * 1024) +#define DESFREEFRACT 8 + +/* + * There are two clock hands, initially separated by HANDSPREAD bytes + * (but at most all of user memory). The amount of time to reclaim + * a page once the pageout process examines it increases with this + * distance and decreases as the scan rate rises. + */ +#define HANDSPREAD (2 * 1024 * 1024) + +/* + * The number of times per second to recompute the desired paging rate + * and poke the pagedaemon. + */ +#define RATETOSCHEDPAGING 4 + +/* + * Believed threshold (in megabytes) for which interleaved + * swapping area is desirable. + */ +#define LOTSOFMEM 2 + +#define mapin(pte, v, pfnum, prot) \ + (*(int *)(pte) = ((pfnum) << PG_SHIFT) | (prot), MachTLBFlushAddr(v)) + +/* + * Mach derived constants + */ + +/* user/kernel map constants */ +#define VM_MIN_ADDRESS ((vm_offset_t)0x00000000) +#define VM_MAXUSER_ADDRESS ((vm_offset_t)0x80000000) +#define VM_MAX_ADDRESS ((vm_offset_t)0x80000000) +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xC0000000) +#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)0xFFFFC000) + +/* virtual sizes (bytes) for various kernel submaps */ +#define VM_MBUF_SIZE (NMBCLUSTERS*MCLBYTES) +#define VM_KMEM_SIZE (NKMEMCLUSTERS*CLBYTES) +#define VM_PHYS_SIZE (USRIOSIZE*CLBYTES) /* pcb base */ -/*#define pcbb(p) ((u_int)(p)->p_addr) */ +#define pcbb(p) ((u_int)(p)->p_addr) diff --git a/sys/arch/pmax/pmax/cpu_exec.c b/sys/arch/pmax/pmax/cpu_exec.c new file mode 100644 index 00000000000..4e3e657011a --- /dev/null +++ b/sys/arch/pmax/pmax/cpu_exec.c @@ -0,0 +1,104 @@ +/* $NetBSD: cpu_exec.c,v 1.4 1995/04/25 19:16:46 mellon Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by Ralph + * Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)machdep.c 8.3 (Berkeley) 1/12/94 + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/proc.h> +#include <sys/malloc.h> +#include <sys/vnode.h> +#include <sys/exec.h> +#include <sys/resourcevar.h> +#include <vm/vm.h> + +#include <sys/exec_ecoff.h> +#include <machine/reg.h> + +/* + * cpu_exec_aout_makecmds(): + * cpu-dependent a.out format hook for execve(). + * + * Determine of the given exec package refers to something which we + * understand and, if so, set up the vmcmds for it. + * + */ +int +cpu_exec_aout_makecmds(p, epp) + struct proc *p; + struct exec_package *epp; +{ + return ENOEXEC; +} + +#ifdef COMPAT_ULTRIX +extern struct emul emul_ultrix; + +void +cpu_exec_ecoff_setregs(p, pack, stack, retval) + struct proc *p; + struct exec_package *pack; + u_long stack; + register_t *retval; +{ + struct ecoff_aouthdr *eap; + + setregs(p, pack, stack, retval); + eap = (struct ecoff_aouthdr *) + ((caddr_t)pack->ep_hdr + sizeof(struct ecoff_filehdr)); + p->p_md.md_regs[GP] = eap->ea_gp_value; +} + +/* + * cpu_exec_ecoff_hook(): + * cpu-dependent ECOFF format hook for execve(). + * + * Do any machine-dependent diddling of the exec package when doing ECOFF. + * + */ +int +cpu_exec_ecoff_hook(p, epp, eap) + struct proc *p; + struct exec_package *epp; + struct ecoff_aouthdr *eap; +{ + + epp->ep_emul = &emul_ultrix; + return 0; +} +#endif diff --git a/sys/arch/pmax/pmax/genassym.c b/sys/arch/pmax/pmax/genassym.c new file mode 100644 index 00000000000..ef560a58aed --- /dev/null +++ b/sys/arch/pmax/pmax/genassym.c @@ -0,0 +1,81 @@ +/* $NetBSD: genassym.c,v 1.9 1996/04/07 14:27:00 jonathan Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)genassym.c 8.2 (Berkeley) 9/23/93 + */ + +#include <stdio.h> +#include <stddef.h> +#include <sys/param.h> +#include <sys/buf.h> +#include <sys/map.h> +#include <sys/proc.h> +#include <sys/mbuf.h> +#include <sys/user.h> + +#include <machine/reg.h> + +#define def(N,V) printf("#define\t%s %d\n", N, V) +#define defx(N,V) printf("#define\t%s 0x%lx\n", N, V) +#define off(N,S,M) def(N, (int)offsetof(S, M)) + +int +main() +{ + + off("P_FORW", struct proc, p_forw); + off("P_BACK", struct proc, p_back); + off("P_PRIORITY", struct proc, p_priority); + off("P_ADDR", struct proc, p_addr); + + off("P_UPTE", struct proc, p_md.md_upte); + off("U_PCB_REGS", struct user, u_pcb.pcb_regs); + + off("U_PCB_FPREGS", struct user, u_pcb.pcb_regs[F0]); + off("U_PCB_CONTEXT", struct user, u_pcb.pcb_context); + off("U_PCB_ONFAULT", struct user, u_pcb.pcb_onfault); + off("U_PCB_SEGTAB", struct user, u_pcb.pcb_segtab); + + defx("VM_MIN_ADDRESS", VM_MIN_ADDRESS); + defx("VM_MIN_KERNEL_ADDRESS", VM_MIN_KERNEL_ADDRESS); + + off("V_SWTCH", struct vmmeter, v_swtch); + + def("SIGILL", SIGILL); + def("SIGFPE", SIGFPE); + exit(0); +} diff --git a/sys/arch/pmax/pmax/locore_r2000.S b/sys/arch/pmax/pmax/locore_r2000.S new file mode 100644 index 00000000000..75edd70ad45 --- /dev/null +++ b/sys/arch/pmax/pmax/locore_r2000.S @@ -0,0 +1,1343 @@ + +/* + *---------------------------------------------------------------------------- + * + * mips_r2000_UTLBmiss -- + * MachUTLBmiss -- + * + * Vector code for a MIPS-I user-space TLB miss from user-space. + * + * + * This code is copied to the UTLB exception vector address to + * handle user level TLB translation misses. + * NOTE: This code must be relocatable!!! + */ + .globl _C_LABEL(mips_R2000_UTLBMiss) +_C_LABEL(mips_R2000_UTLBMiss): + .globl _C_LABEL(MachUTLBMiss) +_C_LABEL(MachUTLBMiss): + .set noat + mfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address + lw k1, UADDR+U_PCB_SEGTAB # get the current segment table + bltz k0, 1f # R3000 chip bug + srl k0, k0, SEGSHIFT # compute segment table index + sll k0, k0, 2 + addu k1, k1, k0 + mfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address + lw k1, 0(k1) # get pointer to segment map + srl k0, k0, PGSHIFT - 2 # compute segment map index + andi k0, k0, (NPTEPG - 1) << 2 + beq k1, zero, 2f # invalid segment map + addu k1, k1, k0 # index into segment map + lw k0, 0(k1) # get page PTE + nop + beq k0, zero, 2f # dont load invalid entries + mtc0 k0, MACH_COP_0_TLB_LOW + mfc0 k1, MACH_COP_0_EXC_PC # get return address + tlbwr # update TLB + j k1 + rfe +1: + mfc0 k1, MACH_COP_0_EXC_PC # get return address + nop + j k1 + rfe +2: + j mips_r2000_SlowFault # handle the rest + nop + .set at + .globl _C_LABEL(MachUTLBMissEnd) +_C_LABEL(MachUTLBMissEnd): + + .globl _C_LABEL(mips_R2000_UTLBMissEnd) +_C_LABEL(mips_R2000_UTLBMissEnd): + + +/* + *---------------------------------------------------------------------------- + * + * mips_R2000_execption -- + * + * Vector code for the general exception vector 0x80000080 + * on an r2000 or r3000. + * + * This code is copied to the general exception vector address to + * handle all execptions except RESET and UTLBMiss. + * NOTE: This code must be relocatable!!! + * + *---------------------------------------------------------------------------- + */ + .globl _C_LABEL(mips_R2000_exception) +_C_LABEL(mips_R2000_exception): +/* + * Find out what mode we came from and jump to the proper handler. + */ + .set noat + mfc0 k0, MACH_COP_0_STATUS_REG # Get the status register + mfc0 k1, MACH_COP_0_CAUSE_REG # Get the cause register value. + and k0, k0, MIPS_3K_SR_KU_PREV # test for user mode + sll k0, k0, 4 # shift user bit for cause index + and k1, k1, MIPS_3K_CR_EXC_CODE # Mask out the cause bits. + or k1, k1, k0 # change index to user table +1: + la k0, _C_LABEL(mips_r2000_ExceptionTable) # get base of the jump table + addu k0, k0, k1 # Get the address of the + # function entry. Note that + # the cause is already + # shifted left by 2 bits so + # we dont have to shift. + lw k0, 0(k0) # Get the function address + nop + j k0 # Jump to the function. + nop + .set at + .globl _C_LABEL(mips_R2000_exceptionEnd) +_C_LABEL(mips_R2000_exceptionEnd): + + + + +/*---------------------------------------------------------------------------- + * + * mips_r2000_SlowFault -- + * + * Alternate entry point into the mips_r2000_UserGenExceptionor or + * or mips_r2000_user_Kern_exception, when the ULTB miss handler couldn't + * find a TLB entry. + * + * Find out what mode we came from and call the appropriate handler. + */ +mips_r2000_SlowFault: + .set noat + mfc0 k0, MACH_COP_0_STATUS_REG + nop + and k0, k0, MACH_SR_KU_PREV + bne k0, zero, _C_LABEL(mips_r2000_UserGenException) + nop + .set at +/* + * Fall though ... + */ + +/*---------------------------------------------------------------------------- + * + * mips_r2000_KernGenException -- + * + * Handle an exception from kernel mode. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ + +/* + * The kernel exception stack contains 18 saved general registers, + * the status register and the multiply lo and high registers. + * In addition, we set this up for linkage conventions. + */ +#define KERN_REG_SIZE (18 * 4) +#define KERN_REG_OFFSET (STAND_FRAME_SIZE) +#define KERN_SR_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE) +#define KERN_MULT_LO_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 4) +#define KERN_MULT_HI_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 8) +#define KERN_EXC_FRAME_SIZE (STAND_FRAME_SIZE + KERN_REG_SIZE + 12) + +NNON_LEAF(mips_r2000_KernGenException, KERN_EXC_FRAME_SIZE, ra) + .set noat +#ifdef KADB + la k0, kdbpcb # save registers for kadb + sw s0, (S0 * 4)(k0) + sw s1, (S1 * 4)(k0) + sw s2, (S2 * 4)(k0) + sw s3, (S3 * 4)(k0) + sw s4, (S4 * 4)(k0) + sw s5, (S5 * 4)(k0) + sw s6, (S6 * 4)(k0) + sw s7, (S7 * 4)(k0) + sw s8, (S8 * 4)(k0) + sw gp, (GP * 4)(k0) + sw sp, (SP * 4)(k0) +#endif + subu sp, sp, KERN_EXC_FRAME_SIZE + .mask 0x80000000, (STAND_RA_OFFSET - KERN_EXC_FRAME_SIZE) +/* + * Save the relevant kernel registers onto the stack. + * We don't need to save s0 - s8, sp and gp because + * the compiler does it for us. + */ + sw AT, KERN_REG_OFFSET + 0(sp) + sw v0, KERN_REG_OFFSET + 4(sp) + sw v1, KERN_REG_OFFSET + 8(sp) + sw a0, KERN_REG_OFFSET + 12(sp) + mflo v0 + mfhi v1 + sw a1, KERN_REG_OFFSET + 16(sp) + sw a2, KERN_REG_OFFSET + 20(sp) + sw a3, KERN_REG_OFFSET + 24(sp) + sw t0, KERN_REG_OFFSET + 28(sp) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t1, KERN_REG_OFFSET + 32(sp) + sw t2, KERN_REG_OFFSET + 36(sp) + sw t3, KERN_REG_OFFSET + 40(sp) + sw t4, KERN_REG_OFFSET + 44(sp) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw t5, KERN_REG_OFFSET + 48(sp) + sw t6, KERN_REG_OFFSET + 52(sp) + sw t7, KERN_REG_OFFSET + 56(sp) + sw t8, KERN_REG_OFFSET + 60(sp) + mfc0 a2, MACH_COP_0_BAD_VADDR # Third arg is the fault addr. + sw t9, KERN_REG_OFFSET + 64(sp) + sw ra, KERN_REG_OFFSET + 68(sp) + sw v0, KERN_MULT_LO_OFFSET(sp) + sw v1, KERN_MULT_HI_OFFSET(sp) + mfc0 a3, MACH_COP_0_EXC_PC # Fourth arg is the pc. + sw a0, KERN_SR_OFFSET(sp) +/* + * Call the exception handler. + */ + jal _C_LABEL(trap) + sw a3, STAND_RA_OFFSET(sp) # for debugging +/* + * Restore registers and return from the exception. + * v0 contains the return address. + */ + lw a0, KERN_SR_OFFSET(sp) + lw t0, KERN_MULT_LO_OFFSET(sp) + lw t1, KERN_MULT_HI_OFFSET(sp) + mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtlo t0 + mthi t1 + move k0, v0 + + lw AT, KERN_REG_OFFSET + 0(sp) + lw v0, KERN_REG_OFFSET + 4(sp) + + RESTORE_KERN_REGISTERS(KERN_REG_OFFSET) + + addu sp, sp, KERN_EXC_FRAME_SIZE + j k0 # Now return from the + rfe # exception. + .set at +END(mips_r2000_KernGenException) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_UserGenException -- + * + * Handle an exception from user mode. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NNON_LEAF(mips_r2000_UserGenException, STAND_FRAME_SIZE, ra) + .set noat + .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) +/* + * Save all of the registers except for the kernel temporaries in u.u_pcb. + */ + sw AT, UADDR+U_PCB_REGS+(AST * 4) + sw v0, UADDR+U_PCB_REGS+(V0 * 4) + sw v1, UADDR+U_PCB_REGS+(V1 * 4) + sw a0, UADDR+U_PCB_REGS+(A0 * 4) + mflo v0 + sw a1, UADDR+U_PCB_REGS+(A1 * 4) + sw a2, UADDR+U_PCB_REGS+(A2 * 4) + sw a3, UADDR+U_PCB_REGS+(A3 * 4) + sw t0, UADDR+U_PCB_REGS+(T0 * 4) + mfhi v1 + sw t1, UADDR+U_PCB_REGS+(T1 * 4) + sw t2, UADDR+U_PCB_REGS+(T2 * 4) + sw t3, UADDR+U_PCB_REGS+(T3 * 4) + sw t4, UADDR+U_PCB_REGS+(T4 * 4) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t5, UADDR+U_PCB_REGS+(T5 * 4) + sw t6, UADDR+U_PCB_REGS+(T6 * 4) + sw t7, UADDR+U_PCB_REGS+(T7 * 4) + sw s0, UADDR+U_PCB_REGS+(S0 * 4) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw s1, UADDR+U_PCB_REGS+(S1 * 4) + sw s2, UADDR+U_PCB_REGS+(S2 * 4) + sw s3, UADDR+U_PCB_REGS+(S3 * 4) + sw s4, UADDR+U_PCB_REGS+(S4 * 4) + mfc0 a2, MACH_COP_0_BAD_VADDR # Third arg is the fault addr + sw s5, UADDR+U_PCB_REGS+(S5 * 4) + sw s6, UADDR+U_PCB_REGS+(S6 * 4) + sw s7, UADDR+U_PCB_REGS+(S7 * 4) + sw t8, UADDR+U_PCB_REGS+(T8 * 4) + mfc0 a3, MACH_COP_0_EXC_PC # Fourth arg is the pc. + sw t9, UADDR+U_PCB_REGS+(T9 * 4) + sw gp, UADDR+U_PCB_REGS+(GP * 4) + sw sp, UADDR+U_PCB_REGS+(SP * 4) + sw s8, UADDR+U_PCB_REGS+(S8 * 4) + li sp, KERNELSTACK - STAND_FRAME_SIZE # switch to kernel SP + sw ra, UADDR+U_PCB_REGS+(RA * 4) + sw v0, UADDR+U_PCB_REGS+(MULLO * 4) + sw v1, UADDR+U_PCB_REGS+(MULHI * 4) + sw a0, UADDR+U_PCB_REGS+(SR * 4) +#ifdef __GP_SUPPORT__ + la gp, _C_LABEL(_gp) # switch to kernel GP +#endif + sw a3, UADDR+U_PCB_REGS+(PC * 4) + sw a3, STAND_RA_OFFSET(sp) # for debugging + .set at + and t0, a0, ~MACH_SR_COP_1_BIT # Turn off the FPU. + .set noat +/* + * Call the exception handler. + */ + jal _C_LABEL(trap) + mtc0 t0, MACH_COP_0_STATUS_REG +/* + * Restore user registers and return. NOTE: interrupts are enabled. + */ + lw a0, UADDR+U_PCB_REGS+(SR * 4) + lw t0, UADDR+U_PCB_REGS+(MULLO * 4) + lw t1, UADDR+U_PCB_REGS+(MULHI * 4) + mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts + mtlo t0 + mthi t1 + lw k0, UADDR+U_PCB_REGS+(PC * 4) + lw AT, UADDR+U_PCB_REGS+(AST * 4) + lw v0, UADDR+U_PCB_REGS+(V0 * 4) + + RESTORE_USER_REGS() + + j k0 + rfe + .set at +END(mips_r2000_UserGenException) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_KernIntr -- + * + * Handle an interrupt from kernel mode. + * Interrupts use the standard kernel stack. + * switch_exit sets up a kernel stack after exit so interrupts won't fail. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +#define KINTR_REG_OFFSET (STAND_FRAME_SIZE) +#define KINTR_SR_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE) +#define KINTR_MULT_LO_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 4) +#define KINTR_MULT_HI_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 8) +#define KINTR_GP_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 12) +#define KINTR_FRAME_SIZE (STAND_FRAME_SIZE + KERN_REG_SIZE + 16) + +NNON_LEAF(mips_r2000_KernIntr, KINTR_FRAME_SIZE, ra) + .set noat + subu sp, sp, KINTR_FRAME_SIZE # allocate stack frame + .mask 0x80000000, (STAND_RA_OFFSET - KINTR_FRAME_SIZE) +/* + * Save the relevant kernel registers onto the stack. + * We don't need to save s0 - s8 and sp because + * the compiler does it for us. + */ + sw AT, KINTR_REG_OFFSET + 0(sp) + sw v0, KINTR_REG_OFFSET + 4(sp) + sw v1, KINTR_REG_OFFSET + 8(sp) + sw a0, KINTR_REG_OFFSET + 12(sp) + mflo v0 + mfhi v1 + sw a1, KINTR_REG_OFFSET + 16(sp) + sw a2, KINTR_REG_OFFSET + 20(sp) + sw a3, KINTR_REG_OFFSET + 24(sp) + sw t0, KINTR_REG_OFFSET + 28(sp) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t1, KINTR_REG_OFFSET + 32(sp) + sw t2, KINTR_REG_OFFSET + 36(sp) + sw t3, KINTR_REG_OFFSET + 40(sp) + sw t4, KINTR_REG_OFFSET + 44(sp) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw t5, KINTR_REG_OFFSET + 48(sp) + sw t6, KINTR_REG_OFFSET + 52(sp) + sw t7, KINTR_REG_OFFSET + 56(sp) + sw t8, KINTR_REG_OFFSET + 60(sp) + mfc0 a2, MACH_COP_0_EXC_PC # Third arg is the pc. + sw t9, KINTR_REG_OFFSET + 64(sp) + sw ra, KINTR_REG_OFFSET + 68(sp) + sw v0, KINTR_MULT_LO_OFFSET(sp) + sw v1, KINTR_MULT_HI_OFFSET(sp) + sw a0, KINTR_SR_OFFSET(sp) + sw gp, KINTR_GP_OFFSET(sp) +#ifdef __GP_SUPPORT__ + la gp, _C_LABEL(_gp) # switch to kernel GP +#endif +/* + * Call the interrupt handler. + */ + jal _C_LABEL(interrupt) + sw a2, STAND_RA_OFFSET(sp) # for debugging +/* + * Restore registers and return from the interrupt. + */ + lw a0, KINTR_SR_OFFSET(sp) + lw t0, KINTR_MULT_LO_OFFSET(sp) + lw t1, KINTR_MULT_HI_OFFSET(sp) + mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtlo t0 + mthi t1 + lw k0, STAND_RA_OFFSET(sp) + lw AT, KINTR_REG_OFFSET + 0(sp) + lw v0, KINTR_REG_OFFSET + 4(sp) + + RESTORE_KERN_REGISTERS(KINTR_REG_OFFSET) + + addu sp, sp, KINTR_FRAME_SIZE + j k0 # Now return from the + rfe # interrupt. + .set at +END(mips_r2000_KernIntr) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_UserIntr -- + * + * Handle an interrupt from user mode. + * Note: we save minimal state in the u.u_pcb struct and use the standard + * kernel stack since there has to be a u page if we came from user mode. + * If there is a pending software interrupt, then save the remaining state + * and call softintr(). This is all because if we call switch() inside + * interrupt(), not all the user registers have been saved in u.u_pcb. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NNON_LEAF(mips_r2000_UserIntr, STAND_FRAME_SIZE, ra) + .set noat + .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) +/* + * Save the relevant user registers into the u.u_pcb struct. + * We don't need to save s0 - s8 because + * the compiler does it for us. + */ + sw AT, UADDR+U_PCB_REGS+(AST * 4) + sw v0, UADDR+U_PCB_REGS+(V0 * 4) + sw v1, UADDR+U_PCB_REGS+(V1 * 4) + sw a0, UADDR+U_PCB_REGS+(A0 * 4) + mflo v0 + mfhi v1 + sw a1, UADDR+U_PCB_REGS+(A1 * 4) + sw a2, UADDR+U_PCB_REGS+(A2 * 4) + sw a3, UADDR+U_PCB_REGS+(A3 * 4) + sw t0, UADDR+U_PCB_REGS+(T0 * 4) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t1, UADDR+U_PCB_REGS+(T1 * 4) + sw t2, UADDR+U_PCB_REGS+(T2 * 4) + sw t3, UADDR+U_PCB_REGS+(T3 * 4) + sw t4, UADDR+U_PCB_REGS+(T4 * 4) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw t5, UADDR+U_PCB_REGS+(T5 * 4) + sw t6, UADDR+U_PCB_REGS+(T6 * 4) + sw t7, UADDR+U_PCB_REGS+(T7 * 4) + sw t8, UADDR+U_PCB_REGS+(T8 * 4) + mfc0 a2, MACH_COP_0_EXC_PC # Third arg is the pc. + sw t9, UADDR+U_PCB_REGS+(T9 * 4) + sw gp, UADDR+U_PCB_REGS+(GP * 4) + sw sp, UADDR+U_PCB_REGS+(SP * 4) + sw ra, UADDR+U_PCB_REGS+(RA * 4) + li sp, KERNELSTACK - STAND_FRAME_SIZE # switch to kernel SP + sw v0, UADDR+U_PCB_REGS+(MULLO * 4) + sw v1, UADDR+U_PCB_REGS+(MULHI * 4) + sw a0, UADDR+U_PCB_REGS+(SR * 4) + sw a2, UADDR+U_PCB_REGS+(PC * 4) +#ifdef __GP_SUPPORT__ + la gp, _C_LABEL(_gp) # switch to kernel GP +#endif + .set at + and t0, a0, ~MACH_SR_COP_1_BIT # Turn off the FPU. + .set noat + mtc0 t0, MACH_COP_0_STATUS_REG +/* + * Call the interrupt handler. + */ + jal _C_LABEL(interrupt) + sw a2, STAND_RA_OFFSET(sp) # for debugging +/* + * Restore registers and return from the interrupt. + */ + lw a0, UADDR+U_PCB_REGS+(SR * 4) + lw v0, _C_LABEL(astpending) # any pending interrupts? + mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + bne v0, zero, 1f # dont restore, call softintr + lw t0, UADDR+U_PCB_REGS+(MULLO * 4) + lw t1, UADDR+U_PCB_REGS+(MULHI * 4) + lw k0, UADDR+U_PCB_REGS+(PC * 4) + lw AT, UADDR+U_PCB_REGS+(AST * 4) + lw v0, UADDR+U_PCB_REGS+(V0 * 4) + lw v1, UADDR+U_PCB_REGS+(V1 * 4) + lw a0, UADDR+U_PCB_REGS+(A0 * 4) + lw a1, UADDR+U_PCB_REGS+(A1 * 4) + lw a2, UADDR+U_PCB_REGS+(A2 * 4) + lw a3, UADDR+U_PCB_REGS+(A3 * 4) + mtlo t0 + mthi t1 + lw t0, UADDR+U_PCB_REGS+(T0 * 4) + lw t1, UADDR+U_PCB_REGS+(T1 * 4) + lw t2, UADDR+U_PCB_REGS+(T2 * 4) + lw t3, UADDR+U_PCB_REGS+(T3 * 4) + lw t4, UADDR+U_PCB_REGS+(T4 * 4) + lw t5, UADDR+U_PCB_REGS+(T5 * 4) + lw t6, UADDR+U_PCB_REGS+(T6 * 4) + lw t7, UADDR+U_PCB_REGS+(T7 * 4) + lw t8, UADDR+U_PCB_REGS+(T8 * 4) + lw t9, UADDR+U_PCB_REGS+(T9 * 4) + lw gp, UADDR+U_PCB_REGS+(GP * 4) + lw sp, UADDR+U_PCB_REGS+(SP * 4) + lw ra, UADDR+U_PCB_REGS+(RA * 4) + j k0 # Now return from the + rfe # interrupt. + +1: +/* + * We have pending software interrupts; save remaining user state in u.u_pcb. + */ + sw s0, UADDR+U_PCB_REGS+(S0 * 4) + sw s1, UADDR+U_PCB_REGS+(S1 * 4) + sw s2, UADDR+U_PCB_REGS+(S2 * 4) + sw s3, UADDR+U_PCB_REGS+(S3 * 4) + sw s4, UADDR+U_PCB_REGS+(S4 * 4) + sw s5, UADDR+U_PCB_REGS+(S5 * 4) + sw s6, UADDR+U_PCB_REGS+(S6 * 4) + sw s7, UADDR+U_PCB_REGS+(S7 * 4) + sw s8, UADDR+U_PCB_REGS+(S8 * 4) + li t0, MACH_HARD_INT_MASK | MIPS_SR_INT_IE +/* + * Call the software interrupt handler. + */ + jal _C_LABEL(softintr) + mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts (spl0) +/* + * Restore user registers and return. NOTE: interrupts are enabled. + */ + lw a0, UADDR+U_PCB_REGS+(SR * 4) + lw t0, UADDR+U_PCB_REGS+(MULLO * 4) + lw t1, UADDR+U_PCB_REGS+(MULHI * 4) + mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts + mtlo t0 + mthi t1 + lw k0, UADDR+U_PCB_REGS+(PC * 4) + lw AT, UADDR+U_PCB_REGS+(AST * 4) + lw v0, UADDR+U_PCB_REGS+(V0 * 4) + + RESTORE_USER_REGS() + + j k0 + rfe + .set at +END(mips_r2000_UserIntr) + + + +/*---------------------------------------------------------------------------- + * + * XXX START of r3000-specific code XXX + * + *---------------------------------------------------------------------------- + */ + + + +#if 0 +/*---------------------------------------------------------------------------- + * + * mips_r2000_TLBModException -- + * + * Handle a TLB modified exception. + * The BaddVAddr, Context, and EntryHi registers contain the failed + * virtual address. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NLEAF(mips_r2000_TLBModException) + .set noat + tlbp # find the TLB entry + mfc0 k0, MACH_COP_0_TLB_LOW # get the physical address + mfc0 k1, MACH_COP_0_TLB_INDEX # check to be sure its valid + or k0, k0, VMMACH_TLB_MOD_BIT # update TLB + blt k1, zero, 4f # not found!!! + mtc0 k0, MACH_COP_0_TLB_LOW + li k1, MACH_CACHED_MEMORY_ADDR + subu k0, k0, k1 + srl k0, k0, VMMACH_TLB_PHYS_PAGE_SHIFT + la k1, pmap_attributes + addu k0, k0, k1 + lbu k1, 0(k0) # fetch old value + nop + or k1, k1, 1 # set modified bit + sb k1, 0(k0) # save new value + mfc0 k0, MACH_COP_0_EXC_PC # get return address + nop + j k0 + rfe +4: + break 0 # panic + .set at +END(mips_r2000_TLBModException) +#endif + +/*---------------------------------------------------------------------------- + * + * mips_r2000_TLBMissException -- + * + * Handle a TLB miss exception from kernel mode. + * The BaddVAddr, Context, and EntryHi registers contain the failed + * virtual address. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NLEAF(mips_r2000_TLBMissException) + .set noat + mfc0 k0, MACH_COP_0_BAD_VADDR # get the fault address + li k1, VM_MIN_KERNEL_ADDRESS # compute index + subu k0, k0, k1 + lw k1, _C_LABEL(Sysmapsize) # index within range? + srl k0, k0, PGSHIFT + sltu k1, k0, k1 + beq k1, zero, 1f # No. check for valid stack + nop + lw k1, _C_LABEL(Sysmap) + sll k0, k0, 2 # compute offset from index + addu k1, k1, k0 + lw k0, 0(k1) # get PTE entry + mfc0 k1, MACH_COP_0_EXC_PC # get return address + mtc0 k0, MACH_COP_0_TLB_LOW # save PTE entry + and k0, k0, PG_V # check for valid entry + beq k0, zero, _C_LABEL(mips_r2000_KernGenException) # PTE invalid + nop + tlbwr # update TLB + j k1 + rfe + +1: + subu k0, sp, UADDR + 0x200 # check to see if we have a + sltiu k0, UPAGES*NBPG - 0x200 # valid kernel stack + bne k0, zero, _C_LABEL(mips_r2000_KernGenException) # Go panic + nop + + la a0, start - START_FRAME - 8 # set sp to a valid place + sw sp, 24(a0) + move sp, a0 + la a0, 1f + mfc0 a2, MACH_COP_0_STATUS_REG + mfc0 a3, MACH_COP_0_CAUSE_REG + mfc0 a1, MACH_COP_0_EXC_PC + sw a2, 16(sp) + sw a3, 20(sp) + sw sp, 24(sp) + move a2, ra + jal _C_LABEL(printf) + mfc0 a3, MACH_COP_0_BAD_VADDR + .data +1: + .asciiz "ktlbmiss: PC %x RA %x ADR %x\nSR %x CR %x SP %x\n" + .text + + la sp, start - START_FRAME # set sp to a valid place + PANIC("kernel stack overflow") + .set at +END(mips_r2000_TLBMissException) + + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBWriteIndexed -- + * + * Write the given entry into the TLB at the given index. + * + * mips_r2000_TLBWriteIndexed(index, highEntry, lowEntry) + * int index; + * int highEntry; + * int lowEntry; + * + * Results: + * None. + * + * Side effects: + * TLB entry set. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBWriteIndexed) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Save the current PID. + + sll a0, a0, VMMACH_TLB_INDEX_SHIFT + mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index. + mtc0 a1, MACH_COP_0_TLB_HI # Set up entry high. + mtc0 a2, MACH_COP_0_TLB_LOW # Set up entry low. + nop + tlbwi # Write the TLB + + mtc0 t0, MACH_COP_0_TLB_HI # Restore the PID. + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBWriteIndexed) + +#if 0 +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBWriteRandom -- + * + * Write the given entry into the TLB at a random location. + * + * mips_r2000_TLBWriteRandom(highEntry, lowEntry) + * unsigned highEntry; + * unsigned lowEntry; + * + * Results: + * None. + * + * Side effects: + * TLB entry set. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBWriteRandom) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 v0, MACH_COP_0_TLB_HI # Save the current PID. + nop + + mtc0 a0, MACH_COP_0_TLB_HI # Set up entry high. + mtc0 a1, MACH_COP_0_TLB_LOW # Set up entry low. + nop + tlbwr # Write the TLB + + mtc0 v0, MACH_COP_0_TLB_HI # Restore the PID. + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBWriteRandom) +#endif + +/*-------------------------------------------------------------------------- + * + * mips_r2000_SetPID -- + * + * Write the given pid into the TLB pid reg. + * + * mips_r2000_SetPID(pid) + * int pid; + * + * Results: + * None. + * + * Side effects: + * PID set in the entry hi register. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_SetPID) + sll a0, a0, VMMACH_TLB_PID_SHIFT # put PID in right spot + mtc0 a0, MACH_COP_0_TLB_HI # Write the hi reg value + j ra + nop +END(mips_r2000_SetPID) + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBFlush -- + * + * Flush the "random" entries from the TLB. + * + * mips_r2000_TLBFlush() + * + * Results: + * None. + * + * Side effects: + * The TLB is flushed. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBFlush) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Save the PID + li t1, MACH_CACHED_MEMORY_ADDR # invalid address + mtc0 t1, MACH_COP_0_TLB_HI # Mark entry high as invalid + mtc0 zero, MACH_COP_0_TLB_LOW # Zero out low entry. +/* + * Align the starting value (t1) and the upper bound (t2). + */ + li t1, VMMACH_FIRST_RAND_ENTRY << VMMACH_TLB_INDEX_SHIFT + li t2, VMMACH_NUM_TLB_ENTRIES << VMMACH_TLB_INDEX_SHIFT +1: + mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register. + addu t1, t1, 1 << VMMACH_TLB_INDEX_SHIFT # Increment index. + bne t1, t2, 1b + tlbwi # Write the TLB entry. + + mtc0 t0, MACH_COP_0_TLB_HI # Restore the PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBFlush) + +#if 0 +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBFlushPID -- + * + * Flush all entries with the given PID from the TLB. + * + * mips_r2000_TLBFlushPID(pid) + * int pid; + * + * Results: + * None. + * + * Side effects: + * All entries corresponding to this PID are flushed. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBFlushPID) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Save the current PID + sll a0, a0, VMMACH_TLB_PID_SHIFT # Align the pid to flush. +/* + * Align the starting value (t1) and the upper bound (t2). + */ + li t1, VMMACH_FIRST_RAND_ENTRY << VMMACH_TLB_INDEX_SHIFT + li t2, VMMACH_NUM_TLB_ENTRIES << VMMACH_TLB_INDEX_SHIFT + mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register +1: + addu t1, t1, 1 << VMMACH_TLB_INDEX_SHIFT # Increment index. + tlbr # Read from the TLB + mfc0 t4, MACH_COP_0_TLB_HI # Fetch the hi register. + nop + and t4, t4, VMMACH_TLB_PID # compare PIDs + bne t4, a0, 2f + li v0, MACH_CACHED_MEMORY_ADDR # invalid address + mtc0 v0, MACH_COP_0_TLB_HI # Mark entry high as invalid + mtc0 zero, MACH_COP_0_TLB_LOW # Zero out low entry. + nop + tlbwi # Write the entry. +2: + bne t1, t2, 1b + mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register + + mtc0 t0, MACH_COP_0_TLB_HI # restore PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBFlushPID) +#endif + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBFlushAddr -- + * + * Flush any TLB entries for the given address and TLB PID. + * + * mips_r2000_TLBFlushAddr(highreg) + * unsigned highreg; + * + * Results: + * None. + * + * Side effects: + * The process's page is flushed from the TLB. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBFlushAddr) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Get current PID + nop + + mtc0 a0, MACH_COP_0_TLB_HI # look for addr & PID + nop + tlbp # Probe for the entry. + mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got + li t1, MACH_CACHED_MEMORY_ADDR # Load invalid entry. + bltz v0, 1f # index < 0 => !found + mtc0 t1, MACH_COP_0_TLB_HI # Mark entry high as invalid + mtc0 zero, MACH_COP_0_TLB_LOW # Zero out low entry. + nop + tlbwi +1: + mtc0 t0, MACH_COP_0_TLB_HI # restore PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBFlushAddr) + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBUpdate -- + * + * Update the TLB if highreg is found; otherwise, enter the data. + * + * mips_r2000_TLBUpdate(highreg, lowreg) + * unsigned highreg, lowreg; + * + * Results: + * None. + * + * Side effects: + * None. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBUpdate) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Save current PID + nop # 2 cycles before intr disabled + mtc0 a0, MACH_COP_0_TLB_HI # init high reg. + nop + tlbp # Probe for the entry. + mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got + mtc0 a1, MACH_COP_0_TLB_LOW # init low reg. + bltz v0, 1f # index < 0 => !found + sra v0, v0, VMMACH_TLB_INDEX_SHIFT # convert index to regular num + b 2f + tlbwi # update slot found +1: + mtc0 a0, MACH_COP_0_TLB_HI # init high reg. + nop + tlbwr # enter into a random slot +2: + mtc0 t0, MACH_COP_0_TLB_HI # restore PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBUpdate) + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBFind -- + * + * Search the TLB for the given entry. + * + * mips_r2000_TLBFind(hi) + * unsigned hi; + * + * Results: + * Returns a value >= 0 if the entry was found (the index). + * Returns a value < 0 if the entry was not found. + * + * Side effects: + * tlbhi and tlblo will contain the TLB entry found. + * + *-------------------------------------------------------------------------- + */ + .comm tlbhi, 4 + .comm tlblo, 4 +LEAF(mips_r2000_TLBFind) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Get current PID + nop + mtc0 a0, MACH_COP_0_TLB_HI # Set up entry high. + nop + tlbp # Probe for the entry. + mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got + nop + bltz v0, 1f # not found + nop + tlbr # read TLB + mfc0 t1, MACH_COP_0_TLB_HI # See what we got + mfc0 t2, MACH_COP_0_TLB_LOW # See what we got + sw t1, tlbhi + sw t2, tlblo + srl v0, v0, VMMACH_TLB_INDEX_SHIFT # convert index to regular num +1: + mtc0 t0, MACH_COP_0_TLB_HI # Restore current PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBFind) + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBRead -- + * + * Read the TLB entry. + * + * mips_r2000_TLBRead(entry) + * unsigned entry; + * + * Results: + * None. + * + * Side effects: + * tlbhi and tlblo will contain the TLB entry found. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBRead) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t0, MACH_COP_0_TLB_HI # Get current PID + + sll a0, a0, VMMACH_TLB_INDEX_SHIFT + mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index register + nop + tlbr # Read from the TLB + mfc0 t3, MACH_COP_0_TLB_HI # fetch the hi entry + mfc0 t4, MACH_COP_0_TLB_LOW # fetch the low entry + sw t3, tlbhi + sw t4, tlblo + + mtc0 t0, MACH_COP_0_TLB_HI # restore PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r2000_TLBRead) + +/*-------------------------------------------------------------------------- + * + * mips_r2000_TLBGetPID -- + * + * mips_r2000_TLBGetPID() + * + * Results: + * Returns the current TLB pid reg. + * + * Side effects: + * None. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r2000_TLBGetPID) + mfc0 v0, MACH_COP_0_TLB_HI # get PID + nop + and v0, v0, VMMACH_TLB_PID # mask off PID + j ra + srl v0, v0, VMMACH_TLB_PID_SHIFT # put PID in right spot +END(mips_r2000_TLBGetPID) + + +/*---------------------------------------------------------------------------- + * + * R3000 cache sizing and flushing code. + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * + * mips_r2000_ConfigCache -- + * + * Size the caches. + * NOTE: should only be called from mach_init(). + * + * Results: + * None. + * + * Side effects: + * The size of the data cache is stored into machDataCacheSize and the + * size of instruction cache is stored into machInstCacheSize. + * + *---------------------------------------------------------------------------- + */ +NON_LEAF(mips_r2000_ConfigCache, STAND_FRAME_SIZE, ra) + subu sp, sp, STAND_FRAME_SIZE + sw ra, STAND_RA_OFFSET(sp) # Save return address. + .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts. + la v0, 1f + or v0, MACH_UNCACHED_MEMORY_ADDR # Run uncached. + j v0 + nop +1: +/* + * This works because jal doesn't change pc[31..28] and the + * linker still thinks SizeCache is in the cached region so it computes + * the correct address without complaining. + */ + jal _C_LABEL(mips_r2000_SizeCache) # Get the size of the d-cache. + nop + sw v0, _C_LABEL(machDataCacheSize) + nop # Make sure sw out of pipe + nop + nop + nop + li v0, MACH_SR_SWAP_CACHES # Swap caches + mtc0 v0, MACH_COP_0_STATUS_REG + nop # Insure caches stable + nop + nop + nop + jal _C_LABEL(mips_r2000_SizeCache) # Get the size of the i-cache. + nop + mtc0 zero, MACH_COP_0_STATUS_REG # Swap back caches and enable. + nop + nop + nop + nop + sw v0, _C_LABEL(machInstCacheSize) + la t0, 1f + j t0 # Back to cached mode + nop +1: + lw ra, STAND_RA_OFFSET(sp) # Restore return addr + addu sp, sp, STAND_FRAME_SIZE # Restore sp. + j ra + nop +END(mips_r2000_ConfigCache) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_SizeCache -- + * + * Get the size of the cache. + * + * Results: + * The size of the cache. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r2000_SizeCache) + mfc0 t0, MACH_COP_0_STATUS_REG # Save the current status reg. + nop + or v0, t0, MACH_SR_ISOL_CACHES # Isolate the caches. + nop # Make sure no stores in pipe + mtc0 v0, MACH_COP_0_STATUS_REG + nop # Make sure isolated + nop + nop +/* + * Clear cache size boundaries. + */ + li v0, MACH_MIN_CACHE_SIZE + li v1, MACH_CACHED_MEMORY_ADDR + li t2, MACH_MAX_CACHE_SIZE +1: + addu t1, v0, v1 # Compute address to clear + sw zero, 0(t1) # Clear cache memory + bne v0, t2, 1b + sll v0, v0, 1 + + li v0, -1 + sw v0, 0(v1) # Store marker in cache + li v0, MACH_MIN_CACHE_SIZE +2: + addu t1, v0, v1 # Compute address + lw t3, 0(t1) # Look for marker + nop + bne t3, zero, 3f # Found marker. + nop + bne v0, t2, 2b # keep looking + sll v0, v0, 1 # cache size * 2 + + move v0, zero # must be no cache +3: + mtc0 t0, MACH_COP_0_STATUS_REG + nop # Make sure unisolated + nop + nop + nop + j ra + nop +END(mips_r2000_SizeCache) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_FlushCache -- + * + * Flush the caches. + * + * Results: + * None. + * + * Side effects: + * The contents of the caches is flushed. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r2000_FlushCache) + lw t1, _C_LABEL(machInstCacheSize) # Must load before isolating + lw t2, _C_LABEL(machDataCacheSize) # Must load before isolating + mfc0 t3, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts. + la v0, 1f + or v0, MACH_UNCACHED_MEMORY_ADDR # Run uncached. + j v0 + nop +/* + * Flush the instruction cache. + */ +1: + li v0, MACH_SR_ISOL_CACHES | MACH_SR_SWAP_CACHES + mtc0 v0, MACH_COP_0_STATUS_REG # Isolate and swap caches. + li t0, MACH_UNCACHED_MEMORY_ADDR + subu t0, t0, t1 + li t1, MACH_UNCACHED_MEMORY_ADDR + la v0, 1f # Run cached + j v0 + nop +1: + addu t0, t0, 4 + bne t0, t1, 1b + sb zero, -4(t0) + + la v0, 1f + or v0, MACH_UNCACHED_MEMORY_ADDR + j v0 # Run uncached + nop +/* + * Flush the data cache. + */ +1: + li v0, MACH_SR_ISOL_CACHES + mtc0 v0, MACH_COP_0_STATUS_REG # Isolate and swap back caches + li t0, MACH_UNCACHED_MEMORY_ADDR + subu t0, t0, t2 + la v0, 1f + j v0 # Back to cached mode + nop +1: + addu t0, t0, 4 + bne t0, t1, 1b + sb zero, -4(t0) + + nop # Insure isolated stores + nop # out of pipe. + nop + nop + mtc0 t3, MACH_COP_0_STATUS_REG # Restore status reg. + nop # Insure cache unisolated. + nop + nop + nop + j ra + nop +END(mips_r2000_FlushCache) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_FlushICache -- + * + * void mips_r2000_FlushICache(addr, len) + * vm_offset_t addr, len; + * + * Flush instruction cache for range of addr to addr + len - 1. + * The address can be any valid address so long as no TLB misses occur. + * + * Results: + * None. + * + * Side effects: + * The contents of the cache is flushed. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r2000_FlushICache) + mfc0 t0, MACH_COP_0_STATUS_REG # Save SR + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts. + + la v1, 1f + or v1, MACH_UNCACHED_MEMORY_ADDR # Run uncached. + j v1 + nop +1: + bc0f 1b # make sure stores are complete + li v1, MACH_SR_ISOL_CACHES | MACH_SR_SWAP_CACHES + mtc0 v1, MACH_COP_0_STATUS_REG + nop + addu a1, a1, a0 # compute ending address +1: + addu a0, a0, 4 + bne a0, a1, 1b + sb zero, -4(a0) + + mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts + j ra # return and run cached + nop +END(mips_r2000_FlushICache) + +/*---------------------------------------------------------------------------- + * + * mips_r2000_FlushDCache -- + * + * void mips_r2000_FlushDCache(addr, len) + * vm_offset_t addr, len; + * + * Flush data cache for range of addr to addr + len - 1. + * The address can be any valid address so long as no TLB misses occur. + * (Be sure to use cached K0SEG kernel addresses) + * Results: + * None. + * + * Side effects: + * The contents of the cache is flushed. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r2000_FlushDCache) + mfc0 t0, MACH_COP_0_STATUS_REG # Save SR + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts. + nop +1: + bc0f 1b # make sure stores are complete +# BUG: should drain write buffer. +# The insn above does not work on some all DEC machines, or all variants +# of the mips architecture. + li v1, MACH_SR_ISOL_CACHES + mtc0 v1, MACH_COP_0_STATUS_REG + nop + addu t1, a1, a0 # compute ending address +1: + sb zero, 0(a0) + sb zero, 4(a0) + sb zero, 8(a0) + sb zero, 12(a0) + sb zero, 16(a0) + sb zero, 20(a0) + sb zero, 24(a0) + addu a0, 32 + bltu a0, t1, 1b + sb zero, -4(a0) + + nop # drain pipeline + nop + mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts + nop + j ra # return and run cached + nop +END(mips_r2000_FlushDCache) + +/*---------------------------------------------------------------------------- + * + * XXX END of r3000-specific code XXX + * + *---------------------------------------------------------------------------- + */ + diff --git a/sys/arch/pmax/pmax/locore_r4000.S b/sys/arch/pmax/pmax/locore_r4000.S new file mode 100644 index 00000000000..21668b06306 --- /dev/null +++ b/sys/arch/pmax/pmax/locore_r4000.S @@ -0,0 +1,1431 @@ + +/* + *============================================================================ + * + * Mips-III ISA support, part 1: locore exception vectors. + * The following code is copied to the vector locations to which + * the CPU jumps in response to an exception or a TLB miss. + * + *============================================================================ + + +/* + *---------------------------------------------------------------------------- + * + * mips_R4000_TLBMiss -- + * MachTLBMiss -- + * + * Vector code for the TLB-miss exception vector 0x80000180 + * on an r4000. + * + * This code is copied to the TLB exception vector address to + * handle TLB translation misses. + * NOTE: This code must be relocatable and max 32 instructions!!! + * Don't check for invalid pte's here. We load them as well and + * let the processor trap to load the correct value after service. + * + *---------------------------------------------------------------------------- + */ + .globl _C_LABEL(mips_R4000_TLBMiss) +_C_LABEL(mips_R4000_TLBMiss): + .globl _C_LABEL(MachTLBMiss) +_C_LABEL(MachTLBMiss): + .set noat + dmfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address + lw k1, UADDR+U_PCB_SEGTAB # get the current segment table + bltz k0, 1f # kernel address space -> + srl k0, k0, SEGSHIFT - 2 # compute segment table index + andi k0, k0, 0x7fc # PMAP_SEGTABSIZ-1 + addu k1, k1, k0 + dmfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address + lw k1, 0(k1) # get pointer to segment map + srl k0, k0, PGSHIFT - 2 # compute segment map index + andi k0, k0, ((NPTEPG/2) - 1) << 3 + beq k1, zero, 2f # invalid segment map + addu k1, k1, k0 # index into segment map + lw k0, 0(k1) # get page PTE + lw k1, 4(k1) + dsll k0, k0, 34 + dsrl k0, k0, 34 + dmtc0 k0, MACH_COP_0_TLB_LO0 + dsll k1, k1, 34 + dsrl k1, k1, 34 + dmtc0 k1, MACH_COP_0_TLB_LO1 + nop + tlbwr # update TLB + nop + nop + nop + nop + nop + eret +1: + j MachTLBMissException + nop +2: + j SlowFault + nop + + .globl _C_LABEL(MachTLBMissEnd) +C_LABEL(MachTLBMissEnd): + .globl _C_LABEL(mips_R4000_TLBMissEnd) +_C_LABEL(mips_R4000_TLBMissEnd): + .set at +#endif /* XXX doesn't assemble in default pmax kernel *//* + + + *---------------------------------------------------------------------------- + * + * Mips_R4000_execption -- + * + * Vector code for the general exception vector 0x80000080 + * on an r4000 or r4400. + * + * This code is copied to the general exception vector address to + * handle all execptions except RESET and TLBMiss. + * NOTE: This code must be relocatable!!! + *---------------------------------------------------------------------------- + */ + .globl mips_r4000_exception +_C_LABEL(mips_R4000_exception): +/* + * Find out what mode we came from and jump to the proper handler. + */ + .set noat + mfc0 k0, MACH_COP_0_STATUS_REG # Get the status register + mfc0 k1, MACH_COP_0_CAUSE_REG # Get the cause register value. + and k0, k0, MIPS_4K_SR_KSU_USER # test for user mode + # sneaky but the bits are + # with us........ + sll k0, k0, 3 # shift user bit for cause index + and k1, k1, MIPS_4K_CR_EXC_CODE # Mask out the cause bits. + or k1, k1, k0 # change index to user table +1: + la k0, machExceptionTable # get base of the jump table + addu k0, k0, k1 # Get the address of the + # function entry. Note that + # the cause is already + # shifted left by 2 bits so + # we dont have to shift. + lw k0, 0(k0) # Get the function address + nop + j k0 # Jump to the function. + nop + .set at + .globl mips_R4000_exceptionEnd +_C_LABEL(mips_R4000_exceptionEnd): + + +/*---------------------------------------------------------------------------- + * + * mips_r4000_SlowFault -- + * + * Alternate entry point into the mips_r2000_UserGenExceptionor or + * or mips_r2000_user_Kern_exception, when the ULTB miss handler couldn't + * find a TLB entry. + * + * Find out what mode we came from and call the appropriate handler. + * + *---------------------------------------------------------------------------- + */ + +/* + * We couldn't find a TLB entry. + * Find out what mode we came from and call the appropriate handler. + */ +mips_r4000_SlowFault: + .set noat + mfc0 k0, MACH_COP_0_STATUS_REG + nop + and k0, k0, MACH_SR_KSU_USER + bne k0, zero, mips_r4000_UserGenException + nop + .set at +/* + * Fall though ... + */ + +/*---------------------------------------------------------------------------- + * + * mips_r4000_KernGenException -- + * + * Handle an exception from kernel mode. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ + +/* + * The kernel exception stack contains 18 saved general registers, + * the status register and the multiply lo and high registers. + * In addition, we set this up for linkage conventions. + */ +#define KERN_REG_SIZE (18 * 4) +#define KERN_REG_OFFSET (STAND_FRAME_SIZE) +#define KERN_SR_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE) +#define KERN_MULT_LO_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 4) +#define KERN_MULT_HI_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 8) +#define KERN_EXC_FRAME_SIZE (STAND_FRAME_SIZE + KERN_REG_SIZE + 12) + +NNON_LEAF(mips_r4000_KernGenException, KERN_EXC_FRAME_SIZE, ra) + .set noat +#ifdef DEBUG + la k0, mdbpcb # save registers for mdb + sw s0, (S0 * 4)(k0) + sw s1, (S1 * 4)(k0) + sw s2, (S2 * 4)(k0) + sw s3, (S3 * 4)(k0) + sw s4, (S4 * 4)(k0) + sw s5, (S5 * 4)(k0) + sw s6, (S6 * 4)(k0) + sw s7, (S7 * 4)(k0) + sw s8, (S8 * 4)(k0) + sw gp, (GP * 4)(k0) + sw sp, (SP * 4)(k0) +#endif + subu sp, sp, KERN_EXC_FRAME_SIZE + .mask 0x80000000, (STAND_RA_OFFSET - KERN_EXC_FRAME_SIZE) +/* + * Save the relevant kernel registers onto the stack. + * We don't need to save s0 - s8, sp and gp because + * the compiler does it for us. + */ + sw AT, KERN_REG_OFFSET + 0(sp) + sw v0, KERN_REG_OFFSET + 4(sp) + sw v1, KERN_REG_OFFSET + 8(sp) + sw a0, KERN_REG_OFFSET + 12(sp) + mflo v0 + mfhi v1 + sw a1, KERN_REG_OFFSET + 16(sp) + sw a2, KERN_REG_OFFSET + 20(sp) + sw a3, KERN_REG_OFFSET + 24(sp) + sw t0, KERN_REG_OFFSET + 28(sp) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t1, KERN_REG_OFFSET + 32(sp) + sw t2, KERN_REG_OFFSET + 36(sp) + sw t3, KERN_REG_OFFSET + 40(sp) + sw t4, KERN_REG_OFFSET + 44(sp) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw t5, KERN_REG_OFFSET + 48(sp) + sw t6, KERN_REG_OFFSET + 52(sp) + sw t7, KERN_REG_OFFSET + 56(sp) + sw t8, KERN_REG_OFFSET + 60(sp) + mfc0 a2, MACH_COP_0_BAD_VADDR # Third arg is the fault addr. + sw t9, KERN_REG_OFFSET + 64(sp) + sw ra, KERN_REG_OFFSET + 68(sp) + sw v0, KERN_MULT_LO_OFFSET(sp) + sw v1, KERN_MULT_HI_OFFSET(sp) + mfc0 a3, MACH_COP_0_EXC_PC # Fourth arg is the pc. + sw a0, KERN_SR_OFFSET(sp) + + mtc0 zero,MACH_COP_0_STATUS_REG # Set kernel no error level +/* + * Call the exception handler. + */ + jal trap + sw a3, STAND_RA_OFFSET(sp) # for debugging +/* + * Restore registers and return from the exception. + * v0 contains the return address. + */ + mtc0 zero,MACH_COP_0_STATUS_REG # Make shure int disabled + lw a0, KERN_SR_OFFSET(sp) + lw t0, KERN_MULT_LO_OFFSET(sp) + lw t1, KERN_MULT_HI_OFFSET(sp) + mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtlo t0 + mthi t1 + dmtc0 v0, MACH_COP_0_EXC_PC # set return address + + lw AT, KERN_REG_OFFSET + 0(sp) + lw v0, KERN_REG_OFFSET + 4(sp) + + RESTORE_KERN_REGISTERS(KINTR_REG_OFFSET) + + addu sp, sp, KERN_EXC_FRAME_SIZE + eret # exception. + .set at +END(mips_r4000_KernGenException) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_UserGenException -- + * + * Handle an exception from user mode. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NNON_LEAF(mips_r4000_UserGenException, STAND_FRAME_SIZE, ra) + .set noat + .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) +/* + * Save all of the registers except for the kernel temporaries in u.u_pcb. + */ + sw AT, UADDR+U_PCB_REGS+(AST * 4) + sw v0, UADDR+U_PCB_REGS+(V0 * 4) + sw v1, UADDR+U_PCB_REGS+(V1 * 4) + sw a0, UADDR+U_PCB_REGS+(A0 * 4) + mflo v0 + sw a1, UADDR+U_PCB_REGS+(A1 * 4) + sw a2, UADDR+U_PCB_REGS+(A2 * 4) + sw a3, UADDR+U_PCB_REGS+(A3 * 4) + sw t0, UADDR+U_PCB_REGS+(T0 * 4) + mfhi v1 + sw t1, UADDR+U_PCB_REGS+(T1 * 4) + sw t2, UADDR+U_PCB_REGS+(T2 * 4) + sw t3, UADDR+U_PCB_REGS+(T3 * 4) + sw t4, UADDR+U_PCB_REGS+(T4 * 4) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t5, UADDR+U_PCB_REGS+(T5 * 4) + sw t6, UADDR+U_PCB_REGS+(T6 * 4) + sw t7, UADDR+U_PCB_REGS+(T7 * 4) + sw s0, UADDR+U_PCB_REGS+(S0 * 4) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw s1, UADDR+U_PCB_REGS+(S1 * 4) + sw s2, UADDR+U_PCB_REGS+(S2 * 4) + sw s3, UADDR+U_PCB_REGS+(S3 * 4) + sw s4, UADDR+U_PCB_REGS+(S4 * 4) + mfc0 a2, MACH_COP_0_BAD_VADDR # Third arg is the fault addr + sw s5, UADDR+U_PCB_REGS+(S5 * 4) + sw s6, UADDR+U_PCB_REGS+(S6 * 4) + sw s7, UADDR+U_PCB_REGS+(S7 * 4) + sw t8, UADDR+U_PCB_REGS+(T8 * 4) + mfc0 a3, MACH_COP_0_EXC_PC # Fourth arg is the pc. + sw t9, UADDR+U_PCB_REGS+(T9 * 4) + sw gp, UADDR+U_PCB_REGS+(GP * 4) + sw sp, UADDR+U_PCB_REGS+(SP * 4) + sw s8, UADDR+U_PCB_REGS+(S8 * 4) + li sp, KERNELSTACK - STAND_FRAME_SIZE # switch to kernel SP + sw ra, UADDR+U_PCB_REGS+(RA * 4) + sw v0, UADDR+U_PCB_REGS+(MULLO * 4) + sw v1, UADDR+U_PCB_REGS+(MULHI * 4) + sw a0, UADDR+U_PCB_REGS+(SR * 4) + la gp, _gp # switch to kernel GP + sw a3, UADDR+U_PCB_REGS+(PC * 4) + sw a3, STAND_RA_OFFSET(sp) # for debugging + .set at +# Turn off fpu and enter kernel mode + and t0, a0, ~(MACH_SR_COP_1_BIT | MACH_SR_EXL | MACH_SR_KSU_MASK | MIPS_SR_INT_IE) + .set noat +/* + * Call the exception handler. + */ + jal trap + mtc0 t0, MACH_COP_0_STATUS_REG +/* + * Restore user registers and return. + * First disable interrupts and set exeption level. + */ + mtc0 zero, MACH_COP_0_STATUS_REG # disable int + nop + nop + nop + li v0, MACH_SR_EXL + mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level + + lw a0, UADDR+U_PCB_REGS+(SR * 4) + lw t0, UADDR+U_PCB_REGS+(MULLO * 4) + lw t1, UADDR+U_PCB_REGS+(MULHI * 4) + mtc0 a0, MACH_COP_0_STATUS_REG # still exeption level + mtlo t0 + mthi t1 + lw a0, UADDR+U_PCB_REGS+(PC * 4) + lw AT, UADDR+U_PCB_REGS+(AST * 4) + lw v0, UADDR+U_PCB_REGS+(V0 * 4) + dmtc0 a0, MACH_COP_0_EXC_PC # set return address + + RESTORE_USER_REGS() + + eret + .set at +END(mips_r4000_UserGenException) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_KernIntr -- + * + * Handle an interrupt from kernel mode. + * Interrupts use the standard kernel stack. + * switch_exit sets up a kernel stack after exit so interrupts won't fail. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +#define KINTR_REG_OFFSET (STAND_FRAME_SIZE) +#define KINTR_SR_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE) +#define KINTR_MULT_LO_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 4) +#define KINTR_MULT_HI_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 8) +#define KINTR_MULT_GP_OFFSET (STAND_FRAME_SIZE + KERN_REG_SIZE + 12) +#define KINTR_FRAME_SIZE (STAND_FRAME_SIZE + KERN_REG_SIZE + 16) + +NNON_LEAF(mips_r4000_KernIntr, KINTR_FRAME_SIZE, ra) + .set noat + subu sp, sp, KINTR_FRAME_SIZE # allocate stack frame + .mask 0x80000000, (STAND_RA_OFFSET - KINTR_FRAME_SIZE) +/* + * Save the relevant kernel registers onto the stack. + * We don't need to save s0 - s8, sp and gp because + * the compiler does it for us. + */ + sw AT, KINTR_REG_OFFSET + 0(sp) + sw v0, KINTR_REG_OFFSET + 4(sp) + sw v1, KINTR_REG_OFFSET + 8(sp) + sw a0, KINTR_REG_OFFSET + 12(sp) + mflo v0 + mfhi v1 + sw a1, KINTR_REG_OFFSET + 16(sp) + sw a2, KINTR_REG_OFFSET + 20(sp) + sw a3, KINTR_REG_OFFSET + 24(sp) + sw t0, KINTR_REG_OFFSET + 28(sp) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t1, KINTR_REG_OFFSET + 32(sp) + sw t2, KINTR_REG_OFFSET + 36(sp) + sw t3, KINTR_REG_OFFSET + 40(sp) + sw t4, KINTR_REG_OFFSET + 44(sp) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw t5, KINTR_REG_OFFSET + 48(sp) + sw t6, KINTR_REG_OFFSET + 52(sp) + sw t7, KINTR_REG_OFFSET + 56(sp) + sw t8, KINTR_REG_OFFSET + 60(sp) + mfc0 a2, MACH_COP_0_EXC_PC # Third arg is the pc. + sw t9, KINTR_REG_OFFSET + 64(sp) + sw ra, KINTR_REG_OFFSET + 68(sp) + sw v0, KINTR_MULT_LO_OFFSET(sp) + sw v1, KINTR_MULT_HI_OFFSET(sp) + sw a0, KINTR_SR_OFFSET(sp) + + mtc0 zero, MACH_COP_0_STATUS_REG # Reset exl, trap possible. +/* + * Call the interrupt handler. + */ + jal interrupt + sw a2, STAND_RA_OFFSET(sp) # for debugging +/* + * Restore registers and return from the interrupt. + */ + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupt + lw a0, KINTR_SR_OFFSET(sp) + lw t0, KINTR_MULT_LO_OFFSET(sp) + lw t1, KINTR_MULT_HI_OFFSET(sp) + mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtlo t0 + mthi t1 + lw a0, STAND_RA_OFFSET(sp) + lw AT, KINTR_REG_OFFSET + 0(sp) + lw v0, KINTR_REG_OFFSET + 4(sp) + dmtc0 a0, MACH_COP_0_EXC_PC # set return address + + RESTORE_KERN_REGISTERS(KINTR_REG_OFFSET) + + addu sp, sp, KINTR_FRAME_SIZE + eret # interrupt. + .set at +END(mips_r4000_KernIntr) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_UserIntr -- + * + * Handle an interrupt from user mode. + * Note: we save minimal state in the u.u_pcb struct and use the standard + * kernel stack since there has to be a u page if we came from user mode. + * If there is a pending software interrupt, then save the remaining state + * and call softintr(). This is all because if we call switch() inside + * interrupt(), not all the user registers have been saved in u.u_pcb. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NNON_LEAF(mips_r4000_UserIntr, STAND_FRAME_SIZE, ra) + .set noat + .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) +/* + * Save the relevant user registers into the u.u_pcb struct. + * We don't need to save s0 - s8 because + * the compiler does it for us. + */ + sw AT, UADDR+U_PCB_REGS+(AST * 4) + sw v0, UADDR+U_PCB_REGS+(V0 * 4) + sw v1, UADDR+U_PCB_REGS+(V1 * 4) + sw a0, UADDR+U_PCB_REGS+(A0 * 4) + mflo v0 + mfhi v1 + sw a1, UADDR+U_PCB_REGS+(A1 * 4) + sw a2, UADDR+U_PCB_REGS+(A2 * 4) + sw a3, UADDR+U_PCB_REGS+(A3 * 4) + sw t0, UADDR+U_PCB_REGS+(T0 * 4) + mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + sw t1, UADDR+U_PCB_REGS+(T1 * 4) + sw t2, UADDR+U_PCB_REGS+(T2 * 4) + sw t3, UADDR+U_PCB_REGS+(T3 * 4) + sw t4, UADDR+U_PCB_REGS+(T4 * 4) + mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + sw t5, UADDR+U_PCB_REGS+(T5 * 4) + sw t6, UADDR+U_PCB_REGS+(T6 * 4) + sw t7, UADDR+U_PCB_REGS+(T7 * 4) + sw t8, UADDR+U_PCB_REGS+(T8 * 4) + mfc0 a2, MACH_COP_0_EXC_PC # Third arg is the pc. + sw t9, UADDR+U_PCB_REGS+(T9 * 4) + sw gp, UADDR+U_PCB_REGS+(GP * 4) + sw sp, UADDR+U_PCB_REGS+(SP * 4) + sw ra, UADDR+U_PCB_REGS+(RA * 4) + li sp, KERNELSTACK - STAND_FRAME_SIZE # switch to kernel SP + sw v0, UADDR+U_PCB_REGS+(MULLO * 4) + sw v1, UADDR+U_PCB_REGS+(MULHI * 4) + sw a0, UADDR+U_PCB_REGS+(SR * 4) + sw a2, UADDR+U_PCB_REGS+(PC * 4) + la gp, _gp # switch to kernel GP +# Turn off fpu and enter kernel mode + .set at + and t0, a0, ~(MACH_SR_COP_1_BIT | MACH_SR_EXL | MIPS_SR_INT_IE | MACH_SR_KSU_MASK) + .set noat + mtc0 t0, MACH_COP_0_STATUS_REG +/* + * Call the interrupt handler. + */ + jal interrupt + sw a2, STAND_RA_OFFSET(sp) # for debugging +/* + * Restore registers and return from the interrupt. + */ + mtc0 zero, MACH_COP_0_STATUS_REG + nop + nop + nop + li v0, MACH_SR_EXL + mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level bit. + + lw a0, UADDR+U_PCB_REGS+(SR * 4) + lw v0, astpending # any pending interrupts? + mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + bne v0, zero, 1f # dont restore, call softintr + lw t0, UADDR+U_PCB_REGS+(MULLO * 4) + lw t1, UADDR+U_PCB_REGS+(MULHI * 4) + lw a0, UADDR+U_PCB_REGS+(PC * 4) + lw AT, UADDR+U_PCB_REGS+(AST * 4) + lw v0, UADDR+U_PCB_REGS+(V0 * 4) + dmtc0 a0, MACH_COP_0_EXC_PC # set return address + lw v1, UADDR+U_PCB_REGS+(V1 * 4) + lw a0, UADDR+U_PCB_REGS+(A0 * 4) + lw a1, UADDR+U_PCB_REGS+(A1 * 4) + lw a2, UADDR+U_PCB_REGS+(A2 * 4) + lw a3, UADDR+U_PCB_REGS+(A3 * 4) + mtlo t0 + mthi t1 + lw t0, UADDR+U_PCB_REGS+(T0 * 4) + lw t1, UADDR+U_PCB_REGS+(T1 * 4) + lw t2, UADDR+U_PCB_REGS+(T2 * 4) + lw t3, UADDR+U_PCB_REGS+(T3 * 4) + lw t4, UADDR+U_PCB_REGS+(T4 * 4) + lw t5, UADDR+U_PCB_REGS+(T5 * 4) + lw t6, UADDR+U_PCB_REGS+(T6 * 4) + lw t7, UADDR+U_PCB_REGS+(T7 * 4) + lw t8, UADDR+U_PCB_REGS+(T8 * 4) + lw t9, UADDR+U_PCB_REGS+(T9 * 4) + lw gp, UADDR+U_PCB_REGS+(GP * 4) + lw sp, UADDR+U_PCB_REGS+(SP * 4) + lw ra, UADDR+U_PCB_REGS+(RA * 4) + eret # interrupt. + +1: +/* + * We have pending software interrupts; save remaining user state in u.u_pcb. + */ + sw s0, UADDR+U_PCB_REGS+(S0 * 4) + sw s1, UADDR+U_PCB_REGS+(S1 * 4) + sw s2, UADDR+U_PCB_REGS+(S2 * 4) + sw s3, UADDR+U_PCB_REGS+(S3 * 4) + sw s4, UADDR+U_PCB_REGS+(S4 * 4) + sw s5, UADDR+U_PCB_REGS+(S5 * 4) + sw s6, UADDR+U_PCB_REGS+(S6 * 4) + sw s7, UADDR+U_PCB_REGS+(S7 * 4) + sw s8, UADDR+U_PCB_REGS+(S8 * 4) + li t0, MACH_HARD_INT_MASK | MIPS_SR_INT_IE +/* + * Call the software interrupt handler. + */ + jal softintr + mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts (spl0) +/* + * Restore user registers and return. NOTE: interrupts are enabled. + */ + mtc0 zero, MACH_COP_0_STATUS_REG + nop + nop + nop + li v0, MACH_SR_EXL + mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level bit. + + lw a0, UADDR+U_PCB_REGS+(SR * 4) + lw t0, UADDR+U_PCB_REGS+(MULLO * 4) + lw t1, UADDR+U_PCB_REGS+(MULHI * 4) + mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts + mtlo t0 + mthi t1 + lw a0, UADDR+U_PCB_REGS+(PC * 4) + lw AT, UADDR+U_PCB_REGS+(AST * 4) + lw v0, UADDR+U_PCB_REGS+(V0 * 4) + dmtc0 a0, MACH_COP_0_EXC_PC # set return address + + /*XXX*/ + RESTORE_USER_REGS() + + eret + .set at +END(mips_r4000_UserIntr) + + +/*---------------------------------------------------------------------------- + * + * XXX START of r4000-specific code XXX + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * + * R4000 TLB exception handlers + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * + * mips_r4000_TLBMInvalidException -- + * + * Handle a TLB invalid exception from kernel mode in kernel space. + * The BaddVAddr, Context, and EntryHi registers contain the failed + * virtual address. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NLEAF(mips_r4000_TLBInvalidException) + .set noat + dmfc0 k0, MACH_COP_0_BAD_VADDR # get the fault address + li k1, VM_MIN_KERNEL_ADDRESS # compute index + subu k0, k0, k1 + lw k1, Sysmapsize # index within range? + srl k0, k0, PGSHIFT + sltu k1, k0, k1 + beq k1, zero, sys_stk_chk # No. check for valid stack + lw k1, Sysmap + + sll k0, k0, 2 # compute offset from index + tlbp # Probe the invalid entry + addu k1, k1, k0 + and k0, k0, 4 # check even/odd page + bne k0, zero, KernTLBIOdd + nop + + mfc0 k0, MACH_COP_0_TLB_INDEX + nop + bltz k0, sys_stk_chk + sltiu k0, k0, 8 + + bne k0, zero, sys_stk_chk + lw k0, 0(k1) # get PTE entry + + dsll k0, k0, 34 # get rid of "wired" bit + dsrl k0, k0, 34 + dmtc0 k0, MACH_COP_0_TLB_LO0 # load PTE entry + and k0, k0, PG_V # check for valid entry + beq k0, zero, mips_r4000_KernGenException # PTE invalid + lw k0, 4(k1) # get odd PTE entry + dsll k0, k0, 34 + dsrl k0, k0, 34 + dmtc0 k0, MACH_COP_0_TLB_LO1 # load PTE entry + nop + tlbwi # write TLB + nop + nop + nop + nop + nop + eret + +KernTLBIOdd: + mfc0 k0, MACH_COP_0_TLB_INDEX + nop + bltz k0, sys_stk_chk + sltiu k0, k0, 8 + + bne k0, zero, sys_stk_chk + lw k0, 0(k1) # get PTE entry + + dsll k0, k0, 34 # get rid of wired bit + dsrl k0, k0, 34 + dmtc0 k0, MACH_COP_0_TLB_LO1 # save PTE entry + and k0, k0, PG_V # check for valid entry + beq k0, zero, mips_r4000_KernGenException # PTE invalid + lw k0, -4(k1) # get even PTE entry + dsll k0, k0, 34 + dsrl k0, k0, 34 + dmtc0 k0, MACH_COP_0_TLB_LO0 # save PTE entry + nop + tlbwi # update TLB + nop + nop + nop + nop + nop + eret +END(mips_r4000_TLBInvalidException) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_TLBMissException -- + * + * Handle a TLB miss exception from kernel mode in kernel space. + * The BaddVAddr, Context, and EntryHi registers contain the failed + * virtual address. + * + * Results: + * None. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------------- + */ +NLEAF(mips_r4000_TLBMissException) + .set noat + dmfc0 k0, MACH_COP_0_BAD_VADDR # get the fault address + li k1, VM_MIN_KERNEL_ADDRESS # compute index + subu k0, k0, k1 + lw k1, Sysmapsize # index within range? + srl k0, k0, PGSHIFT + sltu k1, k0, k1 + beq k1, zero, sys_stk_chk # No. check for valid stack + lw k1, Sysmap + srl k0, k0, 1 + sll k0, k0, 3 # compute offset from index + addu k1, k1, k0 + lw k0, 0(k1) # get PTE entry + lw k1, 4(k1) # get odd PTE entry + dsll k0, k0, 34 # get rid of "wired" bit + dsrl k0, k0, 34 + dmtc0 k0, MACH_COP_0_TLB_LO0 # load PTE entry + dsll k1, k1, 34 + dsrl k1, k1, 34 + dmtc0 k1, MACH_COP_0_TLB_LO1 # load PTE entry + nop + tlbwr # write TLB + nop + nop + nop + nop + nop + eret + +sys_stk_chk: + subu k0, sp, UADDR + 0x200 # check to see if we have a + sltiu k0, UPAGES*NBPG - 0x200 # valid kernel stack + bne k0, zero, mips_r4000_KernGenException # Go panic + nop + + la a0, start - START_FRAME - 8 # set sp to a valid place + sw sp, 24(a0) + move sp, a0 + la a0, 1f + mfc0 a2, MACH_COP_0_STATUS_REG + mfc0 a3, MACH_COP_0_CAUSE_REG + dmfc0 a1, MACH_COP_0_EXC_PC + sw a2, 16(sp) + sw a3, 20(sp) + move a2, ra + jal printf + dmfc0 a3, MACH_COP_0_BAD_VADDR + .data +1: + .asciiz "ktlbmiss: PC %x RA %x ADR %x\nSR %x CR %x SP %x\n" + .text + + la sp, start - START_FRAME # set sp to a valid place + PANIC("kernel stack overflow") + .set at +END(mips_r4000_TLBMissException) + + +/*-------------------------------------------------------------------------- + * + * mips_r4000_TLBWriteIndexed -- + * + * Write the given entry into the TLB at the given index. + * + * mips_r4000_TLBWriteIndexed(index, tlb) + * unsigned index; + * tlb *tlb; + * + * Results: + * None. + * + * Side effects: + * TLB entry set. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_TLBWriteIndexed) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + nop + lw a2, 8(a1) + lw a3, 12(a1) + dmfc0 t0, MACH_COP_0_TLB_HI # Save the current PID. + + dmtc0 a2, MACH_COP_0_TLB_LO0 # Set up entry low0. + dmtc0 a3, MACH_COP_0_TLB_LO1 # Set up entry low1. + lw a2, 0(a1) + lw a3, 4(a1) + mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index. + dmtc0 a2, MACH_COP_0_TLB_PG_MASK # Set up entry mask. + dmtc0 a3, MACH_COP_0_TLB_HI # Set up entry high. + nop + tlbwi # Write the TLB + nop + nop + nop # Delay for effect + nop + + dmtc0 t0, MACH_COP_0_TLB_HI # Restore the PID. + nop + dmtc0 zero, MACH_COP_0_TLB_PG_MASK # Default mask value. + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r4000_TLBWriteIndexed) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_SetPID -- + * + * Write the given pid into the TLB pid reg. + * + * mips_r4000_SetPID(pid) + * int pid; + * + * Results: + * None. + * + * Side effects: + * PID set in the entry hi register. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_SetPID) + dmtc0 a0, MACH_COP_0_TLB_HI # Write the hi reg value + j ra + nop +END(mips_r4000_SetPID) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_SetWIRED -- + * + * Write the given value into the TLB wired reg. + * + * mips_r4000_SetPID(wired) + * int wired; + * + * Results: + * None. + * + * Side effects: + * WIRED set in the wired register. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_SetWIRED) + mtc0 a0, MACH_COP_0_TLB_WIRED + j ra + nop +END(mips_r4000_SetWIRED) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_GetWIRED -- + * + * Get the value from the TLB wired reg. + * + * mips_r4000_GetWIRED(void) + * + * Results: + * Value of wired reg. + * + * Side effects: + * None. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_GetWIRED) + mfc0 v0, MACH_COP_0_TLB_WIRED + j ra + nop +END(mips_r4000_GetWIRED) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_TLBFlush -- + * + * Flush the "random" entries from the TLB. + * Uses "wired" register to determine what register to start with. + * + * mips_r4000_TLBFlush() + * + * Results: + * None. + * + * Side effects: + * The TLB is flushed. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_TLBFlush) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 t1, MACH_COP_0_TLB_WIRED + li t2, VMMACH_NUM_TLB_ENTRIES + li v0, MACH_CACHED_MEMORY_ADDR # invalid address + dmfc0 t0, MACH_COP_0_TLB_HI # Save the PID + + dmtc0 v0, MACH_COP_0_TLB_HI # Mark entry high as invalid + dmtc0 zero, MACH_COP_0_TLB_LO0 # Zero out low entry0. + dmtc0 zero, MACH_COP_0_TLB_LO1 # Zero out low entry1. + mtc0 zero, MACH_COP_0_TLB_PG_MASK # Zero out mask entry. +/* + * Align the starting value (t1) and the upper bound (t2). + */ +1: + mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register. + addu t1, t1, 1 # Increment index. + tlbwi # Write the TLB entry. + nop + nop + bne t1, t2, 1b + nop + + dmtc0 t0, MACH_COP_0_TLB_HI # Restore the PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r4000_TLBFlush) + + +/*-------------------------------------------------------------------------- + * + * mips_r4000_TLBFlushAddr -- + * + * Flush any TLB entries for the given address and TLB PID. + * + * mips_r4000_TLBFlushAddr(TLBhi) + * unsigned TLBhi; + * + * Results: + * None. + * + * Side effects: + * The process's page is flushed from the TLB. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_TLBFlushAddr) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + nop + li v0, (PG_HVPN | PG_ASID) + and a0, a0, v0 # Make shure valid hi value. + dmfc0 t0, MACH_COP_0_TLB_HI # Get current PID + dmtc0 a0, MACH_COP_0_TLB_HI # look for addr & PID + nop + nop + nop + tlbp # Probe for the entry. + nop + nop # Delay for effect + nop + mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got + li t1, MACH_CACHED_MEMORY_ADDR # Load invalid entry. + bltz v0, 1f # index < 0 => !found + nop + dmtc0 t1, MACH_COP_0_TLB_HI # Mark entry high as invalid + + dmtc0 zero, MACH_COP_0_TLB_LO0 # Zero out low entry. + dmtc0 zero, MACH_COP_0_TLB_LO1 # Zero out low entry. + nop + tlbwi + nop + nop + nop + nop +1: + dmtc0 t0, MACH_COP_0_TLB_HI # restore PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r4000_TLBFlushAddr) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_TLBUpdate -- + * + * Update the TLB if highreg is found; otherwise, enter the data. + * + * mips_r4000_TLBUpdate(virpageadr, lowregx) + * unsigned virpageadr, lowregx; + * + * Results: + * < 0 if loaded >= 0 if updated. + * + * Side effects: + * None. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_TLBUpdate) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + and t1, a0, 0x1000 # t1 = Even/Odd flag + li v0, (PG_HVPN | PG_ASID) + and a0, a0, v0 + dmfc0 t0, MACH_COP_0_TLB_HI # Save current PID + dmtc0 a0, MACH_COP_0_TLB_HI # Init high reg + and a2, a1, PG_G # Copy global bit + nop + nop + tlbp # Probe for the entry. + dsll a1, a1, 34 + dsrl a1, a1, 34 + bne t1, zero, 2f # Decide even odd + mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got +# EVEN + nop + bltz v0, 1f # index < 0 => !found + nop + + tlbr # update, read entry first + nop + nop + nop + dmtc0 a1, MACH_COP_0_TLB_LO0 # init low reg0. + nop + tlbwi # update slot found + b 4f + nop +1: + mtc0 zero, MACH_COP_0_TLB_PG_MASK # init mask. + dmtc0 a0, MACH_COP_0_TLB_HI # init high reg. + dmtc0 a1, MACH_COP_0_TLB_LO0 # init low reg0. + dmtc0 a2, MACH_COP_0_TLB_LO1 # init low reg1. + nop + tlbwr # enter into a random slot + b 4f + nop +# ODD +2: + nop + bltz v0, 3f # index < 0 => !found + nop + + tlbr # read the entry first + nop + nop + nop + dmtc0 a1, MACH_COP_0_TLB_LO1 # init low reg1. + nop + tlbwi # update slot found + b 4f + nop +3: + mtc0 zero, MACH_COP_0_TLB_PG_MASK # init mask. + dmtc0 a0, MACH_COP_0_TLB_HI # init high reg. + dmtc0 a2, MACH_COP_0_TLB_LO0 # init low reg0. + dmtc0 a1, MACH_COP_0_TLB_LO1 # init low reg1. + nop + tlbwr # enter into a random slot + +4: # Make shure pipeline + nop # advances before we + nop # uses the tlb. + nop + nop + dmtc0 t0, MACH_COP_0_TLB_HI # restore PID + j ra + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register +END(mips_r4000_TLBUpdate) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_TLBRead -- + * + * Read the TLB entry. + * + * mips_r4000_TLBRead(entry, tlb) + * unsigned entry; + * struct tlb *tlb; + * + * Results: + * None. + * + * Side effects: + * tlb will contain the TLB entry found. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_TLBRead) + mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. + mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + nop + nop + nop + dmfc0 t0, MACH_COP_0_TLB_HI # Get current PID + + mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index register + nop + tlbr # Read from the TLB + nop + nop + nop + mfc0 t2, MACH_COP_0_TLB_PG_MASK # fetch the hi entry + dmfc0 t3, MACH_COP_0_TLB_HI # fetch the hi entry + dmfc0 t4, MACH_COP_0_TLB_LO0 # See what we got + dmfc0 t5, MACH_COP_0_TLB_LO1 # See what we got + dmtc0 t0, MACH_COP_0_TLB_HI # restore PID + nop + nop + nop # wait for PID active + mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register + sw t2, 0(a1) + sw t3, 4(a1) + sw t4, 8(a1) + j ra + sw t5, 12(a1) +END(mips_r4000_TLBRead) + +/*-------------------------------------------------------------------------- + * + * mips_r4000_TLBGetPID -- + * + * mips_r4000_TLBGetPID() + * + * Results: + * Returns the current TLB pid reg. + * + * Side effects: + * None. + * + *-------------------------------------------------------------------------- + */ +LEAF(mips_r4000_TLBGetPID) + dmfc0 v0, MACH_COP_0_TLB_HI # get PID + j ra + and v0, v0, VMMACH_TLB_PID # mask off PID +END(mips_r4000_TLBGetPID) + + + +/*---------------------------------------------------------------------------- + * + * R4000 cache sizing and flushing code. + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * + * mips_r4000_ConfigCache -- + * + * Size the caches. + * NOTE: should only be called from mach_init(). + * + * Results: + * None. + * + * Side effects: + * The size of the data cache is stored into machPrimaryDataCacheSize. + * The size of instruction cache is stored into machPrimaryInstCacheSize. + * Alignment mask for cache aliasing test is stored in machCacheAliasMask. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r4000_ConfigCache) + mfc0 v0, MACH_COP_0_CONFIG # Get configuration register + nop + srl t1, v0, 9 # Get I cache size. + and t1, 3 + li t2, 4096 + sllv t2, t2, t1 + sw t2, machPrimaryDataCacheSize + addiu t2, -1 + and t2, ~(NBPG - 1) + sw t2, machCacheAliasMask + + and t2, v0, 0x20 + srl t2, t2, 1 + addu t2, t2, 16 + sw t2, machPrimaryDataCacheLSize + + srl t1, v0, 6 # Get I cache size. + and t1, 3 + li t2, 4096 + sllv t2, t2, t1 + sw t2, machPrimaryInstCacheSize + + and t2, v0, 0x10 + addu t2, t2, 16 + sw t2, machPrimaryInstCacheLSize + j ra + nop +END(mips_r4000_ConfigCache) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_FlushCache -- + * + * Flush the caches. Assumes a line size of 16 bytes for speed. + * + * Results: + * None. + * + * Side effects: + * The contents of the caches is flushed. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r4000_FlushCache) + lw t1, machPrimaryInstCacheSize + lw t2, machPrimaryDataCacheSize + # lw t3, machPrimaryInstCacheLSize + # lw t4, machPrimaryDataCacheLSize +/* + * Flush the instruction cache. + */ + li t0, MACH_CACHED_MEMORY_ADDR + addu t1, t0, t1 # End address + subu t1, t1, 128 +1: + cache 0, 0(t0) + cache 0, 16(t0) + cache 0, 32(t0) + cache 0, 48(t0) + cache 0, 64(t0) + cache 0, 80(t0) + cache 0, 96(t0) + cache 0, 112(t0) + bne t0, t1, 1b + addu t0, t0, 128 + +/* + * Flush the data cache. + */ + li t0, MACH_CACHED_MEMORY_ADDR + addu t1, t0, t2 # End address + subu t1, t1, 128 +1: + cache 1, 0(t0) + cache 1, 16(t0) + cache 1, 32(t0) + cache 1, 48(t0) + cache 1, 64(t0) + cache 1, 80(t0) + cache 1, 96(t0) + cache 1, 112(t0) + bne t0, t1, 1b + addu t0, t0, 128 + + j ra + nop +END(mips_r4000_FlushCache) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_FlushICache -- + * + * void mips_r4000_FlushICache(addr, len) + * vm_offset_t addr, len; + * + * Flush instruction cache for range of addr to addr + len - 1. + * The address can be any valid address so long as no TLB misses occur. + * Assumes a cache line size of 16 bytes for speed. + * + * Results: + * None. + * + * Side effects: + * The contents of the cache is flushed. + * Must not touch v0. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r4000_FlushICache) + addu a1, 127 # Align + srl a1, a1, 7 # Number of unrolled loops +1: + cache 0, 0(a0) + cache 0, 16(a0) + cache 0, 32(a0) + cache 0, 48(a0) + cache 0, 64(a0) + cache 0, 80(a0) + cache 0, 96(a0) + cache 0, 112(a0) + addu a1, -1 + bne a1, zero, 1b + addu a0, 128 + + j ra + nop +END(mips_r4000_FlushICache) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_FlushDCache -- + * + * void mips_r4000_FlushDCache(addr, len) + * vm_offset_t addr, len; + * + * Flush data cache for index range of addr to addr + len - 1. + * The address is reduced to a kseg0 index. + * + * Results: + * None. + * + * Side effects: + * The contents of the cache is written back to primary memory. + * The cache line is invalidated. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r4000_FlushDCache) + lw a2, machPrimaryDataCacheSize + addiu a2, -1 + and a0, a0, a2 + addu a1, 127 # Align + li a2, 0x80000000 + addu a0, a0, a2 + addu a1, a1, a0 + and a0, a0, -128 + subu a1, a1, a0 + srl a1, a1, 7 # Compute number of cache lines +1: + cache 1, 0(a0) + cache 1, 16(a0) + cache 1, 32(a0) + cache 1, 48(a0) + cache 1, 64(a0) + cache 1, 80(a0) + cache 1, 96(a0) + cache 1, 112(a0) + addu a1, -1 + bne a1, zero, 1b + addu a0, 128 + + j ra + nop +END(mips_r4000_FlushDCache) + +/*---------------------------------------------------------------------------- + * + * mips_r4000_HitFlushDCache -- + * + * void mips_r4000_HitFlushDCache(addr, len) + * vm_offset_t addr, len; + * + * Flush data cache for range of addr to addr + len - 1. + * The address can be any valid viritual address as long + * as no TLB invalid traps occur. Only lines with matching + * addr is flushed. + * + * Results: + * None. + * + * Side effects: + * The contents of the cache is written back to primary memory. + * The cache line is invalidated. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r4000_HitFlushDCache) + beq a1, zero, 2f + addu a1, 127 # Align + addu a1, a1, a0 + and a0, a0, -128 + subu a1, a1, a0 + srl a1, a1, 7 # Compute number of cache lines +1: + cache 0x15, 0(a0) + cache 0x15, 16(a0) + cache 0x15, 32(a0) + cache 0x15, 48(a0) + cache 0x15, 64(a0) + cache 0x15, 80(a0) + cache 0x15, 96(a0) + cache 0x15, 112(a0) + addu a1, -1 + bne a1, zero, 1b + addu a0, 128 + +2: + j ra + nop +END(mips_r4000_HitFlushDCache) +/*---------------------------------------------------------------------------- + * + * mips_r4000_InvalidateDCache -- + * + * void mips_r4000_FlushDCache(addr, len) + * vm_offset_t addr, len; + * + * Flush data cache for range of addr to addr + len - 1. + * The address can be any valid address as long as no TLB misses occur. + * (Be sure to use cached K0SEG kernel addresses or mapped addresses) + * Results: + * None. + * + * Side effects: + * The cache line is invalidated. + * + *---------------------------------------------------------------------------- + */ +LEAF(mips_r4000_InvalidateDCache) + addu a1, a1, a0 # compute ending address +1: + addu a0, a0, 4 + bne a0, a1, 1b + cache 0x11,-4(a0) + + j ra + nop +END(mips_r4000_InvalidateDCache) + +/*---------------------------------------------------------------------------- + * + * XXX END of r4000-specific code XXX + * + *---------------------------------------------------------------------------- + */ diff --git a/sys/arch/pmax/pmax/machdep.c b/sys/arch/pmax/pmax/machdep.c index 9b1c110e50d..e930352d1b1 100644 --- a/sys/arch/pmax/pmax/machdep.c +++ b/sys/arch/pmax/pmax/machdep.c @@ -97,7 +97,7 @@ #include <pmax/pmax/cons.h> -#include <mips/mips/mips_machdep.c> /* XXX */ +#include <pmax/pmax/mips_machdep.c> /* XXX */ #include "pm.h" diff --git a/sys/arch/pmax/pmax/mem.c b/sys/arch/pmax/pmax/mem.c new file mode 100644 index 00000000000..c1d99888c86 --- /dev/null +++ b/sys/arch/pmax/pmax/mem.c @@ -0,0 +1,171 @@ +/* $NetBSD: mem.c,v 1.7 1995/09/29 21:53:29 jonathan Exp $ */ + +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1982, 1986, 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)mem.c 8.3 (Berkeley) 1/12/94 + */ + +/* + * Memory special file + */ + +#include <sys/param.h> +#include <sys/conf.h> +#include <sys/buf.h> +#include <sys/systm.h> +#include <sys/uio.h> +#include <sys/malloc.h> +#include <sys/msgbuf.h> + +#include <machine/cpu.h> + +#include <vm/vm.h> + +extern vm_offset_t avail_end; +caddr_t zeropage; + +/*ARGSUSED*/ +int +mmopen(dev, flag, mode) + dev_t dev; + int flag, mode; +{ + + return (0); +} + +/*ARGSUSED*/ +int +mmclose(dev, flag, mode) + dev_t dev; + int flag, mode; +{ + + return (0); +} + +/*ARGSUSED*/ +int +mmrw(dev, uio, flags) + dev_t dev; + struct uio *uio; + int flags; +{ + register vm_offset_t o, v; + register int c; + register struct iovec *iov; + int error = 0; + + while (uio->uio_resid > 0 && error == 0) { + iov = uio->uio_iov; + if (iov->iov_len == 0) { + uio->uio_iov++; + uio->uio_iovcnt--; + if (uio->uio_iovcnt < 0) + panic("mmrw"); + continue; + } + switch (minor(dev)) { + +/* minor device 0 is physical memory */ + case 0: + v = uio->uio_offset; + c = iov->iov_len; + if (v + c > ctob(physmem)) + return (EFAULT); + v += MACH_CACHED_MEMORY_ADDR; + error = uiomove((caddr_t)v, c, uio); + continue; + +/* minor device 1 is kernel memory */ + case 1: + v = uio->uio_offset; + c = min(iov->iov_len, MAXPHYS); + if (v < MACH_CACHED_MEMORY_ADDR) + return (EFAULT); + if (v + c > MACH_PHYS_TO_CACHED(avail_end + + sizeof (struct msgbuf)) && + (v < MACH_KSEG2_ADDR || + !kernacc((caddr_t)v, c, + uio->uio_rw == UIO_READ ? B_READ : B_WRITE))) + return (EFAULT); + error = uiomove((caddr_t)v, c, uio); + continue; + +/* minor device 2 is EOF/RATHOLE */ + case 2: + if (uio->uio_rw == UIO_WRITE) + uio->uio_resid = 0; + return (0); + +/* minor device 12 (/dev/zero) is source of nulls on read, rathole on write */ + case 12: + if (uio->uio_rw == UIO_WRITE) { + c = iov->iov_len; + break; + } + if (zeropage == NULL) { + zeropage = (caddr_t) + malloc(CLBYTES, M_TEMP, M_WAITOK); + bzero(zeropage, CLBYTES); + } + c = min(iov->iov_len, CLBYTES); + error = uiomove(zeropage, c, uio); + continue; + + default: + return (ENXIO); + } + if (error) + break; + iov->iov_base += c; + iov->iov_len -= c; + uio->uio_offset += c; + uio->uio_resid -= c; + } + return (error); +} + +int +mmmmap(dev, off, prot) + dev_t dev; + int off, prot; +{ + + return (EOPNOTSUPP); +} diff --git a/sys/arch/pmax/pmax/mips_machdep.c b/sys/arch/pmax/pmax/mips_machdep.c new file mode 100644 index 00000000000..d54751b7ffa --- /dev/null +++ b/sys/arch/pmax/pmax/mips_machdep.c @@ -0,0 +1,326 @@ +/* $NetBSD: mips_machdep.c,v 1.1 1996/05/19 00:31:57 jonathan Exp $ */ + +/* + * Copyright 1996 The Board of Trustees of The Leland Stanford + * Junior University. All Rights Reserved. + * + * Permission to use, copy, modify, and distribute this + * software and its documentation for any purpose and without + * fee is hereby granted, provided that the above copyright + * notice appear in all copies. Stanford University + * makes no representations about the suitability of this + * software for any purpose. It is provided "as is" without + * express or implied warranty. + */ + +#include <pmax/cpu.h> /* declaration of of cpu_id */ +#include <machine/locore.h> + +mips_locore_jumpvec_t mips_locore_jumpvec = { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL +}; + + +/* + * MIPS-I (r2000) locore-function vector. + */ +mips_locore_jumpvec_t R2000_locore_vec = +{ + mips_r2000_ConfigCache, + mips_r2000_FlushCache, + mips_r2000_FlushDCache, + mips_r2000_FlushICache, + /*mips_r2000_FlushICache*/ mips_r2000_FlushCache, + mips_r2000_SetPID, + mips_r2000_TLBFlush, + mips_r2000_TLBFlushAddr, + mips_r2000_TLBUpdate, + mips_r2000_TLBWriteIndexed +}; + +#ifdef CPU_R4000 +/* + * MIPS-III (r4000) locore-function vector. + */ +mips_locore_jumpvec_t R4000_locore_vec = +{ + mips_r4000_ConfigCache, + mips_r4000_FlushCache, + mips_r4000_FlushDCache, + mips_r4000_FlushICache, + mips_r4000_ForceCacheUpdate, + mips_r4000_SetPID, + mips_r4000_TLBFlush, + mips_r4000_TLBFlushAddr, + mips_r4000_TLBUpdate, + mips_r4000_TLBWriteIndexed +}; +#endif /* CPU_R4000 */ + + +/* + * Do all the stuff that locore normally does before calling main(), + * that is common to all mips-CPU NetBSD ports. + * + * The principal purpose of this function is to examine the + * variable cpu_id, into which the kernel locore start code + * writes the cpu ID register, and to then copy appropriate + * cod into the CPU exception-vector entries and the jump tables + * used to hide the differences in cache and TLB handling in + * different MIPS CPUs. + * + * This should be the very first thing called by each port's + * init_main() function. + */ + +void +r2000_vector_init() +{ + extern char MachUTLBMiss[], MachUTLBMissEnd[]; + extern char mips_R2000_exception[], mips_R2000_exceptionEnd[]; + + /* + * Copy down exception vector code. + */ + if (MachUTLBMissEnd - MachUTLBMiss > 0x80) + panic("startup: UTLB code too large"); + bcopy(MachUTLBMiss, (char *)MACH_UTLB_MISS_EXC_VEC, + MachUTLBMissEnd - MachUTLBMiss); + bcopy(mips_R2000_exception, (char *)MACH_GEN_EXC_VEC, + mips_R2000_exceptionEnd - mips_R2000_exception); + + /* + * Copy locore-function vector. + */ + bcopy(&R2000_locore_vec, &mips_locore_jumpvec, + sizeof(mips_locore_jumpvec_t)); + + /* + * Clear out the I and D caches. + */ + mips_r2000_ConfigCache(); + mips_r2000_FlushCache(); +} + + +#ifdef CPU_R4000 +void +r4000_vector_init() +{ + + extern char MachUTLBMiss[], MachUTLBMissEnd[]; + extern char mips_R4000_exception[], mips_R4000_exceptionEnd[]; + + /* + * Copy down exception vector code. + */ + if (MachUTLBMissEnd - MachUTLBMiss > 0x80) + panic("startup: UTLB code too large"); + bcopy(MachUTLBMiss, (char *)MACH_UTLB_MISS_EXC_VEC, + MachUTLBMissEnd - MachUTLBMiss); + + bcopy(mips_r4000_exception, (char *)MACH_GEN_EXC_VEC, + mips_r4000_exceptionEnd - mips_r4000_exception); + + /* + * Copy locore-function vector. + */ + bcopy(&R4000_locore_vec, &mips_locore_jumpvec, + sizeof(mips_locore_jumpvec_t)); + + /* + * Clear out the I and D caches. + */ + mips_r4000_ConfigCache(); + mips_r4000_FlushCache(); +} +#endif + +/* + * Initialize the hardware exception vectors, and the jump table used to + * call locore cache and TLB management functions, based on the kind + * of CPU the kernel is running on. + */ +void +mips_vector_init() +{ + register caddr_t v; + extern char edata[], end[]; + + /* clear the BSS segment */ + v = (caddr_t)mips_round_page(end); + bzero(edata, v - edata); + + /* Work out what kind of CPU and FPU are present. */ + switch(cpu_id.cpu.cp_imp) { + + case MIPS_R2000: + case MIPS_R3000: + r2000_vector_init(); + break; + +#ifdef CPU_R4000 + case MIPS_R4000: + r4000_vector_init(); + break; +#endif CPU_R4000 + + default: + panic("Unconfigured or unsupported MIPS cpu\n"); + + } +} + + +/* + * Identify cpu and fpu type and revision. + * + * XXX Should be moved to mips_cpu.c but that doesn't exist + */ +void +cpu_identify() +{ + + + /* Work out what kind of CPU and FPU are present. */ + + switch(cpu_id.cpu.cp_imp) { + + case MIPS_R2000: + printf("MIPS R2000 CPU"); + break; + case MIPS_R3000: + + /* + * XXX + * R2000A silicion has an r3000 core and shows up here. + * The caller should indicate that by setting a flag + * indicating the baseboard is socketed for an r2000. + * Needs more thought. + */ +#ifdef notyet + if (SYSTEM_HAS_R2000_CPU_SOCKET()) + printf("MIPS R2000A CPU"); + else +#endif + printf("MIPS R3000 CPU"); + break; + case MIPS_R6000: + printf("MIPS R6000 CPU"); + break; + + case MIPS_R4000: +#ifdef pica /* XXX*/ + if(machPrimaryInstCacheSize == 16384) + printf("MIPS R4400 CPU"); + else +#endif /* XXX*/ + printf("MIPS R4000 CPU"); + break; + case MIPS_R3LSI: + printf("LSI Logic R3000 derivate"); + break; + case MIPS_R6000A: + printf("MIPS R6000A CPU"); + break; + case MIPS_R3IDT: + printf("IDT R3000 derivate"); + break; + case MIPS_R10000: + printf("MIPS R10000/T5 CPU"); + break; + case MIPS_R4200: + printf("MIPS R4200 CPU (ICE)"); + break; + case MIPS_R8000: + printf("MIPS R8000 Blackbird/TFP CPU"); + break; + case MIPS_R4600: + printf("QED R4600 Orion CPU"); + break; + case MIPS_R3SONY: + printf("Sony R3000 based CPU"); + break; + case MIPS_R3TOSH: + printf("Toshiba R3000 based CPU"); + break; + case MIPS_R3NKK: + printf("NKK R3000 based CPU"); + break; + case MIPS_UNKC1: + case MIPS_UNKC2: + default: + printf("Unknown CPU type (0x%x)",cpu_id.cpu.cp_imp); + break; + } + printf(" Rev. %d.%d with ", cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev); + + + switch(fpu_id.cpu.cp_imp) { + + case MIPS_SOFT: + printf("Software emulation float"); + break; + case MIPS_R2360: + printf("MIPS R2360 FPC"); + break; + case MIPS_R2010: + printf("MIPS R2010 FPC"); + break; + case MIPS_R3010: + /* + * XXX FPUs for R2000A(?) silicion has an r3010 core and + * shows up here. + */ +#ifdef notyet + if (SYSTEM_HAS_R2000_CPU_SOCKET()) + printf("MIPS R2010A CPU"); + else +#endif + printf("MIPS R3010 FPC"); + break; + case MIPS_R6010: + printf("MIPS R6010 FPC"); + break; + case MIPS_R4010: + printf("MIPS R4010 FPC"); + break; + case MIPS_R31LSI: + printf("FPC"); + break; + case MIPS_R10010: + printf("MIPS R10000/T5 FPU"); + break; + case MIPS_R4210: + printf("MIPS R4200 FPC (ICE)"); + case MIPS_R8000: + printf("MIPS R8000 Blackbird/TFP"); + break; + case MIPS_R4600: + printf("QED R4600 Orion FPC"); + break; + case MIPS_R3SONY: + printf("Sony R3000 based FPC"); + break; + case MIPS_R3TOSH: + printf("Toshiba R3000 based FPC"); + break; + case MIPS_R3NKK: + printf("NKK R3000 based FPC"); + break; + case MIPS_UNKF1: + default: + printf("Unknown FPU type (0x%x)", fpu_id.cpu.cp_imp); + break; + } + printf(" Rev. %d.%d", fpu_id.cpu.cp_majrev, fpu_id.cpu.cp_minrev); + printf("\n"); + +#ifdef pica + printf(" Primary cache size: %dkb Instruction, %dkb Data.\n", + machPrimaryInstCacheSize / 1024, + machPrimaryDataCacheSize / 1024); +#endif +} diff --git a/sys/arch/pmax/pmax/pmap.c b/sys/arch/pmax/pmax/pmap.c index b3b2b632144..4fdbf20e843 100644 --- a/sys/arch/pmax/pmax/pmap.c +++ b/sys/arch/pmax/pmax/pmap.c @@ -79,7 +79,7 @@ #include <vm/vm_page.h> #include <vm/vm_pageout.h> -#include <mips/cpuregs.h> +#include <pmax/cpuregs.h> #include <machine/locore.h> #include <machine/pte.h> diff --git a/sys/arch/pmax/pmax/process_machdep.c b/sys/arch/pmax/pmax/process_machdep.c new file mode 100644 index 00000000000..ef3ba42520a --- /dev/null +++ b/sys/arch/pmax/pmax/process_machdep.c @@ -0,0 +1,119 @@ +/* $NetBSD: process_machdep.c,v 1.5 1996/03/20 01:30:49 jonathan Exp $ */ + +/* + * Copyright (c) 1994 Adam Glass + * Copyright (c) 1993 The Regents of the University of California. + * Copyright (c) 1993 Jan-Simon Pendry + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Jan-Simon Pendry. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: + * Id: procfs_i386.c,v 4.1 1993/12/17 10:47:45 jsp Rel + */ + +/* + * This file may seem a bit stylized, but that so that it's easier to port. + * Functions to be implemented here are: + * + * process_read_regs(proc, regs) + * Get the current user-visible register set from the process + * and copy it into the regs structure (<machine/reg.h>). + * The process is stopped at the time read_regs is called. + * + * process_write_regs(proc, regs) + * Update the current register set from the passed in regs + * structure. Take care to avoid clobbering special CPU + * registers or privileged bits in the PSL. + * The process is stopped at the time write_regs is called. + * + * process_sstep(proc) + * Arrange for the process to trap after executing a single instruction. + * + * process_set_pc(proc) + * Set the process's program counter. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/time.h> +#include <sys/kernel.h> +#include <sys/proc.h> +#include <sys/user.h> +#include <sys/vnode.h> +#include <sys/ptrace.h> +#include <machine/psl.h> +#include <machine/reg.h> + + +int +process_read_regs(p, regs) + struct proc *p; + struct reg *regs; +{ + bcopy(p->p_md.md_regs, (caddr_t)regs, sizeof(struct reg)); + return (0); +} + +int +process_write_regs(p, regs) + struct proc *p; + struct reg *regs; +{ + bcopy((caddr_t)regs, p->p_md.md_regs, sizeof(struct reg)); + /* + * XXX: is it safe to let users set system coprocessor regs? + * XXX: Clear to user set bits!! + */ + /*p->p_md.md_tf->tf_psr = psr | (regs->r_psr & PSR_ICC);*/ + return (0); +} + +int +process_sstep(p, sstep) + struct proc *p; +{ + /* XXX correct semantics: sstep once or forevermore? */ + if(sstep) + cpu_singlestep(p); + return (0); +} + +int +process_set_pc(p, addr) + struct proc *p; + caddr_t addr; +{ + p->p_md.md_regs[PC] = (int)addr; + return (0); +} + |