Make SoC version available in a simple form.

2 files changed, 30 insertions, 17 deletions

diff --git a/sys/arch/octeon/include/autoconf.h b/sys/arch/octeon/include/autoconf.h
index 9505ac2bc97..63919f2770a 100644
--- a/sys/arch/octeon/include/autoconf.h
+++ b/sys/arch/octeon/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.h,v 1.1 2010/09/20 06:32:30 syuu Exp $ */
+/*	$OpenBSD: autoconf.h,v 1.2 2017/04/07 13:30:43 visa Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -45,4 +45,10 @@ extern enum devclass bootdev_class;
 
 #include <mips64/autoconf.h>
 
+extern unsigned int octeon_ver;
+#define OCTEON_1	0
+#define OCTEON_PLUS	1
+#define OCTEON_2	2
+#define OCTEON_3	3
+
 #endif /* _MACHINE_AUTOCONF_H_ */
diff --git a/sys/arch/octeon/octeon/machdep.c b/sys/arch/octeon/octeon/machdep.c
index 611437d2c49..2588e1711b7 100644
--- a/sys/arch/octeon/octeon/machdep.c
+++ b/sys/arch/octeon/octeon/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.83 2017/04/02 15:48:19 visa Exp $ */
+/*	$OpenBSD: machdep.c,v 1.84 2017/04/07 13:30:43 visa Exp $ */
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -99,7 +99,8 @@ vm_map_t phys_map;
 struct boot_desc *octeon_boot_desc;
 struct boot_info *octeon_boot_info;
 
-void *octeon_fdt;
+void		*octeon_fdt;
+unsigned int	 octeon_ver;
 
 char uboot_rootdev[OCTEON_ARGV_MAX];
 
@@ -276,6 +277,21 @@ mips_init(__register_t a0, __register_t a1, __register_t a2 __unused,
 
 	bootcpu_hwinfo.clock = boot_desc->eclock;
 
+	switch ((prid >> 8) & 0xff) {
+	default:
+		octeon_ver = OCTEON_1;
+		break;
+	case MIPS_CN50XX:
+		octeon_ver = OCTEON_PLUS;
+		break;
+	case MIPS_CN61XX:
+		octeon_ver = OCTEON_2;
+		break;
+	case MIPS_CN71XX:
+		octeon_ver = OCTEON_3;
+		break;
+	}
+
 	/*
 	 * Look at arguments passed to us and compute boothowto.
 	 */
@@ -584,15 +600,13 @@ octeon_ioclock_speed(void)
 {
 	extern struct boot_info *octeon_boot_info;
 	u_int64_t mio_rst_boot, rst_boot;
-	int chipid;
 
-	chipid = octeon_get_chipid();
-	switch (octeon_model_family(chipid)) {
-	case OCTEON_MODEL_FAMILY_CN61XX:
+	switch (octeon_ver) {
+	case OCTEON_2:
 		mio_rst_boot = octeon_xkphys_read_8(MIO_RST_BOOT);
 		return OCTEON_IO_REF_CLOCK * ((mio_rst_boot >>
 		    MIO_RST_BOOT_PNR_MUL_SHIFT) & MIO_RST_BOOT_PNR_MUL_MASK);
-	case OCTEON_MODEL_FAMILY_CN71XX:
+	case OCTEON_3:
 		rst_boot = octeon_xkphys_read_8(RST_BOOT);
 		return OCTEON_IO_REF_CLOCK * ((rst_boot >>
 		    RST_BOOT_PNR_MUL_SHIFT) & RST_BOOT_PNR_MUL_MASK);
@@ -687,8 +701,6 @@ int	waittime = -1;
 __dead void
 boot(int howto)
 {
-	int chipid;
-
 	if (curproc)
 		savectx(curproc->p_addr, 0);
 
@@ -733,16 +745,11 @@ haltsys:
 		tlb_set_wired(0);
 		tlb_flush(bootcpu_hwinfo.tlbsize);
 
-		chipid = octeon_get_chipid();
-		switch (octeon_model_family(chipid)) {
-		case OCTEON_MODEL_FAMILY_CN71XX:
+		if (octeon_ver == OCTEON_3)
 			octeon_xkphys_write_8(RST_SOFT_RST, 1);
-			break;
-		default:
+		else
 			octeon_xkphys_write_8(OCTEON_CIU_BASE +
 			    CIU_SOFT_RST, 1);
-			break;
-		}
 	}
 
 	for (;;)