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authorMiod Vallat <miod@cvs.openbsd.org>2002-06-08 15:45:33 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2002-06-08 15:45:33 +0000
commit21bce0b3873e59c1f9e8e097e28aa4b985e339c3 (patch)
tree0af6292bf552c6bd5409934f3ae98c0d76fde45e /sys
parentc724abb001fe7546a8883a4bf611667176e9e64b (diff)
Factorize common parts (cache-related stuff).
ok drahn@
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/macppc/include/cpu.h28
-rw-r--r--sys/arch/mvmeppc/include/cpu.h45
-rw-r--r--sys/arch/powerpc/include/cpu.h45
3 files changed, 50 insertions, 68 deletions
diff --git a/sys/arch/macppc/include/cpu.h b/sys/arch/macppc/include/cpu.h
index f535ea93285..1b639da885d 100644
--- a/sys/arch/macppc/include/cpu.h
+++ b/sys/arch/macppc/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.4 2002/02/23 16:59:36 matthieu Exp $ */
+/* $OpenBSD: cpu.h,v 1.5 2002/06/08 15:45:29 miod Exp $ */
/* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */
/*
@@ -36,39 +36,15 @@
#include <powerpc/cpu.h>
-#define CACHELINESIZE 32 /* For now XXX */
-
-static __inline void
-syncicache(void *from, int len)
-{
- int l;
- char *p = from;
- len = len + (((u_int32_t) from) & (CACHELINESIZE-1));
- l = len;
-
- do {
- __asm__ __volatile__ ("dcbst 0,%0" :: "r"(p));
- p += CACHELINESIZE;
- } while ((l -= CACHELINESIZE) > 0);
- __asm__ __volatile__ ("sync");
- p = from;
- l = len;
- do {
- __asm__ __volatile__ ("icbi 0,%0" :: "r"(p));
- p += CACHELINESIZE;
- } while ((l -= CACHELINESIZE) > 0);
- __asm__ __volatile__ ("isync");
-}
-
/*
* CTL_MACHDEP definitions.
*/
#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */
#define CPU_MAXID 2 /* number of valid machdep ids */
-
#define CTL_MACHDEP_NAMES { \
{ 0, 0 }, \
{ "allowaperture", CTLTYPE_INT }, \
}
+
#endif /* _MACHINE_CPU_H_ */
diff --git a/sys/arch/mvmeppc/include/cpu.h b/sys/arch/mvmeppc/include/cpu.h
index 71d77072af9..71e8e9a7cb7 100644
--- a/sys/arch/mvmeppc/include/cpu.h
+++ b/sys/arch/mvmeppc/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.4 2002/06/07 01:00:55 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.5 2002/06/08 15:45:31 miod Exp $ */
/* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */
/*
@@ -36,45 +36,8 @@
#include <powerpc/cpu.h>
-#define CACHELINESIZE 32 /* For now XXX */
-
-static __inline void
-syncicache(void *from, int len)
-{
- int l;
- char *p = from;
-
- len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
- l = len;
-
- do {
- __asm__ __volatile__ ("dcbst 0,%0" :: "r"(p));
- p += CACHELINESIZE;
- } while ((l -= CACHELINESIZE) > 0);
- __asm__ __volatile__ ("sync");
- p = from;
- l = len;
- do {
- __asm__ __volatile__ ("icbi 0,%0" :: "r"(p));
- p += CACHELINESIZE;
- } while ((l -= CACHELINESIZE) > 0);
- __asm__ __volatile__ ("isync");
-}
-
-static __inline void
-invdcache(void *from, int len)
-{
- int l;
- char *p = from;
-
- len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
- l = len;
-
- do {
- __asm__ __volatile__ ("dcbi 0,%0" :: "r"(p));
- p += CACHELINESIZE;
- } while ((l -= CACHELINESIZE) > 0);
- __asm__ __volatile__ ("sync");
-}
+u_int32_t ppc_set_msr(u_int32_t);
+u_int32_t ppc_get_msr(void);
+void install_extint(void (*)(void));
#endif /* _MACHINE_CPU_H_ */
diff --git a/sys/arch/powerpc/include/cpu.h b/sys/arch/powerpc/include/cpu.h
index 5fddfb0fc62..826cb409e2e 100644
--- a/sys/arch/powerpc/include/cpu.h
+++ b/sys/arch/powerpc/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.10 2002/06/07 21:33:43 nordin Exp $ */
+/* $OpenBSD: cpu.h,v 1.11 2002/06/08 15:45:32 miod Exp $ */
/* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */
/*
@@ -57,4 +57,47 @@ extern volatile int astpending;
extern char *bootpath;
+#ifndef CACHELINESIZE
+#define CACHELINESIZE 32 /* For now XXX */
+#endif
+
+static __inline void
+syncicache(void *from, int len)
+{
+ int l;
+ char *p = from;
+
+ len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
+ l = len;
+
+ do {
+ __asm__ __volatile__ ("dcbst 0,%0" :: "r"(p));
+ p += CACHELINESIZE;
+ } while ((l -= CACHELINESIZE) > 0);
+ __asm__ __volatile__ ("sync");
+ p = from;
+ l = len;
+ do {
+ __asm__ __volatile__ ("icbi 0,%0" :: "r"(p));
+ p += CACHELINESIZE;
+ } while ((l -= CACHELINESIZE) > 0);
+ __asm__ __volatile__ ("isync");
+}
+
+static __inline void
+invdcache(void *from, int len)
+{
+ int l;
+ char *p = from;
+
+ len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
+ l = len;
+
+ do {
+ __asm__ __volatile__ ("dcbi 0,%0" :: "r"(p));
+ p += CACHELINESIZE;
+ } while ((l -= CACHELINESIZE) > 0);
+ __asm__ __volatile__ ("sync");
+}
+
#endif /* _POWERPC_CPU_H_ */