add Intel 10Gb Ethernet driver with support for LR/SR and CX4 cards.

From: Intel's web-site

ok deraadt@

9 files changed, 5362 insertions, 1 deletions

diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index f03922e14a3..75b96f59ee6 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.189 2005/09/06 02:22:37 krw Exp $
+#	$OpenBSD: files.pci,v 1.190 2005/11/14 23:25:43 brad Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -309,6 +309,13 @@ attach	em at pci
 file	dev/pci/if_em.c			em
 file	dev/pci/if_em_hw.c		em
 
+# Intel Pro/10GbE
+device	ixgb: ether, ifnet, ifmedia
+attach	ixgb at pci
+file	dev/pci/if_ixgb.c		ixgb   
+file	dev/pci/ixgb_ee.c		ixgb
+file	dev/pci/ixgb_hw.c		ixgb
+
 # DEC/Intel 21143 and "tulip" clone ethernet
 attach	dc at pci with dc_pci
 file	dev/pci/if_dc_pci.c		dc_pci
diff --git a/sys/dev/pci/if_ixgb.c b/sys/dev/pci/if_ixgb.c
new file mode 100644
index 00000000000..ef6cfb74ffe
--- /dev/null
+++ b/sys/dev/pci/if_ixgb.c
@@ -0,0 +1,2052 @@
+/**************************************************************************
+
+Copyright (c) 2001-2005, Intel Corporation
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+    contributors may be used to endorse or promote products derived from
+    this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+***************************************************************************/
+
+/* $OpenBSD: if_ixgb.c,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+#include <dev/pci/if_ixgb.h>
+
+/*********************************************************************
+ *  Set this to one to display debug statistics
+ *********************************************************************/
+int             ixgb_display_debug_stats = 0;
+
+/*********************************************************************
+ *  Driver version
+ *********************************************************************/
+
+char ixgb_driver_version[] = "1.0.26";
+
+/*********************************************************************
+ *  PCI Device ID Table
+ *********************************************************************/
+
+const struct pci_matchid ixgb_devices[] = {
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_LR },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_CX4 },
+};
+
+/*********************************************************************
+ *  Function prototypes
+ *********************************************************************/
+int  ixgb_probe(struct device *, void *, void *);
+void ixgb_attach(struct device *, struct device *, void *);
+void ixgb_power(int, void *);
+int  ixgb_intr(void *);
+void ixgb_start(struct ifnet *);
+int  ixgb_ioctl(struct ifnet *, u_long, caddr_t);
+void ixgb_watchdog(struct ifnet *);
+void ixgb_init(void *);
+void ixgb_stop(void *);
+void ixgb_media_status(struct ifnet *, struct ifmediareq *);
+int  ixgb_media_change(struct ifnet *);
+void ixgb_identify_hardware(struct ixgb_softc *);
+int  ixgb_allocate_pci_resources(struct ixgb_softc *);
+void ixgb_free_pci_resources(struct ixgb_softc *);
+void ixgb_local_timer(void *);
+int  ixgb_hardware_init(struct ixgb_softc *);
+void ixgb_setup_interface(struct ixgb_softc *);
+int  ixgb_setup_transmit_structures(struct ixgb_softc *);
+void ixgb_initialize_transmit_unit(struct ixgb_softc *);
+int  ixgb_setup_receive_structures(struct ixgb_softc *);
+void ixgb_initialize_receive_unit(struct ixgb_softc *);
+void ixgb_enable_intr(struct ixgb_softc *);
+void ixgb_disable_intr(struct ixgb_softc *);
+void ixgb_free_transmit_structures(struct ixgb_softc *);
+void ixgb_free_receive_structures(struct ixgb_softc *);
+void ixgb_update_stats_counters(struct ixgb_softc *);
+void ixgb_clean_transmit_interrupts(struct ixgb_softc *);
+int  ixgb_allocate_receive_structures(struct ixgb_softc *);
+int  ixgb_allocate_transmit_structures(struct ixgb_softc *);
+void ixgb_process_receive_interrupts(struct ixgb_softc *, int);
+void
+ixgb_receive_checksum(struct ixgb_softc *,
+		      struct ixgb_rx_desc * rx_desc,
+		      struct mbuf *);
+void
+ixgb_transmit_checksum_setup(struct ixgb_softc *,
+			     struct mbuf *,
+			     u_int8_t *);
+void ixgb_set_promisc(struct ixgb_softc *);
+void ixgb_disable_promisc(struct ixgb_softc *);
+void ixgb_set_multi(struct ixgb_softc *);
+void ixgb_print_hw_stats(struct ixgb_softc *);
+void ixgb_update_link_status(struct ixgb_softc *);
+int
+ixgb_get_buf(int i, struct ixgb_softc *,
+	     struct mbuf *);
+int  ixgb_encap(struct ixgb_softc *, struct mbuf *);
+int
+ixgb_dma_malloc(struct ixgb_softc *, bus_size_t,
+		struct ixgb_dma_alloc *, int);
+void ixgb_dma_free(struct ixgb_softc *, struct ixgb_dma_alloc *);
+
+/*********************************************************************
+ *  OpenBSD Device Interface Entry Points
+ *********************************************************************/
+
+struct cfattach ixgb_ca = {
+	sizeof(struct ixgb_softc), ixgb_probe, ixgb_attach
+};
+
+struct cfdriver ixgb_cd = {
+	0, "ixgb", DV_IFNET
+};
+
+/* some defines for controlling descriptor fetches in h/w */
+#define RXDCTL_PTHRESH_DEFAULT 128	/* chip considers prefech below this */
+#define RXDCTL_HTHRESH_DEFAULT 16	/* chip will only prefetch if tail is
+					 * pushed this many descriptors from
+					 * head */
+#define RXDCTL_WTHRESH_DEFAULT 0	/* chip writes back at this many or RXT0 */
+
+
+/*********************************************************************
+ *  Device identification routine
+ *
+ *  ixgb_probe determines if the driver should be loaded on
+ *  adapter based on PCI vendor/device id of the adapter.
+ *
+ *  return 0 on success, positive on failure
+ *********************************************************************/
+
+int
+ixgb_probe(struct device *parent, void *match, void *aux)
+{
+	INIT_DEBUGOUT("ixgb_probe: begin");
+
+	return (pci_matchbyid((struct pci_attach_args *)aux, ixgb_devices,
+	    sizeof(ixgb_devices)/sizeof(ixgb_devices[0])));
+}
+
+/*********************************************************************
+ *  Device initialization routine
+ *
+ *  The attach entry point is called when the driver is being loaded.
+ *  This routine identifies the type of hardware, allocates all resources
+ *  and initializes the hardware.
+ *
+ *  return 0 on success, positive on failure
+ *********************************************************************/
+
+void
+ixgb_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct pci_attach_args *pa = aux;
+	struct ixgb_softc *sc;
+	int             tsize, rsize;
+
+	INIT_DEBUGOUT("ixgb_attach: begin");
+
+	sc = (struct ixgb_softc *)self;
+	sc->osdep.ixgb_pa = *pa;
+
+	timeout_set(&sc->timer_handle, ixgb_local_timer, sc);
+
+	/* Determine hardware revision */
+	ixgb_identify_hardware(sc);
+
+	/* Parameters (to be read from user) */
+	sc->num_tx_desc = IXGB_MAX_TXD;
+	sc->num_rx_desc = IXGB_MAX_RXD;
+	sc->tx_int_delay = TIDV;
+	sc->rx_int_delay = RDTR;
+	sc->rx_buffer_len = IXGB_RXBUFFER_2048;
+
+	/*
+	 * These parameters control the automatic generation(Tx) and
+	 * response(Rx) to Ethernet PAUSE frames.
+	 */
+	sc->hw.fc.high_water = FCRTH;
+	sc->hw.fc.low_water = FCRTL;
+	sc->hw.fc.pause_time = FCPAUSE;
+	sc->hw.fc.send_xon = TRUE;
+	sc->hw.fc.type = FLOW_CONTROL;
+
+	/* Set the max frame size assuming standard ethernet sized frames */
+	sc->hw.max_frame_size = IXGB_MAX_JUMBO_FRAME_SIZE;
+
+	if (ixgb_allocate_pci_resources(sc)) {
+		printf("%s: Allocation of PCI resources failed\n",
+		       sc->sc_dv.dv_xname);
+		goto err_pci;
+	}
+
+	tsize = IXGB_ROUNDUP(sc->num_tx_desc * sizeof(struct ixgb_tx_desc),
+	    IXGB_MAX_TXD * sizeof(struct ixgb_tx_desc));
+	tsize = IXGB_ROUNDUP(tsize, PAGE_SIZE);
+
+	/* Allocate Transmit Descriptor ring */
+	if (ixgb_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) {
+		printf("%s: Unable to allocate TxDescriptor memory\n",
+		       sc->sc_dv.dv_xname);
+		goto err_tx_desc;
+	}
+	sc->tx_desc_base = (struct ixgb_tx_desc *) sc->txdma.dma_vaddr;
+
+	rsize = IXGB_ROUNDUP(sc->num_rx_desc * sizeof(struct ixgb_rx_desc),
+	    IXGB_MAX_RXD * sizeof(struct ixgb_rx_desc));
+	rsize = IXGB_ROUNDUP(rsize, PAGE_SIZE);
+
+	/* Allocate Receive Descriptor ring */
+	if (ixgb_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) {
+		printf("%s: Unable to allocate rx_desc memory\n",
+		       sc->sc_dv.dv_xname);
+		goto err_rx_desc;
+	}
+	sc->rx_desc_base = (struct ixgb_rx_desc *) sc->rxdma.dma_vaddr;
+
+	/* Initialize the hardware */
+	if (ixgb_hardware_init(sc)) {
+		printf("%s: Unable to initialize the hardware\n",
+		       sc->sc_dv.dv_xname);
+		goto err_hw_init;
+	}
+
+	/* Setup OS specific network interface */
+	ixgb_setup_interface(sc);
+
+	/* Initialize statistics */
+	ixgb_clear_hw_cntrs(&sc->hw);
+	ixgb_update_stats_counters(sc);
+
+	printf(", address %s\n", ether_sprintf(sc->interface_data.ac_enaddr));
+
+	INIT_DEBUGOUT("ixgb_attach: end");
+	sc->sc_powerhook = powerhook_establish(ixgb_power, sc);
+	return;
+
+err_hw_init:
+	ixgb_dma_free(sc, &sc->rxdma);
+err_rx_desc:
+	ixgb_dma_free(sc, &sc->txdma);
+err_tx_desc:
+err_pci:
+	ixgb_free_pci_resources(sc);
+
+}
+
+void
+ixgb_power(int why, void *arg)
+{
+	struct ixgb_softc *sc = (struct ixgb_softc *)arg;
+	struct ifnet *ifp;
+
+	if (why == PWR_RESUME) {
+		ifp = &sc->interface_data.ac_if;
+		if (ifp->if_flags & IFF_UP)
+			ixgb_init(sc);
+	}
+}
+
+/*********************************************************************
+ *  Transmit entry point
+ *
+ *  ixgb_start is called by the stack to initiate a transmit.
+ *  The driver will remain in this routine as long as there are
+ *  packets to transmit and transmit resources are available.
+ *  In case resources are not available stack is notified and
+ *  the packet is requeued.
+ **********************************************************************/
+
+void
+ixgb_start(struct ifnet *ifp)
+{
+	struct mbuf    *m_head;
+	struct ixgb_softc *sc = ifp->if_softc;
+
+	if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
+		return;
+
+	if (!sc->link_active)
+		return;
+
+	for (;;) {
+		IFQ_POLL(&ifp->if_snd, m_head);
+
+		if (m_head == NULL)
+			break;
+
+		if (ixgb_encap(sc, m_head)) {
+			ifp->if_flags |= IFF_OACTIVE;
+			break;
+		}
+
+		IFQ_DEQUEUE(&ifp->if_snd, m_head);
+
+#if NBPFILTER > 0
+		/* Send a copy of the frame to the BPF listener */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m_head);
+#endif
+
+		/* Set timeout in case hardware has problems transmitting */
+		ifp->if_timer = IXGB_TX_TIMEOUT;
+
+	}
+}
+
+/*********************************************************************
+ *  Ioctl entry point
+ *
+ *  ixgb_ioctl is called when the user wants to configure the
+ *  interface.
+ *
+ *  return 0 on success, positive on failure
+ **********************************************************************/
+
+int
+ixgb_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+        int		s, error = 0;
+	struct ifreq   *ifr = (struct ifreq *) data;
+	struct ifaddr  *ifa = (struct ifaddr *)data;
+	struct ixgb_softc *sc = ifp->if_softc;
+
+	s = splnet();
+
+	if (sc->in_detach)
+		return (error);
+
+	if ((error = ether_ioctl(ifp, &sc->interface_data, command, data)) > 0) {
+		splx(s);
+		return (error);
+	}
+
+	switch (command) {
+	case SIOCSIFADDR:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface "
+			       "Addr)");
+		ifp->if_flags |= IFF_UP;
+		ixgb_init(sc);
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			arp_ifinit(&sc->interface_data, ifa);
+			break;
+#endif /* INET */
+		default:
+			break;
+		}
+		break;
+	case SIOCSIFMTU:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
+		if (ifr->ifr_mtu < ETHERMIN ||
+		    ifr->ifr_mtu > IXGB_MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN - ETHER_CRC_LEN) {
+			error = EINVAL;
+		} else if (ifp->if_mtu != ifr->ifr_mtu) {
+			ifp->if_mtu = ifr->ifr_mtu;
+		}
+		break;
+	case SIOCSIFFLAGS:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)");
+		if (ifp->if_flags & IFF_UP) {
+			if (!(ifp->if_flags & IFF_RUNNING)) {
+				ixgb_init(sc);
+			}
+
+			ixgb_disable_promisc(sc);
+			ixgb_set_promisc(sc);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING) {
+				ixgb_stop(sc);
+			}
+		}
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
+		error = (command == SIOCADDMULTI)
+			? ether_addmulti(ifr, &sc->interface_data)
+			: ether_delmulti(ifr, &sc->interface_data);
+
+		if (error == ENETRESET) {
+			if (ifp->if_flags & IFF_RUNNING) {
+				ixgb_disable_intr(sc);
+				ixgb_set_multi(sc);
+				ixgb_enable_intr(sc);
+			}
+			error = 0;
+		}
+		break;
+	case SIOCSIFMEDIA:
+	case SIOCGIFMEDIA:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
+		error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
+		break;
+	default:
+		IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%X)\n", (int)command);
+		error = EINVAL;
+	}
+
+	splx(s);
+	return (error);
+}
+
+/*********************************************************************
+ *  Watchdog entry point
+ *
+ *  This routine is called whenever hardware quits transmitting.
+ *
+ **********************************************************************/
+
+void
+ixgb_watchdog(struct ifnet * ifp)
+{
+	struct ixgb_softc *sc;
+	sc = ifp->if_softc;
+
+	/*
+	 * If we are in this routine because of pause frames, then don't
+	 * reset the hardware.
+	 */
+	if (IXGB_READ_REG(&sc->hw, STATUS) & IXGB_STATUS_TXOFF) {
+		ifp->if_timer = IXGB_TX_TIMEOUT;
+		return;
+	}
+	printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname);
+
+	ifp->if_flags &= ~IFF_RUNNING;
+
+	ixgb_stop(sc);
+	ixgb_init(sc);
+
+	sc->watchdog_events++;;
+}
+
+/*********************************************************************
+ *  Init entry point
+ *
+ *  This routine is used in two ways. It is used by the stack as
+ *  init entry point in network interface structure. It is also used
+ *  by the driver as a hw/sw initialization routine to get to a
+ *  consistent state.
+ *
+ *  return 0 on success, positive on failure
+ **********************************************************************/
+
+void
+ixgb_init(void *arg)
+{
+	struct ixgb_softc *sc = arg;
+	struct ifnet   *ifp = &sc->interface_data.ac_if;
+	uint32_t temp_reg;
+	int s;
+
+	INIT_DEBUGOUT("ixgb_init: begin");
+
+	s = splnet();
+
+	ixgb_stop(sc);
+
+	/* Get the latest mac address, User can use a LAA */
+	bcopy(sc->interface_data.ac_enaddr, sc->hw.curr_mac_addr,
+	      IXGB_ETH_LENGTH_OF_ADDRESS);
+
+	/* Initialize the hardware */
+	if (ixgb_hardware_init(sc)) {
+		printf("%s: Unable to initialize the hardware\n",
+		       sc->sc_dv.dv_xname);
+		splx(s);
+		return;
+	}
+
+	/* Prepare transmit descriptors and buffers */
+	if (ixgb_setup_transmit_structures(sc)) {
+		printf("%s: Could not setup transmit structures\n",
+		       sc->sc_dv.dv_xname);
+		ixgb_stop(sc);
+		splx(s);
+		return;
+	}
+	ixgb_initialize_transmit_unit(sc);
+
+	/* Setup Multicast table */
+	ixgb_set_multi(sc);
+
+	/* Prepare receive descriptors and buffers */
+	if (ixgb_setup_receive_structures(sc)) {
+		printf("%s: Could not setup receive structures\n",
+		       sc->sc_dv.dv_xname);
+		ixgb_stop(sc);
+		splx(s);
+		return;
+	}
+	ixgb_initialize_receive_unit(sc);
+
+	/* Don't loose promiscuous settings */
+	ixgb_set_promisc(sc);
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	/* Enable jumbo frames */
+	IXGB_WRITE_REG(&sc->hw, MFRMS,
+	    sc->hw.max_frame_size << IXGB_MFRMS_SHIFT);
+	temp_reg = IXGB_READ_REG(&sc->hw, CTRL0);
+	temp_reg |= IXGB_CTRL0_JFE;
+	IXGB_WRITE_REG(&sc->hw, CTRL0, temp_reg);
+
+	timeout_add(&sc->timer_handle, hz);
+	ixgb_clear_hw_cntrs(&sc->hw);
+	ixgb_enable_intr(sc);
+
+	splx(s);
+}
+
+/*********************************************************************
+ *
+ *  Interrupt Service routine
+ *
+ **********************************************************************/
+
+int
+ixgb_intr(void *arg)
+{
+	struct ixgb_softc *sc = arg;
+	struct ifnet	*ifp;
+	u_int32_t	reg_icr;
+	boolean_t	rxdmt0 = FALSE;
+	int s, claimed = 0;
+
+	s = splnet();
+
+	ifp = &sc->interface_data.ac_if;
+
+	 for (;;) {
+		reg_icr = IXGB_READ_REG(&sc->hw, ICR);
+		if (reg_icr == 0)
+			break;
+
+		claimed = 1;
+
+		if (reg_icr & IXGB_INT_RXDMT0)
+			rxdmt0 = TRUE;
+
+		if (ifp->if_flags & IFF_RUNNING) {
+			ixgb_process_receive_interrupts(sc, -1);
+			ixgb_clean_transmit_interrupts(sc);
+		}
+
+		/* Link status change */
+		if (reg_icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC)) {
+			timeout_del(&sc->timer_handle);
+			ixgb_check_for_link(&sc->hw);
+			ixgb_update_link_status(sc);
+			timeout_add(&sc->timer_handle, hz);
+		}
+
+		if (rxdmt0 && sc->raidc) {
+			IXGB_WRITE_REG(&sc->hw, IMC, IXGB_INT_RXDMT0);
+			IXGB_WRITE_REG(&sc->hw, IMS, IXGB_INT_RXDMT0);
+		}
+	}
+
+	if (ifp->if_flags & IFF_RUNNING &&
+	    IFQ_IS_EMPTY(&ifp->if_snd) == 0)
+		ixgb_start(ifp);
+
+	splx(s);
+	return (claimed);
+}
+
+
+/*********************************************************************
+ *
+ *  Media Ioctl callback
+ *
+ *  This routine is called whenever the user queries the status of
+ *  the interface using ifconfig.
+ *
+ **********************************************************************/
+void
+ixgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct ixgb_softc *sc = ifp->if_softc;
+
+	INIT_DEBUGOUT("ixgb_media_status: begin");
+
+	ixgb_check_for_link(&sc->hw);
+	ixgb_update_link_status(sc);
+
+	ifmr->ifm_status = IFM_AVALID;
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (!sc->hw.link_up)
+		return;
+
+	ifmr->ifm_status |= IFM_ACTIVE;
+	ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
+
+	return;
+}
+
+/*********************************************************************
+ *
+ *  Media Ioctl callback
+ *
+ *  This routine is called when the user changes speed/duplex using
+ *  media/mediopt option with ifconfig.
+ *
+ **********************************************************************/
+int
+ixgb_media_change(struct ifnet * ifp)
+{
+	struct ixgb_softc *sc = ifp->if_softc;
+	struct ifmedia *ifm = &sc->media;
+
+	INIT_DEBUGOUT("ixgb_media_change: begin");
+
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+		return (EINVAL);
+
+	return (0);
+}
+
+/*********************************************************************
+ *
+ *  This routine maps the mbufs to tx descriptors.
+ *
+ *  return 0 on success, positive on failure
+ **********************************************************************/
+
+int
+ixgb_encap(struct ixgb_softc *sc, struct mbuf *m_head)
+{
+	u_int8_t        txd_popts;
+	int             i, j, error;
+
+	struct ixgb_q   q;
+	struct ixgb_buffer *tx_buffer = NULL;
+	struct ixgb_tx_desc *current_tx_desc = NULL;
+
+	/*
+	 * Force a cleanup if number of TX descriptors available hits the
+	 * threshold
+	 */
+	if (sc->num_tx_desc_avail <= IXGB_TX_CLEANUP_THRESHOLD) {
+		ixgb_clean_transmit_interrupts(sc);
+	}
+	if (sc->num_tx_desc_avail <= IXGB_TX_CLEANUP_THRESHOLD) {
+		sc->no_tx_desc_avail1++;
+		return (ENOBUFS);
+	}
+	/*
+	 * Map the packet for DMA.
+	 */
+	if (bus_dmamap_create(sc->txtag, IXGB_MAX_JUMBO_FRAME_SIZE, 32,
+	    IXGB_MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &q.map)) {
+		sc->no_tx_map_avail++;
+		return (ENOMEM);
+	}
+	error = bus_dmamap_load_mbuf(sc->txtag, q.map,
+				     m_head, BUS_DMA_NOWAIT);
+	if (error != 0) {
+		sc->no_tx_dma_setup++;
+		bus_dmamap_destroy(sc->txtag, q.map);
+		return (error);
+	}
+	IXGB_KASSERT(q.map->dm_nsegs != 0, ("ixgb_encap: empty packet"));
+
+	if (q.map->dm_nsegs > sc->num_tx_desc_avail) {
+		sc->no_tx_desc_avail2++;
+		bus_dmamap_destroy(sc->txtag, q.map);
+		return (ENOBUFS);
+	}
+
+#if 0
+	ixgb_transmit_checksum_setup(sc, m_head, &txd_popts);
+#endif
+	txd_popts = 0;
+
+	i = sc->next_avail_tx_desc;
+	for (j = 0; j < q.map->dm_nsegs; j++) {
+		tx_buffer = &sc->tx_buffer_area[i];
+		current_tx_desc = &sc->tx_desc_base[i];
+
+		current_tx_desc->buff_addr = htole64(q.map->dm_segs[j].ds_addr);
+		current_tx_desc->cmd_type_len = htole32((sc->txd_cmd | q.map->dm_segs[j].ds_len));
+		current_tx_desc->popts = txd_popts;
+		if (++i == sc->num_tx_desc)
+			i = 0;
+
+		tx_buffer->m_head = NULL;
+	}
+
+	sc->num_tx_desc_avail -= q.map->dm_nsegs;
+	sc->next_avail_tx_desc = i;
+
+	tx_buffer->m_head = m_head;
+	tx_buffer->map = q.map;
+	bus_dmamap_sync(sc->txtag, q.map, 0, q.map->dm_mapsize,
+	    BUS_DMASYNC_PREWRITE);
+
+	/*
+	 * Last Descriptor of Packet needs End Of Packet (EOP)
+	 */
+	current_tx_desc->cmd_type_len |= htole32(IXGB_TX_DESC_CMD_EOP);
+
+	/*
+	 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
+	 * that this frame is available to transmit.
+	 */
+	bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
+	    sc->txdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+	IXGB_WRITE_REG(&sc->hw, TDT, i);
+
+	return (0);
+}
+
+void
+ixgb_set_promisc(struct ixgb_softc *sc)
+{
+
+	u_int32_t       reg_rctl;
+	struct ifnet   *ifp = &sc->interface_data.ac_if;
+
+	reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
+
+	if (ifp->if_flags & IFF_PROMISC) {
+		reg_rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
+		IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
+	} else if (ifp->if_flags & IFF_ALLMULTI) {
+		reg_rctl |= IXGB_RCTL_MPE;
+		reg_rctl &= ~IXGB_RCTL_UPE;
+		IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
+	}
+}
+
+void
+ixgb_disable_promisc(struct ixgb_softc *sc)
+{
+	u_int32_t       reg_rctl;
+
+	reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
+
+	reg_rctl &= (~IXGB_RCTL_UPE);
+	reg_rctl &= (~IXGB_RCTL_MPE);
+	IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
+}
+
+
+/*********************************************************************
+ *  Multicast Update
+ *
+ *  This routine is called whenever multicast address list is updated.
+ *
+ **********************************************************************/
+
+void
+ixgb_set_multi(struct ixgb_softc *sc)
+{
+	u_int32_t       reg_rctl = 0;
+	u_int8_t        mta[MAX_NUM_MULTICAST_ADDRESSES * IXGB_ETH_LENGTH_OF_ADDRESS];
+	int             mcnt = 0;
+	struct ifnet   *ifp = &sc->interface_data.ac_if;
+	struct arpcom *ac = &sc->interface_data;
+	struct ether_multi *enm;
+	struct ether_multistep step;
+
+	IOCTL_DEBUGOUT("ixgb_set_multi: begin");
+
+	ETHER_FIRST_MULTI(step, ac, enm);
+	while (enm != NULL) {
+		if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
+			ifp->if_flags |= IFF_ALLMULTI;
+			mcnt = MAX_NUM_MULTICAST_ADDRESSES;
+		}
+		if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
+			break;
+		bcopy(enm->enm_addrlo, &mta[mcnt*IXGB_ETH_LENGTH_OF_ADDRESS],
+		      IXGB_ETH_LENGTH_OF_ADDRESS);
+		mcnt++;
+		ETHER_NEXT_MULTI(step, enm);
+	}
+
+	if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
+		reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
+		reg_rctl |= IXGB_RCTL_MPE;
+		IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
+	} else
+		ixgb_mc_addr_list_update(&sc->hw, mta, mcnt, 0);
+}
+
+
+/*********************************************************************
+ *  Timer routine
+ *
+ *  This routine checks for link status and updates statistics.
+ *
+ **********************************************************************/
+
+void
+ixgb_local_timer(void *arg)
+{
+	struct ifnet   *ifp;
+	struct ixgb_softc *sc = arg;
+	int s;
+
+	ifp = &sc->interface_data.ac_if;
+
+	s = splnet();
+
+	ixgb_check_for_link(&sc->hw);
+	ixgb_update_link_status(sc);
+	ixgb_update_stats_counters(sc);
+	if (ixgb_display_debug_stats && ifp->if_flags & IFF_RUNNING) {
+		ixgb_print_hw_stats(sc);
+	}
+
+	timeout_add(&sc->timer_handle, hz);
+
+	splx(s);
+}
+
+void
+ixgb_update_link_status(struct ixgb_softc *sc)
+{
+	struct ifnet *ifp = &sc->interface_data.ac_if;
+
+	if (sc->hw.link_up) {
+		if (!sc->link_active) {
+			sc->link_active = 1;
+			ifp->if_link_state = LINK_STATE_UP;
+			if_link_state_change(ifp);
+		}
+	} else {
+		if (sc->link_active) {
+			sc->link_active = 0;
+			ifp->if_link_state = LINK_STATE_DOWN;
+			if_link_state_change(ifp);
+		}
+	}
+}
+
+
+
+/*********************************************************************
+ *
+ *  This routine disables all traffic on the adapter by issuing a
+ *  global reset on the MAC and deallocates TX/RX buffers.
+ *
+ **********************************************************************/
+
+void
+ixgb_stop(void *arg)
+{
+	struct ifnet   *ifp;
+	struct ixgb_softc *sc = arg;
+	ifp = &sc->interface_data.ac_if;
+
+	INIT_DEBUGOUT("ixgb_stop: begin\n");
+	ixgb_disable_intr(sc);
+	sc->hw.adapter_stopped = FALSE;
+	ixgb_adapter_stop(&sc->hw);
+	timeout_del(&sc->timer_handle);
+
+	/* Tell the stack that the interface is no longer active */
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+	ixgb_free_transmit_structures(sc);
+	ixgb_free_receive_structures(sc);
+}
+
+
+/*********************************************************************
+ *
+ *  Determine hardware revision.
+ *
+ **********************************************************************/
+void
+ixgb_identify_hardware(struct ixgb_softc *sc)
+{
+	u_int32_t	reg;
+	struct pci_attach_args *pa = &sc->osdep.ixgb_pa;
+
+	/* Make sure our PCI config space has the necessary stuff set */
+	sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag,
+					    PCI_COMMAND_STATUS_REG);
+
+	/* Save off the information about this board */
+	sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
+	sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
+
+	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
+	sc->hw.revision_id = PCI_REVISION(reg);
+
+	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+	sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
+	sc->hw.subsystem_id = PCI_PRODUCT(reg);
+
+	/* Set MacType, etc. based on this PCI info */
+	switch (sc->hw.device_id) {
+	case IXGB_DEVICE_ID_82597EX:
+	case IXGB_DEVICE_ID_82597EX_SR:
+	case IXGB_DEVICE_ID_82597EX_LR:
+	case IXGB_DEVICE_ID_82597EX_CX4:
+		sc->hw.mac_type = ixgb_82597;
+		break;
+	default:
+		INIT_DEBUGOUT1("Unknown device if 0x%x", sc->hw.device_id);
+		printf("%s: unsupported device id 0x%x\n", sc->sc_dv.dv_xname, sc->hw.device_id);
+	}
+}
+
+int
+ixgb_allocate_pci_resources(struct ixgb_softc *sc)
+	
+{
+	int val;
+	pci_intr_handle_t	ih;
+	const char		*intrstr = NULL;
+	struct pci_attach_args *pa =  &sc->osdep.ixgb_pa;
+	pci_chipset_tag_t	pc = pa->pa_pc;
+
+	val = pci_conf_read(pa->pa_pc, pa->pa_tag, IXGB_MMBA);
+	if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
+		printf(": mmba isn't memory");
+		return (ENXIO);
+	}
+	if (pci_mapreg_map(pa, IXGB_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
+	    &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle,
+	    &sc->osdep.ixgb_membase, &sc->osdep.ixgb_memsize, 0)) {
+		printf(": can't find mem space\n");
+		return (ENXIO);
+	}
+
+	if (pci_intr_map(pa, &ih)) {
+		printf(": couldn't map interrupt\n");
+		return (ENXIO);
+	}
+
+	intrstr = pci_intr_string(pc, ih);
+	sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, ixgb_intr, sc,
+					    sc->sc_dv.dv_xname);
+	if (sc->sc_intrhand == NULL) {
+		printf(": couldn't establish interrupt");
+		if (intrstr != NULL)
+			printf(" at %s", intrstr);
+		printf("\n");
+		return (ENXIO);
+	}
+	printf(": %s", intrstr);
+
+	sc->hw.back = &sc->osdep;
+
+	return(0);
+}
+
+void
+ixgb_free_pci_resources(struct ixgb_softc *sc)
+{
+	struct pci_attach_args *pa = &sc->osdep.ixgb_pa;
+	pci_chipset_tag_t	pc = pa->pa_pc;
+
+	if(sc->sc_intrhand)
+		pci_intr_disestablish(pc, sc->sc_intrhand);
+	sc->sc_intrhand = 0;
+
+	if(sc->osdep.ixgb_membase)
+		bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle,
+				sc->osdep.ixgb_memsize);
+	sc->osdep.ixgb_membase = 0;
+}
+
+/*********************************************************************
+ *
+ *  Initialize the hardware to a configuration as specified by the
+ *  adapter structure. The controller is reset, the EEPROM is
+ *  verified, the MAC address is set, then the shared initialization
+ *  routines are called.
+ *
+ **********************************************************************/
+int
+ixgb_hardware_init(struct ixgb_softc *sc)
+{
+	/* Issue a global reset */
+	sc->hw.adapter_stopped = FALSE;
+	ixgb_adapter_stop(&sc->hw);
+
+	/* Make sure we have a good EEPROM before we read from it */
+	if (!ixgb_validate_eeprom_checksum(&sc->hw)) {
+		printf("%s: The EEPROM Checksum Is Not Valid\n",
+		       sc->sc_dv.dv_xname);
+		return (EIO);
+	}
+	if (!ixgb_init_hw(&sc->hw)) {
+		printf("%s: Hardware Initialization Failed",
+		       sc->sc_dv.dv_xname);
+		return (EIO);
+	}
+	bcopy(sc->hw.curr_mac_addr, sc->interface_data.ac_enaddr,
+	      IXGB_ETH_LENGTH_OF_ADDRESS);
+
+	return (0);
+}
+
+/*********************************************************************
+ *
+ *  Setup networking device structure and register an interface.
+ *
+ **********************************************************************/
+void
+ixgb_setup_interface(struct ixgb_softc *sc)
+{
+	struct ifnet   *ifp;
+	INIT_DEBUGOUT("ixgb_setup_interface: begin");
+
+	ifp = &sc->interface_data.ac_if;
+	strlcpy(ifp->if_xname, sc->sc_dv.dv_xname, IFNAMSIZ);
+
+	ifp->if_baudrate = 1000000000;
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = ixgb_ioctl;
+	ifp->if_start = ixgb_start;
+	ifp->if_watchdog = ixgb_watchdog;
+	IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1);
+	IFQ_SET_READY(&ifp->if_snd);
+
+	ifp->if_capabilities = IFCAP_VLAN_MTU;
+
+	/*
+	 * Specify the media types supported by this adapter and register
+	 * callbacks to update media and link information
+	 */
+	ifmedia_init(&sc->media, IFM_IMASK, ixgb_media_change,
+		     ixgb_media_status);
+	ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
+		    0, NULL);
+	ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX,
+		    0, NULL);
+	ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
+	ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
+
+	if_attach(ifp);
+	ether_ifattach(ifp);
+}
+
+/********************************************************************
+ * Manage DMA'able memory.
+ *******************************************************************/
+int
+ixgb_dma_malloc(struct ixgb_softc *sc, bus_size_t size,
+		struct ixgb_dma_alloc * dma, int mapflags)
+{
+	int r;
+
+	dma->dma_tag = sc->osdep.ixgb_pa.pa_dmat;
+	r = bus_dmamap_create(dma->dma_tag, size, 1,
+	    size, 0, BUS_DMA_NOWAIT, &dma->dma_map);
+	if (r != 0) {
+		printf("%s: ixgb_dma_malloc: bus_dmamap_create failed; "
+			"error %u\n", sc->sc_dv.dv_xname, r);
+		goto fail_0;
+	}
+
+	r = bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg,
+	    1, &dma->dma_nseg, BUS_DMA_NOWAIT);
+	if (r != 0) {
+		printf("%s: ixgb_dma_malloc: bus_dmammem_alloc failed; "
+			"size %lu, error %d\n", sc->sc_dv.dv_xname,
+			(unsigned long)size, r);
+		goto fail_1;
+	}
+
+	r = bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size,
+	    &dma->dma_vaddr, BUS_DMA_NOWAIT);
+	if (r != 0) {
+		printf("%s: ixgb_dma_malloc: bus_dmammem_map failed; "
+			"size %lu, error %d\n", sc->sc_dv.dv_xname,
+			(unsigned long)size, r);
+		goto fail_2;
+	}
+
+	r = bus_dmamap_load(sc->osdep.ixgb_pa.pa_dmat, dma->dma_map,
+			    dma->dma_vaddr,
+			    size,
+			    NULL,
+			    mapflags | BUS_DMA_NOWAIT);
+	if (r != 0) {
+		printf("%s: ixgb_dma_malloc: bus_dmamap_load failed; "
+			"error %u\n", sc->sc_dv.dv_xname, r);
+		goto fail_3;
+	}
+
+	dma->dma_size = size;
+	return (0);
+
+/* fail_4: */
+	bus_dmamap_unload(dma->dma_tag, dma->dma_map);
+fail_3: 
+	bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
+fail_2: 
+	bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg);
+fail_1: 
+	bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
+fail_0: 
+	dma->dma_map = NULL;
+	/* dma->dma_tag = NULL; */
+	return (r);
+}
+
+void
+ixgb_dma_free(struct ixgb_softc *sc, struct ixgb_dma_alloc *dma)
+{
+	bus_dmamap_unload(dma->dma_tag, dma->dma_map);
+	bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size);
+	bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg);
+	bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
+}
+
+/*********************************************************************
+ *
+ *  Allocate memory for tx_buffer structures. The tx_buffer stores all
+ *  the information needed to transmit a packet on the wire.
+ *
+ **********************************************************************/
+int
+ixgb_allocate_transmit_structures(struct ixgb_softc *sc)
+{
+	if (!(sc->tx_buffer_area =
+	      (struct ixgb_buffer *) malloc(sizeof(struct ixgb_buffer) *
+					    sc->num_tx_desc, M_DEVBUF,
+					    M_NOWAIT))) {
+		printf("%s: Unable to allocate tx_buffer memory\n",
+		       sc->sc_dv.dv_xname);
+		return ENOMEM;
+	}
+	bzero(sc->tx_buffer_area,
+	      sizeof(struct ixgb_buffer) * sc->num_tx_desc);
+
+	return (0);
+}
+
+/*********************************************************************
+ *
+ *  Allocate and initialize transmit structures.
+ *
+ **********************************************************************/
+int
+ixgb_setup_transmit_structures(struct ixgb_softc *sc)
+{
+	sc->txtag = sc->osdep.ixgb_pa.pa_dmat;
+
+	if (ixgb_allocate_transmit_structures(sc))
+		return (ENOMEM);
+
+	bzero((void *)sc->tx_desc_base,
+	      (sizeof(struct ixgb_tx_desc)) * sc->num_tx_desc);
+
+	sc->next_avail_tx_desc = 0;
+	sc->oldest_used_tx_desc = 0;
+
+	/* Set number of descriptors available */
+	sc->num_tx_desc_avail = sc->num_tx_desc;
+
+	/* Set checksum context */
+	sc->active_checksum_context = OFFLOAD_NONE;
+
+	return (0);
+}
+
+/*********************************************************************
+ *
+ *  Enable transmit unit.
+ *
+ **********************************************************************/
+void
+ixgb_initialize_transmit_unit(struct ixgb_softc *sc)
+{
+	u_int32_t       reg_tctl;
+	u_int64_t       bus_addr;
+
+	/* Setup the Base and Length of the Tx Descriptor Ring */
+	bus_addr = sc->txdma.dma_map->dm_segs[0].ds_addr;
+	IXGB_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr);
+	IXGB_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32));
+	IXGB_WRITE_REG(&sc->hw, TDLEN,
+		       sc->num_tx_desc *
+		       sizeof(struct ixgb_tx_desc));
+
+	/* Setup the HW Tx Head and Tail descriptor pointers */
+	IXGB_WRITE_REG(&sc->hw, TDH, 0);
+	IXGB_WRITE_REG(&sc->hw, TDT, 0);
+
+	HW_DEBUGOUT2("Base = %x, Length = %x\n",
+		     IXGB_READ_REG(&sc->hw, TDBAL),
+		     IXGB_READ_REG(&sc->hw, TDLEN));
+
+	IXGB_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay);
+
+	/* Program the Transmit Control Register */
+	reg_tctl = IXGB_READ_REG(&sc->hw, TCTL);
+	reg_tctl = IXGB_TCTL_TCE | IXGB_TCTL_TXEN | IXGB_TCTL_TPDE;
+	IXGB_WRITE_REG(&sc->hw, TCTL, reg_tctl);
+
+	/* Setup Transmit Descriptor Settings for this adapter */
+	sc->txd_cmd = IXGB_TX_DESC_TYPE | IXGB_TX_DESC_CMD_RS;
+
+	if (sc->tx_int_delay > 0)
+		sc->txd_cmd |= IXGB_TX_DESC_CMD_IDE;
+}
+
+/*********************************************************************
+ *
+ *  Free all transmit related data structures.
+ *
+ **********************************************************************/
+void
+ixgb_free_transmit_structures(struct ixgb_softc *sc)
+{
+	struct ixgb_buffer *tx_buffer;
+	int             i;
+
+	INIT_DEBUGOUT("free_transmit_structures: begin");
+
+	if (sc->tx_buffer_area != NULL) {
+		tx_buffer = sc->tx_buffer_area;
+		for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) {
+			if (tx_buffer->m_head != NULL) {
+				bus_dmamap_unload(sc->txtag, tx_buffer->map);
+				bus_dmamap_destroy(sc->txtag, tx_buffer->map);
+				m_freem(tx_buffer->m_head);
+			}
+			tx_buffer->m_head = NULL;
+		}
+	}
+	if (sc->tx_buffer_area != NULL) {
+		free(sc->tx_buffer_area, M_DEVBUF);
+		sc->tx_buffer_area = NULL;
+	}
+	if (sc->txtag != NULL) {
+		sc->txtag = NULL;
+	}
+}
+
+/*********************************************************************
+ *
+ *  The offload context needs to be set when we transfer the first
+ *  packet of a particular protocol (TCP/UDP). We change the
+ *  context only if the protocol type changes.
+ *
+ **********************************************************************/
+void
+ixgb_transmit_checksum_setup(struct ixgb_softc *sc,
+			     struct mbuf *mp,
+			     u_int8_t *txd_popts)
+{
+	struct ixgb_context_desc *TXD;
+	struct ixgb_buffer *tx_buffer;
+	int             curr_txd;
+
+	if (mp->m_pkthdr.csum_flags) {
+
+		if (mp->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) {
+			*txd_popts = IXGB_TX_DESC_POPTS_TXSM;
+			if (sc->active_checksum_context == OFFLOAD_TCP_IP)
+				return;
+			else
+				sc->active_checksum_context = OFFLOAD_TCP_IP;
+
+		} else if (mp->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) {
+			*txd_popts = IXGB_TX_DESC_POPTS_TXSM;
+			if (sc->active_checksum_context == OFFLOAD_UDP_IP)
+				return;
+			else
+				sc->active_checksum_context = OFFLOAD_UDP_IP;
+		} else {
+			*txd_popts = 0;
+			return;
+		}
+	} else {
+		*txd_popts = 0;
+		return;
+	}
+
+	/*
+	 * If we reach this point, the checksum offload context needs to be
+	 * reset.
+	 */
+	curr_txd = sc->next_avail_tx_desc;
+	tx_buffer = &sc->tx_buffer_area[curr_txd];
+	TXD = (struct ixgb_context_desc *) & sc->tx_desc_base[curr_txd];
+
+	TXD->tucss = ENET_HEADER_SIZE + sizeof(struct ip);
+	TXD->tucse = 0;
+
+	TXD->mss = 0;
+
+	if (sc->active_checksum_context == OFFLOAD_TCP_IP) {
+		TXD->tucso =
+			ENET_HEADER_SIZE + sizeof(struct ip) +
+			offsetof(struct tcphdr, th_sum);
+	} else if (sc->active_checksum_context == OFFLOAD_UDP_IP) {
+		TXD->tucso =
+			ENET_HEADER_SIZE + sizeof(struct ip) +
+			offsetof(struct udphdr, uh_sum);
+	}
+	TXD->cmd_type_len = htole32(IXGB_CONTEXT_DESC_CMD_TCP | IXGB_TX_DESC_CMD_RS | IXGB_CONTEXT_DESC_CMD_IDE);
+
+	tx_buffer->m_head = NULL;
+
+	if (++curr_txd == sc->num_tx_desc)
+		curr_txd = 0;
+
+	sc->num_tx_desc_avail--;
+	sc->next_avail_tx_desc = curr_txd;
+}
+
+/**********************************************************************
+ *
+ *  Examine each tx_buffer in the used queue. If the hardware is done
+ *  processing the packet then free associated resources. The
+ *  tx_buffer is put back on the free queue.
+ *
+ **********************************************************************/
+void
+ixgb_clean_transmit_interrupts(struct ixgb_softc *sc)
+{
+	int             i, num_avail;
+	struct ixgb_buffer *tx_buffer;
+	struct ixgb_tx_desc *tx_desc;
+	struct ifnet	*ifp = &sc->interface_data.ac_if;
+
+	if (sc->num_tx_desc_avail == sc->num_tx_desc)
+		return;
+
+	num_avail = sc->num_tx_desc_avail;
+	i = sc->oldest_used_tx_desc;
+
+	tx_buffer = &sc->tx_buffer_area[i];
+	tx_desc = &sc->tx_desc_base[i];
+
+	bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
+	    sc->txdma.dma_size, BUS_DMASYNC_POSTREAD);
+	while (tx_desc->status & IXGB_TX_DESC_STATUS_DD) {
+
+		tx_desc->status = 0;
+		num_avail++;
+
+		if (tx_buffer->m_head) {
+			ifp->if_opackets++;
+			bus_dmamap_unload(sc->txtag, tx_buffer->map);
+			bus_dmamap_destroy(sc->txtag, tx_buffer->map);
+
+			m_freem(tx_buffer->m_head);
+			tx_buffer->m_head = NULL;
+		}
+		if (++i == sc->num_tx_desc)
+			i = 0;
+
+		tx_buffer = &sc->tx_buffer_area[i];
+		tx_desc = &sc->tx_desc_base[i];
+	}
+	bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
+	    sc->txdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	sc->oldest_used_tx_desc = i;
+
+	/*
+	 * If we have enough room, clear IFF_OACTIVE to tell the stack that
+	 * it is OK to send packets. If there are no pending descriptors,
+	 * clear the timeout. Otherwise, if some descriptors have been freed,
+	 * restart the timeout.
+	 */
+	if (num_avail > IXGB_TX_CLEANUP_THRESHOLD) {
+		ifp->if_flags &= ~IFF_OACTIVE;
+		if (num_avail == sc->num_tx_desc)
+			ifp->if_timer = 0;
+		else if (num_avail == sc->num_tx_desc_avail)
+			ifp->if_timer = IXGB_TX_TIMEOUT;
+	}
+	sc->num_tx_desc_avail = num_avail;
+}
+
+
+/*********************************************************************
+ *
+ *  Get a buffer from system mbuf buffer pool.
+ *
+ **********************************************************************/
+int
+ixgb_get_buf(int i, struct ixgb_softc *sc,
+	     struct mbuf *nmp)
+{
+	struct mbuf *mp = nmp;
+	struct ixgb_buffer *rx_buffer;
+	struct ifnet   *ifp;
+	int             error;
+
+	ifp = &sc->interface_data.ac_if;
+
+	if (mp == NULL) {
+		MGETHDR(mp, M_DONTWAIT, MT_DATA);
+		if (mp == NULL) {
+			sc->mbuf_alloc_failed++;
+			return (ENOBUFS);
+		}
+		MCLGET(mp, M_DONTWAIT);
+		if ((mp->m_flags & M_EXT) == 0) {
+			m_freem(mp);
+			sc->mbuf_cluster_failed++;
+			return (ENOBUFS);
+		}
+		mp->m_len = mp->m_pkthdr.len = MCLBYTES;
+	} else {
+		mp->m_len = mp->m_pkthdr.len = MCLBYTES;
+		mp->m_data = mp->m_ext.ext_buf;
+		mp->m_next = NULL;
+	}
+
+	if (ifp->if_mtu <= ETHERMTU) {
+		m_adj(mp, ETHER_ALIGN);
+	}
+	rx_buffer = &sc->rx_buffer_area[i];
+
+	/*
+	 * Using memory from the mbuf cluster pool, invoke the bus_dma
+	 * machinery to arrange the memory mapping.
+	 */
+	error = bus_dmamap_load(sc->rxtag, rx_buffer->map,
+	    mtod(mp, void *), mp->m_len, NULL, 0);
+	if (error) {
+		m_free(mp);
+		return (error);
+	}
+	rx_buffer->m_head = mp;
+	sc->rx_desc_base[i].buff_addr = htole64(rx_buffer->map->dm_segs[0].ds_addr);
+	bus_dmamap_sync(sc->rxtag, rx_buffer->map, 0,
+	    rx_buffer->map->dm_mapsize,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	return (0);
+}
+
+/*********************************************************************
+ *
+ *  Allocate memory for rx_buffer structures. Since we use one
+ *  rx_buffer per received packet, the maximum number of rx_buffer's
+ *  that we'll need is equal to the number of receive descriptors
+ *  that we've allocated.
+ *
+ **********************************************************************/
+int
+ixgb_allocate_receive_structures(struct ixgb_softc *sc)
+{
+	int             i, error;
+	struct ixgb_buffer *rx_buffer;
+
+	if (!(sc->rx_buffer_area =
+	      (struct ixgb_buffer *) malloc(sizeof(struct ixgb_buffer) *
+					    sc->num_rx_desc, M_DEVBUF,
+					    M_NOWAIT))) {
+		printf("%s: Unable to allocate rx_buffer memory\n",
+		       sc->sc_dv.dv_xname);
+		return (ENOMEM);
+	}
+
+	bzero(sc->rx_buffer_area,
+	      sizeof(struct ixgb_buffer) * sc->num_rx_desc);
+
+	sc->rxtag = sc->osdep.ixgb_pa.pa_dmat;
+
+	rx_buffer = sc->rx_buffer_area;
+	for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) {
+		error = bus_dmamap_create(sc->rxtag, MCLBYTES, 1,
+					  MCLBYTES, 0, BUS_DMA_NOWAIT,
+					  &rx_buffer->map);
+		if (error != 0) {
+			printf("%s: ixgb_allocate_receive_structures: "
+			       "bus_dmamap_create failed; error %u\n",
+			       sc->sc_dv.dv_xname, error);
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < sc->num_rx_desc; i++) {
+		if (ixgb_get_buf(i, sc, NULL) == ENOBUFS) {
+			sc->rx_buffer_area[i].m_head = NULL;
+			sc->rx_desc_base[i].buff_addr = 0;
+			return (ENOBUFS);
+		}
+	}
+	bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0,
+	    sc->rxdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	return (0);
+
+fail:
+	sc->rxtag = NULL;
+	free(sc->rx_buffer_area, M_DEVBUF);
+	sc->rx_buffer_area = NULL;
+	return (error);
+}
+
+/*********************************************************************
+ *
+ *  Allocate and initialize receive structures.
+ *
+ **********************************************************************/
+int
+ixgb_setup_receive_structures(struct ixgb_softc *sc)
+{
+	bzero((void *)sc->rx_desc_base,
+	      (sizeof(struct ixgb_rx_desc)) * sc->num_rx_desc);
+
+	if (ixgb_allocate_receive_structures(sc))
+		return (ENOMEM);
+
+	/* Setup our descriptor pointers */
+	sc->next_rx_desc_to_check = 0;
+	sc->next_rx_desc_to_use = 0;
+	return (0);
+}
+
+/*********************************************************************
+ *
+ *  Enable receive unit.
+ *
+ **********************************************************************/
+void
+ixgb_initialize_receive_unit(struct ixgb_softc *sc)
+{
+	u_int32_t       reg_rctl;
+	u_int32_t       reg_rxcsum;
+	u_int32_t       reg_rxdctl;
+	struct ifnet   *ifp;
+	u_int64_t       bus_addr;
+
+	ifp = &sc->interface_data.ac_if;
+
+	/*
+	 * Make sure receives are disabled while setting up the descriptor
+	 * ring
+	 */
+	reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
+	IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl & ~IXGB_RCTL_RXEN);
+
+	/* Set the Receive Delay Timer Register */
+	IXGB_WRITE_REG(&sc->hw, RDTR,
+		       sc->rx_int_delay);
+
+	/* Setup the Base and Length of the Rx Descriptor Ring */
+	bus_addr = sc->rxdma.dma_map->dm_segs[0].ds_addr;
+	IXGB_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr);
+	IXGB_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32));
+	IXGB_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc *
+		       sizeof(struct ixgb_rx_desc));
+
+	/* Setup the HW Rx Head and Tail Descriptor Pointers */
+	IXGB_WRITE_REG(&sc->hw, RDH, 0);
+
+	IXGB_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1);
+
+	reg_rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT
+		| RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT
+		| RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
+	IXGB_WRITE_REG(&sc->hw, RXDCTL, reg_rxdctl);
+
+	sc->raidc = 1;
+	if (sc->raidc) {
+		uint32_t        raidc;
+		uint8_t         poll_threshold;
+#define IXGB_RAIDC_POLL_DEFAULT 120
+
+		poll_threshold = ((sc->num_rx_desc - 1) >> 3);
+		poll_threshold >>= 1;
+		poll_threshold &= 0x3F;
+		raidc = IXGB_RAIDC_EN | IXGB_RAIDC_RXT_GATE |
+			(IXGB_RAIDC_POLL_DEFAULT << IXGB_RAIDC_POLL_SHIFT) |
+			(sc->rx_int_delay << IXGB_RAIDC_DELAY_SHIFT) |
+			poll_threshold;
+		IXGB_WRITE_REG(&sc->hw, RAIDC, raidc);
+	}
+
+	/* Enable Receive Checksum Offload for TCP and UDP ? */
+	reg_rxcsum = IXGB_READ_REG(&sc->hw, RXCSUM);
+	reg_rxcsum |= IXGB_RXCSUM_TUOFL;
+	IXGB_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
+
+	/* Setup the Receive Control Register */
+	reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
+	reg_rctl &= ~(3 << IXGB_RCTL_MO_SHIFT);
+	reg_rctl |= IXGB_RCTL_BAM | IXGB_RCTL_RDMTS_1_2 | IXGB_RCTL_SECRC |
+		IXGB_RCTL_CFF |
+		(sc->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT);
+
+	switch (sc->rx_buffer_len) {
+	default:
+	case IXGB_RXBUFFER_2048:
+		reg_rctl |= IXGB_RCTL_BSIZE_2048;
+		break;
+	case IXGB_RXBUFFER_4096:
+		reg_rctl |= IXGB_RCTL_BSIZE_4096;
+		break;
+	case IXGB_RXBUFFER_8192:
+		reg_rctl |= IXGB_RCTL_BSIZE_8192;
+		break;
+	case IXGB_RXBUFFER_16384:
+		reg_rctl |= IXGB_RCTL_BSIZE_16384;
+		break;
+	}
+
+	reg_rctl |= IXGB_RCTL_RXEN;
+
+	/* Enable Receives */
+	IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
+}
+
+/*********************************************************************
+ *
+ *  Free receive related data structures.
+ *
+ **********************************************************************/
+void
+ixgb_free_receive_structures(struct ixgb_softc *sc)
+{
+	struct ixgb_buffer *rx_buffer;
+	int             i;
+
+	INIT_DEBUGOUT("free_receive_structures: begin");
+
+	if (sc->rx_buffer_area != NULL) {
+		rx_buffer = sc->rx_buffer_area;
+		for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) {
+			if (rx_buffer->map != NULL) {
+				bus_dmamap_unload(sc->rxtag, rx_buffer->map);
+				bus_dmamap_destroy(sc->rxtag, rx_buffer->map);
+			}
+			if (rx_buffer->m_head != NULL)
+				m_freem(rx_buffer->m_head);
+			rx_buffer->m_head = NULL;
+		}
+	}
+	if (sc->rx_buffer_area != NULL) {
+		free(sc->rx_buffer_area, M_DEVBUF);
+		sc->rx_buffer_area = NULL;
+	}
+	if (sc->rxtag != NULL) {
+		sc->rxtag = NULL;
+	}
+}
+
+/*********************************************************************
+ *
+ *  This routine executes in interrupt context. It replenishes
+ *  the mbufs in the descriptor and sends data which has been
+ *  dma'ed into host memory to upper layer.
+ *
+ *  We loop at most count times if count is > 0, or until done if
+ *  count < 0.
+ *
+ *********************************************************************/
+void
+ixgb_process_receive_interrupts(struct ixgb_softc *sc, int count)
+{
+	struct ifnet   *ifp;
+	struct mbuf    *mp;
+	int             eop = 0;
+	int             len;
+	u_int8_t        accept_frame = 0;
+	int             i;
+	int             next_to_use = 0;
+	int             eop_desc;
+
+	/* Pointer to the receive descriptor being examined. */
+	struct ixgb_rx_desc *current_desc;
+
+	ifp = &sc->interface_data.ac_if;
+	i = sc->next_rx_desc_to_check;
+	next_to_use = sc->next_rx_desc_to_use;
+	eop_desc = sc->next_rx_desc_to_check;
+	current_desc = &sc->rx_desc_base[i];
+	bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0,
+	    sc->rxdma.dma_size, BUS_DMASYNC_POSTREAD);
+
+	if (!((current_desc->status) & IXGB_RX_DESC_STATUS_DD)) {
+		return;
+	}
+
+	while ((current_desc->status & IXGB_RX_DESC_STATUS_DD) &&
+		    (count != 0) &&
+		    (ifp->if_flags & IFF_RUNNING)) {
+
+		mp = sc->rx_buffer_area[i].m_head;
+		bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map,
+		    0, sc->rx_buffer_area[i].map->dm_mapsize,
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(sc->rxtag, sc->rx_buffer_area[i].map);
+
+		accept_frame = 1;
+		if (current_desc->status & IXGB_RX_DESC_STATUS_EOP) {
+			count--;
+			eop = 1;
+		} else {
+			eop = 0;
+		}
+		len = current_desc->length;
+
+		if (current_desc->errors & (IXGB_RX_DESC_ERRORS_CE |
+			    IXGB_RX_DESC_ERRORS_SE | IXGB_RX_DESC_ERRORS_P |
+					    IXGB_RX_DESC_ERRORS_RXE)) {
+			accept_frame = 0;
+		}
+		if (accept_frame) {
+
+			/* Assign correct length to the current fragment */
+			mp->m_len = len;
+
+			if (sc->fmp == NULL) {
+				mp->m_pkthdr.len = len;
+				sc->fmp = mp;	/* Store the first mbuf */
+				sc->lmp = mp;
+			} else {
+				/* Chain mbuf's together */
+				mp->m_flags &= ~M_PKTHDR;
+				sc->lmp->m_next = mp;
+				sc->lmp = sc->lmp->m_next;
+				sc->fmp->m_pkthdr.len += len;
+			}
+
+			if (eop) {
+				eop_desc = i;
+				sc->fmp->m_pkthdr.rcvif = ifp;
+				ifp->if_ipackets++;
+
+#if NBPFILTER > 0
+				/*
+				 * Handle BPF listeners. Let the BPF
+				 * user see the packet.
+				 */
+				if (ifp->if_bpf)
+					bpf_mtap(ifp->if_bpf, sc->fmp);
+#endif
+
+				ixgb_receive_checksum(sc, current_desc,
+						      sc->fmp);
+				ether_input_mbuf(ifp, sc->fmp);
+				sc->fmp = NULL;
+				sc->lmp = NULL;
+			}
+			sc->rx_buffer_area[i].m_head = NULL;
+		} else {
+			sc->dropped_pkts++;
+			if (sc->fmp != NULL)
+				m_freem(sc->fmp);
+			sc->fmp = NULL;
+			sc->lmp = NULL;
+		}
+
+		/* Zero out the receive descriptors status  */
+		current_desc->status = 0;
+		bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0,
+		    sc->rxdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+		/* Advance our pointers to the next descriptor */
+		if (++i == sc->num_rx_desc) {
+			i = 0;
+			current_desc = sc->rx_desc_base;
+		} else
+			current_desc++;
+	}
+	sc->next_rx_desc_to_check = i;
+
+	if (--i < 0)
+		i = (sc->num_rx_desc - 1);
+
+	/*
+	 * 82597EX: Workaround for redundent write back in receive descriptor ring (causes
+ 	 * memory corruption). Avoid using and re-submitting the most recently received RX
+	 * descriptor back to hardware.
+	 *
+	 * if(Last written back descriptor == EOP bit set descriptor)
+	 * 	then avoid re-submitting the most recently received RX descriptor 
+	 *	back to hardware.
+	 * if(Last written back descriptor != EOP bit set descriptor)
+	 *	then avoid re-submitting the most recently received RX descriptors
+	 * 	till last EOP bit set descriptor. 
+	 */
+	if (eop_desc != i) {
+		if (++eop_desc == sc->num_rx_desc)
+			eop_desc = 0;
+		i = eop_desc;
+	} 
+	/* Replenish the descriptors with new mbufs till last EOP bit set descriptor */
+	while (next_to_use != i) {
+		current_desc = &sc->rx_desc_base[next_to_use];
+		if ((current_desc->errors & (IXGB_RX_DESC_ERRORS_CE |
+			    IXGB_RX_DESC_ERRORS_SE | IXGB_RX_DESC_ERRORS_P |
+					     IXGB_RX_DESC_ERRORS_RXE))) {
+			mp = sc->rx_buffer_area[next_to_use].m_head;
+			ixgb_get_buf(next_to_use, sc, mp);
+		} else {
+			if (ixgb_get_buf(next_to_use, sc, NULL) == ENOBUFS)
+				break;
+		}
+		/* Advance our pointers to the next descriptor */
+		if (++next_to_use == sc->num_rx_desc) 
+			next_to_use = 0;
+	}
+	sc->next_rx_desc_to_use = next_to_use;
+	if (--next_to_use < 0)
+                next_to_use = (sc->num_rx_desc - 1);
+        /* Advance the IXGB's Receive Queue #0  "Tail Pointer" */
+        IXGB_WRITE_REG(&sc->hw, RDT, next_to_use);
+}
+
+/*********************************************************************
+ *
+ *  Verify that the hardware indicated that the checksum is valid.
+ *  Inform the stack about the status of checksum so that stack
+ *  doesn't spend time verifying the checksum.
+ *
+ *********************************************************************/
+void
+ixgb_receive_checksum(struct ixgb_softc *sc,
+		      struct ixgb_rx_desc *rx_desc,
+		      struct mbuf *mp)
+{
+	if (rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) {
+		mp->m_pkthdr.csum_flags = 0;
+		return;
+	}
+
+	if (rx_desc->status & IXGB_RX_DESC_STATUS_IPCS) {
+		/* Did it pass? */
+		if (!(rx_desc->errors & IXGB_RX_DESC_ERRORS_IPE)) {
+			/* IP Checksum Good */
+			mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK;
+
+		} else {
+			mp->m_pkthdr.csum_flags = 0;
+		}
+	}
+	if (rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS) {
+		/* Did it pass? */
+		if (!(rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE)) {
+			mp->m_pkthdr.csum_flags |=
+				M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
+		}
+	}
+}
+
+void
+ixgb_enable_intr(struct ixgb_softc *sc)
+{
+	IXGB_WRITE_REG(&sc->hw, IMS, (IXGB_INT_RXT0 | IXGB_INT_TXDW |
+			    IXGB_INT_RXDMT0 | IXGB_INT_LSC | IXGB_INT_RXO));
+}
+
+void
+ixgb_disable_intr(struct ixgb_softc *sc)
+{
+	IXGB_WRITE_REG(&sc->hw, IMC, ~0);
+}
+
+void
+ixgb_write_pci_cfg(struct ixgb_hw *hw,
+		   uint32_t reg,
+		   uint16_t *value)
+{
+	struct pci_attach_args *pa = &((struct ixgb_osdep *)hw->back)->ixgb_pa;
+	pci_chipset_tag_t pc = pa->pa_pc;
+	/* Should we do read/mask/write...?  16 vs 32 bit!!! */
+	pci_conf_write(pc, pa->pa_tag, reg, *value);
+}
+
+/**********************************************************************
+ *
+ *  Update the board statistics counters.
+ *
+ **********************************************************************/
+void
+ixgb_update_stats_counters(struct ixgb_softc *sc)
+{
+	struct ifnet   *ifp;
+
+	sc->stats.crcerrs += IXGB_READ_REG(&sc->hw, CRCERRS);
+	sc->stats.gprcl += IXGB_READ_REG(&sc->hw, GPRCL);
+	sc->stats.gprch += IXGB_READ_REG(&sc->hw, GPRCH);
+	sc->stats.gorcl += IXGB_READ_REG(&sc->hw, GORCL);
+	sc->stats.gorch += IXGB_READ_REG(&sc->hw, GORCH);
+	sc->stats.bprcl += IXGB_READ_REG(&sc->hw, BPRCL);
+	sc->stats.bprch += IXGB_READ_REG(&sc->hw, BPRCH);
+	sc->stats.mprcl += IXGB_READ_REG(&sc->hw, MPRCL);
+	sc->stats.mprch += IXGB_READ_REG(&sc->hw, MPRCH);
+	sc->stats.roc += IXGB_READ_REG(&sc->hw, ROC);
+
+	sc->stats.mpc += IXGB_READ_REG(&sc->hw, MPC);
+	sc->stats.dc += IXGB_READ_REG(&sc->hw, DC);
+	sc->stats.rlec += IXGB_READ_REG(&sc->hw, RLEC);
+	sc->stats.xonrxc += IXGB_READ_REG(&sc->hw, XONRXC);
+	sc->stats.xontxc += IXGB_READ_REG(&sc->hw, XONTXC);
+	sc->stats.xoffrxc += IXGB_READ_REG(&sc->hw, XOFFRXC);
+	sc->stats.xofftxc += IXGB_READ_REG(&sc->hw, XOFFTXC);
+	sc->stats.gptcl += IXGB_READ_REG(&sc->hw, GPTCL);
+	sc->stats.gptch += IXGB_READ_REG(&sc->hw, GPTCH);
+	sc->stats.gotcl += IXGB_READ_REG(&sc->hw, GOTCL);
+	sc->stats.gotch += IXGB_READ_REG(&sc->hw, GOTCH);
+	sc->stats.ruc += IXGB_READ_REG(&sc->hw, RUC);
+	sc->stats.rfc += IXGB_READ_REG(&sc->hw, RFC);
+	sc->stats.rjc += IXGB_READ_REG(&sc->hw, RJC);
+	sc->stats.torl += IXGB_READ_REG(&sc->hw, TORL);
+	sc->stats.torh += IXGB_READ_REG(&sc->hw, TORH);
+	sc->stats.totl += IXGB_READ_REG(&sc->hw, TOTL);
+	sc->stats.toth += IXGB_READ_REG(&sc->hw, TOTH);
+	sc->stats.tprl += IXGB_READ_REG(&sc->hw, TPRL);
+	sc->stats.tprh += IXGB_READ_REG(&sc->hw, TPRH);
+	sc->stats.tptl += IXGB_READ_REG(&sc->hw, TPTL);
+	sc->stats.tpth += IXGB_READ_REG(&sc->hw, TPTH);
+	sc->stats.plt64c += IXGB_READ_REG(&sc->hw, PLT64C);
+	sc->stats.mptcl += IXGB_READ_REG(&sc->hw, MPTCL);
+	sc->stats.mptch += IXGB_READ_REG(&sc->hw, MPTCH);
+	sc->stats.bptcl += IXGB_READ_REG(&sc->hw, BPTCL);
+	sc->stats.bptch += IXGB_READ_REG(&sc->hw, BPTCH);
+
+	sc->stats.uprcl += IXGB_READ_REG(&sc->hw, UPRCL);
+	sc->stats.uprch += IXGB_READ_REG(&sc->hw, UPRCH);
+	sc->stats.vprcl += IXGB_READ_REG(&sc->hw, VPRCL);
+	sc->stats.vprch += IXGB_READ_REG(&sc->hw, VPRCH);
+	sc->stats.jprcl += IXGB_READ_REG(&sc->hw, JPRCL);
+	sc->stats.jprch += IXGB_READ_REG(&sc->hw, JPRCH);
+	sc->stats.rnbc += IXGB_READ_REG(&sc->hw, RNBC);
+	sc->stats.icbc += IXGB_READ_REG(&sc->hw, ICBC);
+	sc->stats.ecbc += IXGB_READ_REG(&sc->hw, ECBC);
+	sc->stats.uptcl += IXGB_READ_REG(&sc->hw, UPTCL);
+	sc->stats.uptch += IXGB_READ_REG(&sc->hw, UPTCH);
+	sc->stats.vptcl += IXGB_READ_REG(&sc->hw, VPTCL);
+	sc->stats.vptch += IXGB_READ_REG(&sc->hw, VPTCH);
+	sc->stats.jptcl += IXGB_READ_REG(&sc->hw, JPTCL);
+	sc->stats.jptch += IXGB_READ_REG(&sc->hw, JPTCH);
+	sc->stats.tsctc += IXGB_READ_REG(&sc->hw, TSCTC);
+	sc->stats.tsctfc += IXGB_READ_REG(&sc->hw, TSCTFC);
+	sc->stats.ibic += IXGB_READ_REG(&sc->hw, IBIC);
+	sc->stats.lfc += IXGB_READ_REG(&sc->hw, LFC);
+	sc->stats.pfrc += IXGB_READ_REG(&sc->hw, PFRC);
+	sc->stats.pftc += IXGB_READ_REG(&sc->hw, PFTC);
+	sc->stats.mcfrc += IXGB_READ_REG(&sc->hw, MCFRC);
+
+	ifp = &sc->interface_data.ac_if;
+
+	/* Fill out the OS statistics structure */
+	ifp->if_collisions = 0;
+
+	/* Rx Errors */
+	ifp->if_ierrors =
+		sc->dropped_pkts +
+		sc->stats.crcerrs +
+		sc->stats.rnbc +
+		sc->stats.mpc +
+		sc->stats.rlec;
+
+	/* Tx Errors */
+	ifp->if_oerrors =
+		sc->watchdog_events;
+}
+
+/**********************************************************************
+ *
+ *  This routine is called only when ixgb_display_debug_stats is enabled.
+ *  This routine provides a way to take a look at important statistics
+ *  maintained by the driver and hardware.
+ *
+ **********************************************************************/
+void
+ixgb_print_hw_stats(struct ixgb_softc *sc)
+{
+	char            buf_speed[100], buf_type[100];
+	ixgb_bus_speed  bus_speed;
+	ixgb_bus_type   bus_type;
+	const char * const unit = sc->sc_dv.dv_xname;
+
+	bus_speed = sc->hw.bus.speed;
+	bus_type = sc->hw.bus.type;
+	snprintf(buf_speed, sizeof(buf_speed),
+		bus_speed == ixgb_bus_speed_33 ? "33MHz" :
+		bus_speed == ixgb_bus_speed_66 ? "66MHz" :
+		bus_speed == ixgb_bus_speed_100 ? "100MHz" :
+		bus_speed == ixgb_bus_speed_133 ? "133MHz" :
+		"UNKNOWN");
+	printf("ixgb%d: PCI_Bus_Speed = %s\n", unit,
+	       buf_speed);
+
+	snprintf(buf_type, sizeof(buf_type),
+		bus_type == ixgb_bus_type_pci ? "PCI" :
+		bus_type == ixgb_bus_type_pcix ? "PCI-X" :
+		"UNKNOWN");
+	printf("%s: PCI_Bus_Type = %s\n", unit,
+	       buf_type);
+
+	printf("%s: Tx Descriptors not Avail1 = %ld\n", unit,
+	       sc->no_tx_desc_avail1);
+	printf("%s: Tx Descriptors not Avail2 = %ld\n", unit,
+	       sc->no_tx_desc_avail2);
+	printf("%s: Std Mbuf Failed = %ld\n", unit,
+	       sc->mbuf_alloc_failed);
+	printf("%s: Std Cluster Failed = %ld\n", unit,
+	       sc->mbuf_cluster_failed);
+
+	printf("%s: Defer count = %lld\n", unit,
+	       (long long)sc->stats.dc);
+	printf("%s: Missed Packets = %lld\n", unit,
+	       (long long)sc->stats.mpc);
+	printf("%s: Receive No Buffers = %lld\n", unit,
+	       (long long)sc->stats.rnbc);
+	printf("%s: Receive length errors = %lld\n", unit,
+	       (long long)sc->stats.rlec);
+	printf("%s: Crc errors = %lld\n", unit,
+	       (long long)sc->stats.crcerrs);
+	printf("%s: Driver dropped packets = %ld\n", unit,
+	       sc->dropped_pkts);
+
+	printf("%s: XON Rcvd = %lld\n", unit,
+	       (long long)sc->stats.xonrxc);
+	printf("%s: XON Xmtd = %lld\n", unit,
+	       (long long)sc->stats.xontxc);
+	printf("%s: XOFF Rcvd = %lld\n", unit,
+	       (long long)sc->stats.xoffrxc);
+	printf("%s: XOFF Xmtd = %lld\n", unit,
+	       (long long)sc->stats.xofftxc);
+
+	printf("%s: Good Packets Rcvd = %lld\n", unit,
+	       (long long)sc->stats.gprcl);
+	printf("%s: Good Packets Xmtd = %lld\n", unit,
+	       (long long)sc->stats.gptcl);
+
+	printf("%s: Jumbo frames recvd = %lld\n", unit,
+	       (long long)sc->stats.jprcl);
+	printf("%s: Jumbo frames Xmtd = %lld\n", unit,
+	       (long long)sc->stats.jptcl);
+}
diff --git a/sys/dev/pci/if_ixgb.h b/sys/dev/pci/if_ixgb.h
new file mode 100644
index 00000000000..a2ae272e228
--- /dev/null
+++ b/sys/dev/pci/if_ixgb.h
@@ -0,0 +1,332 @@
+/**************************************************************************
+
+Copyright (c) 2001-2005, Intel Corporation
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+    contributors may be used to endorse or promote products derived from
+    this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+***************************************************************************/
+
+/* $OpenBSD: if_ixgb.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+#ifndef _IXGB_H_DEFINED_
+#define _IXGB_H_DEFINED_
+
+#include "bpfilter.h"
+#include "vlan.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#include <netinet/tcp.h>
+#include <netinet/udp.h>
+#endif
+
+#if NVLAN > 0
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/ixgb_hw.h>
+#include <dev/pci/ixgb_ee.h>
+#include <dev/pci/ixgb_ids.h>
+
+/* Tunables */
+
+/*
+ * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
+ * number of transmit descriptors allocated by the driver. Increasing this
+ * value allows the driver to queue more transmits. Each descriptor is 16
+ * bytes.
+ */
+#define IXGB_MAX_TXD                      256
+
+/*
+ * RxDescriptors Valid Range: 64-512 Default Value: 512 This value is the
+ * number of receive descriptors allocated by the driver. Increasing this
+ * value allows the driver to buffer more incoming packets. Each descriptor
+ * is 16 bytes.  A receive buffer is also allocated for each descriptor. The
+ * maximum MTU size is 16110.
+ * Note: Maximum number of receive descriptors is limited to 512 to avoid a
+ * hardware descriptor cache issue under heavy receive traffic. 
+ */
+#define IXGB_MAX_RXD                     512
+
+/*
+ * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value
+ * delays the generation of transmit interrupts in units of 1.024
+ * microseconds. Transmit interrupt reduction can improve CPU efficiency if
+ * properly tuned for specific network traffic. If the system is reporting
+ * dropped transmits, this value may be set too high causing the driver to
+ * run out of available transmit descriptors.
+ */
+#define TIDV 32
+
+/*
+ * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value
+ * delays the generation of receive interrupts in units of 1.024
+ * microseconds.  Receive interrupt reduction can improve CPU efficiency if
+ * properly tuned for specific network traffic. Increasing this value adds
+ * extra latency to frame reception and can end up decreasing the throughput
+ * of TCP traffic. If the system is reporting dropped receives, this value
+ * may be set too high, causing the driver to run out of available receive
+ * descriptors.
+ * 
+ */
+#define RDTR 72
+
+/*
+ * This parameter controls the maximum no of times the driver will loop in
+ * the isr. Minimum Value = 1
+ */
+#define IXGB_MAX_INTR                     3
+
+/*
+ * This parameter controls the duration of transmit watchdog timer.
+ */
+#define IXGB_TX_TIMEOUT                   5	/* set to 5 seconds */
+
+/*
+ * This parameter controls when the driver calls the routine to reclaim
+ * transmit descriptors.
+ */
+#define IXGB_TX_CLEANUP_THRESHOLD         IXGB_MAX_TXD / 8
+
+/* 
+ * Flow Control Types. 
+ * 1. ixgb_fc_none - Flow Control Disabled 
+ * 2. ixgb_fc_rx_pause - Flow Control Receive Only
+ * 3. ixgb_fc_tx_pause - Flow Control Transmit Only
+ * 4. ixgb_fc_full - Flow Control Enabled
+ */
+#define FLOW_CONTROL_NONE    	ixgb_fc_none 
+#define FLOW_CONTROL_RX_PAUSE   ixgb_fc_rx_pause
+#define FLOW_CONTROL_TX_PAUSE   ixgb_fc_tx_pause
+#define FLOW_CONTROL_FULL       ixgb_fc_full
+
+/*
+ * Set the flow control type. Assign one of the above flow control types to be enabled.
+ * Default Value: FLOW_CONTROL_FULL   
+ */    
+#define FLOW_CONTROL	        FLOW_CONTROL_FULL
+
+/*
+ * Receive Flow control low threshold (when we send a resume frame) (FCRTL)
+ * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be
+ * less than high threshold by at least 8 bytes Default Value:  163,840
+ * (0x28000)
+ */
+#define FCRTL                   0x28000
+
+/*
+ * Receive Flow control high threshold (when we send a pause frame) (FCRTH)
+ * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default
+ * Value: 196,608 (0x30000)
+ */
+#define FCRTH                   0x30000
+
+/*
+ * Flow control request timeout (how long to pause the link partner's tx)
+ * (PAP 15:0) Valid Range: 1 - 65535 Default Value:  256 (0x100)
+ */
+#define FCPAUSE		     0x100
+
+/* Tunables -- End */
+
+
+#define IXGB_VENDOR_ID                    0x8086
+#define IXGB_MMBA                         0x0010	/* Mem base address */
+#define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
+
+#define IOCTL_CMD_TYPE                  u_long
+#define MAX_NUM_MULTICAST_ADDRESSES     128
+#define PCI_ANY_ID                      (~0U)
+#define ETHER_ALIGN                     2
+
+/* Defines for printing debug information */
+#define DEBUG_INIT  0
+#define DEBUG_IOCTL 0
+#define DEBUG_HW    0
+
+#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
+#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
+#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
+#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
+#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
+#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
+#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
+#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
+#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
+
+
+/* Supported RX Buffer Sizes */
+#define IXGB_RXBUFFER_2048        2048
+#define IXGB_RXBUFFER_4096        4096
+#define IXGB_RXBUFFER_8192        8192
+#define IXGB_RXBUFFER_16384      16384
+
+#define IXGB_MAX_SCATTER           100
+
+struct ixgb_buffer {
+	struct mbuf    *m_head;
+	bus_dmamap_t    map;	/* bus_dma map for packet */
+};
+
+struct ixgb_q {
+	bus_dmamap_t    map;	/* bus_dma map for packet */
+};
+
+/*
+ * Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free.
+ */
+struct ixgb_dma_alloc {
+	bus_addr_t      dma_paddr;
+	caddr_t         dma_vaddr;
+	bus_dma_tag_t   dma_tag;
+	bus_dmamap_t    dma_map;
+	bus_dma_segment_t dma_seg;
+	bus_size_t      dma_size;
+	int             dma_nseg;
+};
+
+typedef enum _XSUM_CONTEXT_T {
+	OFFLOAD_NONE,
+	OFFLOAD_TCP_IP,
+	OFFLOAD_UDP_IP
+}               XSUM_CONTEXT_T;
+
+/* Our adapter structure */
+struct ixgb_softc {
+	struct device	sc_dv;
+	struct arpcom   interface_data;
+	struct ixgb_hw  hw;
+
+	/* OpenBSD operating-system-specific structures */
+	struct ixgb_osdep osdep;
+	struct ifmedia  media;
+	int             io_rid;
+
+	void            *sc_intrhand;
+	struct timeout	ixgb_intr_enable;
+	struct timeout	timer_handle;
+	void		*sc_powerhook;
+
+	/* Info about the board itself */
+	u_int32_t       part_num;
+	u_int8_t        link_active;
+	u_int16_t       link_speed;
+	u_int16_t       link_duplex;
+	u_int32_t       tx_int_delay;
+	u_int32_t       tx_abs_int_delay;
+	u_int32_t       rx_int_delay;
+	u_int32_t       rx_abs_int_delay;
+
+	int             raidc;
+
+	XSUM_CONTEXT_T  active_checksum_context;
+
+	/*
+	 * Transmit definitions
+	 * 
+	 * We have an array of num_tx_desc descriptors (handled by the
+	 * controller) paired with an array of tx_buffers (at
+	 * tx_buffer_area). The index of the next available descriptor is
+	 * next_avail_tx_desc. The number of remaining tx_desc is
+	 * num_tx_desc_avail.
+	 */
+	struct ixgb_dma_alloc txdma;	/* bus_dma glue for tx desc */
+	struct ixgb_tx_desc *tx_desc_base;
+	u_int32_t       next_avail_tx_desc;
+	u_int32_t       oldest_used_tx_desc;
+	                volatile u_int16_t num_tx_desc_avail;
+	u_int16_t       num_tx_desc;
+	u_int32_t       txd_cmd;
+	struct ixgb_buffer *tx_buffer_area;
+	bus_dma_tag_t   txtag;	/* dma tag for tx */
+
+	/*
+	 * Receive definitions
+	 * 
+	 * we have an array of num_rx_desc rx_desc (handled by the controller),
+	 * and paired with an array of rx_buffers (at rx_buffer_area). The
+	 * next pair to check on receive is at offset next_rx_desc_to_check
+	 */
+	struct ixgb_dma_alloc rxdma;	/* bus_dma glue for rx desc */
+	struct ixgb_rx_desc *rx_desc_base;
+	u_int32_t       next_rx_desc_to_check;
+	u_int16_t       num_rx_desc;
+	u_int32_t       rx_buffer_len;
+	struct ixgb_buffer *rx_buffer_area;
+	bus_dma_tag_t   rxtag;	/* dma tag for Rx */
+	u_int32_t       next_rx_desc_to_use;
+
+	/* Jumbo frame */
+	struct mbuf    *fmp;
+	struct mbuf    *lmp;
+
+	/* Misc stats maintained by the driver */
+	unsigned long   dropped_pkts;
+	unsigned long   mbuf_alloc_failed;
+	unsigned long   mbuf_cluster_failed;
+	unsigned long   no_tx_desc_avail1;
+	unsigned long   no_tx_desc_avail2;
+	unsigned long   no_tx_map_avail;
+	unsigned long   no_tx_dma_setup;
+	unsigned long	watchdog_events;
+
+	boolean_t       in_detach;
+
+	struct ixgb_hw_stats stats;
+};
+
+#endif				/* _IXGB_H_DEFINED_ */
diff --git a/sys/dev/pci/if_ixgb_osdep.h b/sys/dev/pci/if_ixgb_osdep.h
new file mode 100644
index 00000000000..e22b052d8af
--- /dev/null
+++ b/sys/dev/pci/if_ixgb_osdep.h
@@ -0,0 +1,109 @@
+/**************************************************************************
+
+Copyright (c) 2001-2005, Intel Corporation
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+    contributors may be used to endorse or promote products derived from
+    this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+***************************************************************************/
+
+/* $OpenBSD: if_ixgb_osdep.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+#ifndef _IXGB_OPENBSD_OS_H_
+#define _IXGB_OPENBSD_OS_H_
+
+#define ASSERT(x) if(!(x)) panic("IXGB: x")
+
+/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
+#define usec_delay(x) DELAY(x)
+#define msec_delay(x) DELAY(1000*(x))
+
+#define DBG 0 
+#define MSGOUT(S, A, B)     printf(S "\n", A, B)
+#define DEBUGFUNC(F)        DEBUGOUT(F);
+#if DBG
+	#define DEBUGOUT(S)         printf(S "\n")
+	#define DEBUGOUT1(S,A)      printf(S "\n",A)
+	#define DEBUGOUT2(S,A,B)    printf(S "\n",A,B)
+	#define DEBUGOUT3(S,A,B,C)  printf(S "\n",A,B,C)
+	#define DEBUGOUT7(S,A,B,C,D,E,F,G)  printf(S "\n",A,B,C,D,E,F,G)
+#else
+	#define DEBUGOUT(S)
+	#define DEBUGOUT1(S,A)
+	#define DEBUGOUT2(S,A,B)
+	#define DEBUGOUT3(S,A,B,C)
+	#define DEBUGOUT7(S,A,B,C,D,E,F,G)
+#endif
+
+#define FALSE               0
+#define TRUE                1
+#define CMD_MEM_WRT_INVALIDATE          0x0010  /* BIT_4 */
+#define PCI_COMMAND_REGISTER            PCIR_COMMAND
+
+#define le16_to_cpu 
+
+struct ixgb_osdep
+{
+	bus_space_tag_t    mem_bus_space_tag;
+	bus_space_handle_t mem_bus_space_handle;
+        struct device     *dev;
+
+        struct pci_attach_args ixgb_pa;
+
+        bus_size_t              ixgb_memsize;
+        bus_addr_t              ixgb_membase;
+};
+
+#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
+
+#define IXGB_READ_REG(a, reg)						\
+   bus_space_read_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
+                     ((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
+                     IXGB_##reg)
+
+#define IXGB_WRITE_REG(a, reg, value)					\
+   bus_space_write_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
+                     ((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
+                     IXGB_##reg, value)
+
+#define IXGB_READ_REG_ARRAY(a, reg, offset)				\
+   bus_space_read_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
+                     ((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
+                     (IXGB_##reg + ((offset) << 2)))
+
+#define IXGB_WRITE_REG_ARRAY(a, reg, offset, value)			\
+      bus_space_write_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
+                      ((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
+                      (IXGB_##reg + ((offset) << 2)), value)
+
+#ifdef DEBUG
+#define IXGB_KASSERT(exp,msg)        do { if (!(exp)) panic msg; } while (0)
+#else
+#define IXGB_KASSERT(exp,msg)
+#endif
+
+#endif  /* _IXGB_OPENBSD_OS_H_ */
diff --git a/sys/dev/pci/ixgb_ee.c b/sys/dev/pci/ixgb_ee.c
new file mode 100644
index 00000000000..2f0031d9e2a
--- /dev/null
+++ b/sys/dev/pci/ixgb_ee.c
@@ -0,0 +1,628 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2005, Intel Corporation
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived from
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/* $OpenBSD: ixgb_ee.c,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/ixgb_hw.h> 
+#include <dev/pci/ixgb_ee.h> 
+
+/* Local prototypes */
+static uint16_t ixgb_shift_in_bits(struct ixgb_hw *hw);
+
+static void ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data,
+                                uint16_t count);
+static void ixgb_standby_eeprom(struct ixgb_hw *hw);
+
+static boolean_t ixgb_wait_eeprom_command(struct ixgb_hw *hw);
+
+static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
+
+/******************************************************************************
+ * Raises the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd_reg - EECD's current value
+ *****************************************************************************/
+static void
+ixgb_raise_clock(struct ixgb_hw *hw, uint32_t *eecd_reg)
+{
+	/* Raise the clock input to the EEPROM (by setting the SK bit), and
+	 * then wait 50 microseconds. */
+	*eecd_reg = *eecd_reg | IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+	usec_delay(50);
+	return;
+}
+
+/******************************************************************************
+ * Lowers the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd_reg - EECD's current value
+ *****************************************************************************/
+static void
+ixgb_lower_clock(struct ixgb_hw *hw, uint32_t *eecd_reg)
+{
+	/* Lower the clock input to the EEPROM (by clearing the SK bit), and
+	 * then wait 50 microseconds. */
+	*eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+	usec_delay(50);
+	return;
+}
+
+/******************************************************************************
+ * Shift data bits out to the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * data - data to send to the EEPROM
+ * count - number of bits to shift out
+ *****************************************************************************/
+static void
+ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data, uint16_t count)
+{
+	uint32_t eecd_reg;
+	uint32_t mask;
+
+	/* We need to shift "count" bits out to the EEPROM. So, value in the
+	 * "data" parameter will be shifted out to the EEPROM one bit at a
+	 * time. In order to do this, "data" must be broken down into bits. */
+	mask = 0x01 << (count - 1);
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+	eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
+	do {
+		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a
+		 * "1", and then raising and then lowering the clock (the SK
+		 * bit controls the clock input to the EEPROM).  A "0" is
+		 * shifted out to the EEPROM by setting "DI" to "0" and then
+		 * raising and then lowering the clock. */
+		eecd_reg &= ~IXGB_EECD_DI;
+
+		if(data & mask)
+			eecd_reg |= IXGB_EECD_DI;
+
+		IXGB_WRITE_REG(hw, EECD, eecd_reg);
+
+		usec_delay(50);
+
+		ixgb_raise_clock(hw, &eecd_reg);
+		ixgb_lower_clock(hw, &eecd_reg);
+
+		mask = mask >> 1;
+
+	} while(mask);
+
+	/* We leave the "DI" bit set to "0" when we leave this routine. */
+	eecd_reg &= ~IXGB_EECD_DI;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	return;
+}
+
+/******************************************************************************
+ * Shift data bits in from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static uint16_t
+ixgb_shift_in_bits(struct ixgb_hw *hw)
+{
+	uint32_t eecd_reg;
+	uint32_t i;
+	uint16_t data;
+
+	/* In order to read a register from the EEPROM, we need to shift 16
+	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
+	 * input to the EEPROM (setting the SK bit), and then reading the value
+	 * of the "DO" bit.  During this "shifting in" process the "DI" bit
+	 * should always be clear.. */
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
+	data = 0;
+
+	for(i = 0; i < 16; i++) {
+		data = data << 1;
+		ixgb_raise_clock(hw, &eecd_reg);
+
+		eecd_reg = IXGB_READ_REG(hw, EECD);
+
+		eecd_reg &= ~(IXGB_EECD_DI);
+		if(eecd_reg & IXGB_EECD_DO)
+			data |= 1;
+
+		ixgb_lower_clock(hw, &eecd_reg);
+	}
+
+	return data;
+}
+
+/******************************************************************************
+ * Prepares EEPROM for access
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
+ * function should be called before issuing a command to the EEPROM.
+ *****************************************************************************/
+static void
+ixgb_setup_eeprom(struct ixgb_hw *hw)
+{
+	uint32_t eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	/* Clear SK and DI */
+	eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI);
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+
+	/* Set CS */
+	eecd_reg |= IXGB_EECD_CS;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	return;
+}
+
+/******************************************************************************
+ * Returns EEPROM to a "standby" state
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_standby_eeprom(struct ixgb_hw *hw)
+{
+	uint32_t eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	/* Deselct EEPROM */
+	eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	usec_delay(50);
+
+	/* Clock high */
+	eecd_reg |= IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	usec_delay(50);
+
+	/* Select EEPROM */
+	eecd_reg |= IXGB_EECD_CS;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	usec_delay(50);
+
+	/* Clock low */
+	eecd_reg &= ~IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	usec_delay(50);
+	return;
+}
+
+/******************************************************************************
+ * Raises then lowers the EEPROM's clock pin
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_clock_eeprom(struct ixgb_hw *hw)
+{
+	uint32_t eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	/* Rising edge of clock */
+	eecd_reg |= IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	usec_delay(50);
+
+	/* Falling edge of clock */
+	eecd_reg &= ~IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	usec_delay(50);
+	return;
+}
+
+/******************************************************************************
+ * Terminates a command by lowering the EEPROM's chip select pin
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_cleanup_eeprom(struct ixgb_hw *hw)
+{
+	uint32_t eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI);
+
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+
+	ixgb_clock_eeprom(hw);
+	return;
+}
+
+/******************************************************************************
+ * Waits for the EEPROM to finish the current command.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * The command is done when the EEPROM's data out pin goes high.
+ *
+ * Returns:
+ *      TRUE: EEPROM data pin is high before timeout.
+ *      FALSE:  Time expired.
+ *****************************************************************************/
+static boolean_t
+ixgb_wait_eeprom_command(struct ixgb_hw *hw)
+{
+	uint32_t eecd_reg;
+	uint32_t i;
+
+	/* Toggle the CS line.  This in effect tells to EEPROM to actually
+	 * execute the command in question. */
+	ixgb_standby_eeprom(hw);
+
+	/* Now read DO repeatedly until is high (equal to '1').  The EEEPROM
+	 * will signal that the command has been completed by raising the DO
+	 * signal. If DO does not go high in 10 milliseconds, then error out. */
+	for(i = 0; i < 200; i++) {
+		eecd_reg = IXGB_READ_REG(hw, EECD);
+
+		if(eecd_reg & IXGB_EECD_DO)
+			return (TRUE);
+
+		usec_delay(50);
+	}
+	ASSERT(0);
+	return (FALSE);
+}
+
+/******************************************************************************
+ * Verifies that the EEPROM has a valid checksum
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Reads the first 64 16 bit words of the EEPROM and sums the values read.
+ * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
+ * valid.
+ *
+ * Returns:
+ *  TRUE: Checksum is valid
+ *  FALSE: Checksum is not valid.
+ *****************************************************************************/
+boolean_t
+ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
+{
+	uint16_t checksum = 0;
+	uint16_t i;
+
+	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
+		checksum += ixgb_read_eeprom(hw, i);
+
+	if(checksum == (uint16_t)EEPROM_SUM)
+		return (TRUE);
+	else
+		return (FALSE);
+}
+
+/******************************************************************************
+ * Calculates the EEPROM checksum and writes it to the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
+ * Writes the difference to word offset 63 of the EEPROM.
+ *****************************************************************************/
+void
+ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
+{
+	uint16_t checksum = 0;
+	uint16_t i;
+
+	for(i = 0; i < EEPROM_CHECKSUM_REG; i++)
+		checksum += ixgb_read_eeprom(hw, i);
+
+	checksum = (uint16_t)EEPROM_SUM - checksum;
+
+	ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
+	return;
+}
+
+/******************************************************************************
+ * Writes a 16 bit word to a given offset in the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * reg - offset within the EEPROM to be written to
+ * data - 16 bit word to be writen to the EEPROM
+ *
+ * If ixgb_update_eeprom_checksum is not called after this function, the
+ * EEPROM will most likely contain an invalid checksum.
+ *
+ *****************************************************************************/
+void
+ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data)
+{
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	/* Prepare the EEPROM for writing */
+	ixgb_setup_eeprom(hw);
+
+	/* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit
+	 * opcode plus 4-bit dummy).  This puts the EEPROM into write/erase
+	 * mode. */
+	ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);
+	ixgb_shift_out_bits(hw, 0, 4);
+
+	/* Prepare the EEPROM */
+	ixgb_standby_eeprom(hw);
+
+	/* Send the Write command (3-bit opcode + 6-bit addr) */
+	ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);
+	ixgb_shift_out_bits(hw, offset, 6);
+
+	/* Send the data */
+	ixgb_shift_out_bits(hw, data, 16);
+
+	ixgb_wait_eeprom_command(hw);
+
+	/* Recover from write */
+	ixgb_standby_eeprom(hw);
+
+	/* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit
+	 * opcode plus 4-bit dummy).  This takes the EEPROM out of write/erase
+	 * mode. */
+	ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);
+	ixgb_shift_out_bits(hw, 0, 4);
+
+	/* Done with writing */
+	ixgb_cleanup_eeprom(hw);
+
+	/* clear the init_ctrl_reg_1 to signify that the cache is invalidated */
+	ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR);
+
+	return;
+}
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of 16 bit word in the EEPROM to read
+ *
+ * Returns:
+ *  The 16-bit value read from the eeprom
+ *****************************************************************************/
+uint16_t
+ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t offset)
+{
+	uint16_t data;
+
+	/* Prepare the EEPROM for reading */
+	ixgb_setup_eeprom(hw);
+
+	/* Send the READ command (opcode + addr) */
+	ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3);
+	/*
+	 * We have a 64 word EEPROM, there are 6 address bits
+	 */
+	ixgb_shift_out_bits(hw, offset, 6);
+
+	/* Read the data */
+	data = ixgb_shift_in_bits(hw);
+
+	/* End this read operation */
+	ixgb_standby_eeprom(hw);
+
+	return (data);
+}
+
+/******************************************************************************
+ * Reads eeprom and stores data in shared structure.
+ * Validates eeprom checksum and eeprom signature.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *      TRUE: if eeprom read is successful
+ *      FALSE: otherwise.
+ *****************************************************************************/
+boolean_t
+ixgb_get_eeprom_data(struct ixgb_hw *hw)
+{
+	uint16_t i;
+	uint16_t checksum = 0;
+	struct ixgb_ee_map_type *ee_map;
+
+	DEBUGFUNC("ixgb_get_eeprom_data");
+
+	ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	DEBUGOUT("ixgb_ee: Reading eeprom data\n");
+	for(i = 0; i < IXGB_EEPROM_SIZE; i++) {
+		uint16_t ee_data;
+
+		ee_data = ixgb_read_eeprom(hw, i);
+		checksum += ee_data;
+		hw->eeprom[i] = le16_to_cpu(ee_data);
+	}
+
+	if(checksum != (uint16_t)EEPROM_SUM) {
+		DEBUGOUT("ixgb_ee: Checksum invalid.\n");
+		/* clear the init_ctrl_reg_1 to signify that the cache is
+		 * invalidated */
+		ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR);
+		return (FALSE);
+	}
+
+	if((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK))
+	   != le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) {
+		DEBUGOUT("ixgb_ee: Signature invalid.\n");
+		return (FALSE);
+	}
+
+	return (TRUE);
+}
+
+/******************************************************************************
+ * Local function to check if the eeprom signature is good
+ * If the eeprom signature is good, calls ixgb)get_eeprom_data.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *      TRUE: eeprom signature was good and the eeprom read was successful
+ *      FALSE: otherwise.
+ ******************************************************************************/
+static boolean_t
+ixgb_check_and_get_eeprom_data(struct ixgb_hw *hw)
+{
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	if((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK))
+	   == le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) {
+		return (TRUE);
+	} else {
+		return ixgb_get_eeprom_data(hw);
+	}
+}
+
+/******************************************************************************
+ * return a word from the eeprom
+ *
+ * hw - Struct containing variables accessed by shared code
+ * index - Offset of eeprom word
+ *
+ * Returns:
+ *          Word at indexed offset in eeprom, if valid, 0 otherwise.
+ ******************************************************************************/
+uint16_t
+ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index)
+{
+
+	if((index < IXGB_EEPROM_SIZE) &&
+	   (ixgb_check_and_get_eeprom_data(hw) == TRUE)) {
+		return (hw->eeprom[index]);
+	}
+
+	return (0);
+}
+
+/******************************************************************************
+ * return the mac address from EEPROM
+ *
+ * hw       - Struct containing variables accessed by shared code
+ * mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise
+ *
+ * Returns: None.
+ ******************************************************************************/
+void
+ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr)
+{
+	int i;
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	DEBUGFUNC("ixgb_get_ee_mac_addr");
+
+	if(ixgb_check_and_get_eeprom_data(hw) == TRUE) {
+		for(i = 0; i < IXGB_ETH_LENGTH_OF_ADDRESS; i++) {
+			mac_addr[i] = ee_map->mac_addr[i];
+			DEBUGOUT2("mac(%d) = %.2X\n", i, mac_addr[i]);
+		}
+	}
+}
+
+
+/******************************************************************************
+ * return the Printed Board Assembly number from EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *          PBA number if EEPROM contents are valid, 0 otherwise
+ ******************************************************************************/
+uint32_t
+ixgb_get_ee_pba_number(struct ixgb_hw *hw)
+{
+	if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
+		return (le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
+			| (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG]) << 16));
+
+	return (0);
+}
+
+
+/******************************************************************************
+ * return the Device Id from EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *          Device Id if EEPROM contents are valid, 0 otherwise
+ ******************************************************************************/
+uint16_t
+ixgb_get_ee_device_id(struct ixgb_hw *hw)
+{
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
+		return (le16_to_cpu(ee_map->device_id));
+
+	return (0);
+}
+
diff --git a/sys/dev/pci/ixgb_ee.h b/sys/dev/pci/ixgb_ee.h
new file mode 100644
index 00000000000..c99529b3fee
--- /dev/null
+++ b/sys/dev/pci/ixgb_ee.h
@@ -0,0 +1,113 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2005, Intel Corporation
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived from
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/* $OpenBSD: ixgb_ee.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+#ifndef _IXGB_EE_H_
+#define _IXGB_EE_H_
+
+#define IXGB_EEPROM_SIZE    64		    /* Size in words */
+
+#define IXGB_ETH_LENGTH_OF_ADDRESS   6
+
+/* EEPROM Commands */
+#define EEPROM_READ_OPCODE  0x6		    /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE 0x5		    /* EEPROM write opcode */
+#define EEPROM_ERASE_OPCODE 0x7		    /* EEPROM erase opcode */
+#define EEPROM_EWEN_OPCODE  0x13	    /* EEPROM erase/write enable */
+#define EEPROM_EWDS_OPCODE  0x10	    /* EEPROM erase/write disable */
+
+/* EEPROM MAP (Word Offsets) */
+#define EEPROM_IA_1_2_REG        0x0000
+#define EEPROM_IA_3_4_REG        0x0001
+#define EEPROM_IA_5_6_REG        0x0002
+#define EEPROM_COMPATIBILITY_REG 0x0003
+#define EEPROM_PBA_1_2_REG       0x0008
+#define EEPROM_PBA_3_4_REG       0x0009
+#define EEPROM_INIT_CONTROL1_REG 0x000A
+#define EEPROM_SUBSYS_ID_REG     0x000B
+#define EEPROM_SUBVEND_ID_REG    0x000C
+#define EEPROM_DEVICE_ID_REG     0x000D
+#define EEPROM_VENDOR_ID_REG     0x000E
+#define EEPROM_INIT_CONTROL2_REG 0x000F
+#define EEPROM_SWDPINS_REG       0x0020
+#define EEPROM_CIRCUIT_CTRL_REG  0x0021
+#define EEPROM_D0_D3_POWER_REG   0x0022
+#define EEPROM_FLASH_VERSION     0x0032
+#define EEPROM_CHECKSUM_REG      0x003F
+
+/* Mask bits for fields in Word 0x0a of the EEPROM */
+
+#define EEPROM_ICW1_SIGNATURE_MASK  0xC000
+#define EEPROM_ICW1_SIGNATURE_VALID 0x4000
+#define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000
+
+/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
+#define EEPROM_SUM 0xBABA
+
+/* EEPROM Map Sizes (Byte Counts) */
+#define PBA_SIZE 4
+
+/* EEPROM Map defines (WORD OFFSETS)*/
+
+/* EEPROM structure */
+struct ixgb_ee_map_type {
+	uint8_t  mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
+	uint16_t compatibility;
+	uint16_t reserved1[4];
+	uint32_t pba_number;
+	uint16_t init_ctrl_reg_1;
+	uint16_t subsystem_id;
+	uint16_t subvendor_id;
+	uint16_t device_id;
+	uint16_t vendor_id;
+	uint16_t init_ctrl_reg_2;
+	uint16_t oem_reserved[16];
+	uint16_t swdpins_reg;
+	uint16_t circuit_ctrl_reg;
+	uint8_t  d3_power;
+	uint8_t  d0_power;
+	uint16_t reserved2[28];
+	uint16_t checksum;
+};
+
+/* EEPROM Functions */
+uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
+
+boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
+
+void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
+
+void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
+
+#endif /* IXGB_EE_H */
diff --git a/sys/dev/pci/ixgb_hw.c b/sys/dev/pci/ixgb_hw.c
new file mode 100644
index 00000000000..d2d5b910e0a
--- /dev/null
+++ b/sys/dev/pci/ixgb_hw.c
@@ -0,0 +1,1200 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2005, Intel Corporation
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived from
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/* $OpenBSD: ixgb_hw.c,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+/* ixgb_hw.c
+ * Shared functions for accessing and configuring the adapter
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/ixgb_hw.h> 
+#include <dev/pci/ixgb_ids.h> 
+
+/*  Local function prototypes */
+
+static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr);
+
+static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
+
+static void ixgb_get_bus_info(struct ixgb_hw *hw);
+
+static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
+
+static void ixgb_optics_reset(struct ixgb_hw *hw);
+
+static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
+
+uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
+
+uint32_t
+ixgb_mac_reset(struct ixgb_hw *hw)
+{
+	uint32_t ctrl_reg;
+
+    ctrl_reg =  IXGB_CTRL0_RST |
+                IXGB_CTRL0_SDP3_DIR |   /* All pins are Output=1 */
+                IXGB_CTRL0_SDP2_DIR |
+                IXGB_CTRL0_SDP1_DIR |
+                IXGB_CTRL0_SDP0_DIR |
+                IXGB_CTRL0_SDP3     |   /* Initial value 1101   */
+                IXGB_CTRL0_SDP2     |
+                IXGB_CTRL0_SDP0;
+
+#ifdef HP_ZX1
+	/* Workaround for 82597EX reset errata */
+	IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
+#else
+	IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
+#endif
+
+	/* Delay a few ms just to allow the reset to complete */
+	msec_delay(IXGB_DELAY_AFTER_RESET);
+	ctrl_reg = IXGB_READ_REG(hw, CTRL0);
+#ifdef DBG
+	/* Make sure the self-clearing global reset bit did self clear */
+	ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
+#endif
+
+	if(hw->phy_type == ixgb_phy_type_txn17401) {
+		ixgb_optics_reset(hw);
+	}
+
+	return ctrl_reg;
+}
+
+/******************************************************************************
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+boolean_t
+ixgb_adapter_stop(struct ixgb_hw *hw)
+{
+	uint32_t ctrl_reg;
+	uint32_t icr_reg;
+
+	DEBUGFUNC("ixgb_adapter_stop");
+
+	/* If we are stopped or resetting exit gracefully and wait to be
+	 * started again before accessing the hardware. */
+	if(hw->adapter_stopped) {
+		DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
+		return FALSE;
+	}
+
+	/* Set the Adapter Stopped flag so other driver functions stop touching
+	 * the Hardware. */
+	hw->adapter_stopped = TRUE;
+
+	/* Clear interrupt mask to stop board from generating interrupts */
+	DEBUGOUT("Masking off all interrupts\n");
+	IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
+
+	/* Disable the Transmit and Receive units.  Then delay to allow any
+	 * pending transactions to complete before we hit the MAC with the
+	 * global reset. */
+	IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
+	IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
+	msec_delay(IXGB_DELAY_BEFORE_RESET);
+
+	/* Issue a global reset to the MAC.  This will reset the chip's
+	 * transmit, receive, DMA, and link units.  It will not effect the
+	 * current PCI configuration.  The global reset bit is self- clearing,
+	 * and should clear within a microsecond. */
+	DEBUGOUT("Issuing a global reset to MAC\n");
+
+	ctrl_reg = ixgb_mac_reset(hw);
+
+	/* Clear interrupt mask to stop board from generating interrupts */
+	DEBUGOUT("Masking off all interrupts\n");
+	IXGB_WRITE_REG(hw, IMC, 0xffffffff);
+
+	/* Clear any pending interrupt events. */
+	icr_reg = IXGB_READ_REG(hw, ICR);
+
+	return (ctrl_reg & IXGB_CTRL0_RST);
+}
+
+/******************************************************************************
+ * Identifies the vendor of the optics module on the adapter.  The SR adapters
+ * support two different types of XPAK optics, so it is necessary to determine
+ * which optics are present before applying any optics-specific workarounds.
+ *
+ * hw - Struct containing variables accessed by shared code.
+ *
+ * Returns: the vendor of the XPAK optics module.
+ *****************************************************************************/
+static ixgb_xpak_vendor
+ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
+{
+	uint32_t i;
+	uint16_t vendor_name[5];
+	ixgb_xpak_vendor xpak_vendor;
+
+	DEBUGFUNC("ixgb_identify_xpak_vendor");
+
+	/* Read the first few bytes of the vendor string from the XPAK NVR
+	 * registers.  These are standard XENPAK/XPAK registers, so all XPAK
+	 * devices should implement them. */
+	for(i = 0; i < 5; i++) {
+		vendor_name[i] =
+			ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i,
+					  IXGB_PHY_ADDRESS, MDIO_PMA_PMD_DID);
+	}
+
+	/* Determine the actual vendor */
+	if (vendor_name[0] == 'I' &&
+	    vendor_name[1] == 'N' &&
+	    vendor_name[2] == 'T' &&
+	    vendor_name[3] == 'E' &&
+	    vendor_name[4] == 'L') {
+	    xpak_vendor = ixgb_xpak_vendor_intel;
+	}
+	else {
+		xpak_vendor = ixgb_xpak_vendor_infineon;
+	}
+	return (xpak_vendor);
+}
+
+/******************************************************************************
+ * Determine the physical layer module on the adapter.
+ *
+ * hw - Struct containing variables accessed by shared code.  The device_id
+ *      field must be (correctly) populated before calling this routine.
+ *
+ * Returns: the phy type of the adapter.
+ *****************************************************************************/
+static ixgb_phy_type
+ixgb_identify_phy(struct ixgb_hw *hw)
+{
+	ixgb_phy_type phy_type;
+	ixgb_xpak_vendor xpak_vendor;
+
+	DEBUGFUNC("ixgb_identify_phy");
+
+	/* Infer the transceiver/phy type from the device id */
+	switch(hw->device_id) {
+	case IXGB_DEVICE_ID_82597EX:
+		DEBUGOUT("Identified TXN17401 optics\n");
+		phy_type = ixgb_phy_type_txn17401;
+		break;
+
+	case IXGB_DEVICE_ID_82597EX_SR:
+		/* The SR adapters carry two different types of XPAK optics
+		 * modules; read the vendor identifier to determine the exact
+		 * type of optics. */
+		xpak_vendor = ixgb_identify_xpak_vendor(hw);
+		if(xpak_vendor == ixgb_xpak_vendor_intel) {
+			DEBUGOUT("Identified TXN17201 optics\n");
+			phy_type = ixgb_phy_type_txn17201;
+		} else {
+			DEBUGOUT("Identified G6005 optics\n");
+			phy_type = ixgb_phy_type_g6005;
+		}
+		break;
+
+	case IXGB_DEVICE_ID_82597EX_LR:
+		DEBUGOUT("Identified G6104 optics\n");
+		phy_type = ixgb_phy_type_g6104;
+		break;
+
+	default:
+		DEBUGOUT("Unknown physical layer module\n");
+		phy_type = ixgb_phy_type_unknown;
+		break;
+	}
+
+	return (phy_type);
+}
+
+/******************************************************************************
+ * Performs basic configuration of the adapter.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Resets the controller.
+ * Reads and validates the EEPROM.
+ * Initializes the receive address registers.
+ * Initializes the multicast table.
+ * Clears all on-chip counters.
+ * Calls routine to setup flow control settings.
+ * Leaves the transmit and receive units disabled and uninitialized.
+ *
+ * Returns:
+ *      TRUE if successful,
+ *      FALSE if unrecoverable problems were encountered.
+ *****************************************************************************/
+boolean_t
+ixgb_init_hw(struct ixgb_hw *hw)
+{
+	uint32_t i;
+	uint32_t ctrl_reg;
+	boolean_t status;
+
+	DEBUGFUNC("ixgb_init_hw");
+
+	/* Issue a global reset to the MAC.  This will reset the chip's
+	 * transmit, receive, DMA, and link units.  It will not effect the
+	 * current PCI configuration.  The global reset bit is self- clearing,
+	 * and should clear within a microsecond. */
+	DEBUGOUT("Issuing a global reset to MAC\n");
+
+	ctrl_reg = ixgb_mac_reset(hw);
+
+	DEBUGOUT("Issuing an EE reset to MAC\n");
+#ifdef HP_ZX1
+	/* Workaround for 82597EX reset errata */
+	IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
+#else
+	IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
+#endif
+
+	/* Delay a few ms just to allow the reset to complete */
+	msec_delay(IXGB_DELAY_AFTER_EE_RESET);
+
+	if(ixgb_get_eeprom_data(hw) == FALSE) {
+		return (FALSE);
+	}
+
+	/* Use the device id to determine the type of phy/transceiver. */
+	hw->device_id = ixgb_get_ee_device_id(hw);
+	hw->phy_type = ixgb_identify_phy(hw);
+
+	/* Setup the receive addresses. Receive Address Registers (RARs 0 -
+	 * 15). */
+	ixgb_init_rx_addrs(hw);
+
+	/*
+	 * Check that a valid MAC address has been set.
+	 * If it is not valid, we fail hardware init.
+	 */
+	if(!mac_addr_valid(hw->curr_mac_addr)) {
+		DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
+		return (FALSE);
+	}
+
+	/* tell the routines in this file they can access hardware again */
+	hw->adapter_stopped = FALSE;
+
+	/* Fill in the bus_info structure */
+	ixgb_get_bus_info(hw);
+
+	/* Zero out the Multicast HASH table */
+	DEBUGOUT("Zeroing the MTA\n");
+	for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
+		IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
+
+	/* Zero out the VLAN Filter Table Array */
+	ixgb_clear_vfta(hw);
+
+	/* Zero all of the hardware counters */
+	ixgb_clear_hw_cntrs(hw);
+
+	/* Call a subroutine to setup flow control. */
+	status = ixgb_setup_fc(hw);
+
+	/* 82597EX errata: Call check-for-link in case lane deskew is locked */
+	ixgb_check_for_link(hw);
+
+	return (status);
+}
+
+/******************************************************************************
+ * Initializes receive address filters.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Places the MAC address in receive address register 0 and clears the rest
+ * of the receive addresss registers. Clears the multicast table. Assumes
+ * the receiver is in reset when the routine is called.
+ *****************************************************************************/
+void
+ixgb_init_rx_addrs(struct ixgb_hw *hw)
+{
+	uint32_t i;
+
+	DEBUGFUNC("ixgb_init_rx_addrs");
+
+	/*
+	 * If the current mac address is valid, assume it is a software override
+	 * to the permanent address.
+	 * Otherwise, use the permanent address from the eeprom.
+	 */
+	if(!mac_addr_valid(hw->curr_mac_addr)) {
+
+		/* Get the MAC address from the eeprom for later reference */
+		ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
+
+		DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
+			  hw->curr_mac_addr[0], hw->curr_mac_addr[1],
+			  hw->curr_mac_addr[2]);
+		DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
+			  hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
+	} else {
+
+		/* Setup the receive address. */
+		DEBUGOUT("Overriding MAC Address in RAR[0]\n");
+		DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
+			  hw->curr_mac_addr[0], hw->curr_mac_addr[1],
+			  hw->curr_mac_addr[2]);
+		DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
+			  hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
+
+		ixgb_rar_set(hw, hw->curr_mac_addr, 0);
+	}
+
+	/* Zero out the other 15 receive addresses. */
+	DEBUGOUT("Clearing RAR[1-15]\n");
+	for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
+		IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+		IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+	}
+
+	return;
+}
+
+/******************************************************************************
+ * Updates the MAC's list of multicast addresses.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * mc_addr_list - the list of new multicast addresses
+ * mc_addr_count - number of addresses
+ * pad - number of bytes between addresses in the list
+ *
+ * The given list replaces any existing list. Clears the last 15 receive
+ * address registers and the multicast table. Uses receive address registers
+ * for the first 15 multicast addresses, and hashes the rest into the
+ * multicast table.
+ *****************************************************************************/
+void
+ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
+			 uint32_t mc_addr_count, uint32_t pad)
+{
+	uint32_t hash_value;
+	uint32_t i;
+	uint32_t rar_used_count = 1;	/* RAR[0] is used for our MAC address */
+
+	DEBUGFUNC("ixgb_mc_addr_list_update");
+
+	/* Set the new number of MC addresses that we are being requested to
+	 * use. */
+	hw->num_mc_addrs = mc_addr_count;
+
+	/* Clear RAR[1-15] */
+	DEBUGOUT(" Clearing RAR[1-15]\n");
+	for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
+		IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+		IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+	}
+
+	/* Clear the MTA */
+	DEBUGOUT(" Clearing MTA\n");
+	for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
+		IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
+	}
+
+	/* Add the new addresses */
+	for(i = 0; i < mc_addr_count; i++) {
+		DEBUGOUT(" Adding the multicast addresses:\n");
+		DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
+			  mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
+			  mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1],
+			  mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2],
+			  mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3],
+			  mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4],
+			  mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]);
+
+		/* Place this multicast address in the RAR if there is room, *
+		 * else put it in the MTA */
+		if(rar_used_count < IXGB_RAR_ENTRIES) {
+			ixgb_rar_set(hw,
+				     mc_addr_list +
+				     (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
+				     rar_used_count);
+			DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
+			rar_used_count++;
+		} else {
+			hash_value =
+				ixgb_hash_mc_addr(hw,
+						  mc_addr_list +
+						  (i *
+						   (IXGB_ETH_LENGTH_OF_ADDRESS +
+						    pad)));
+
+			DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
+
+			ixgb_mta_set(hw, hash_value);
+		}
+	}
+
+	DEBUGOUT("MC Update Complete\n");
+	return;
+}
+
+/******************************************************************************
+ * Hashes an address to determine its location in the multicast table
+ *
+ * hw - Struct containing variables accessed by shared code
+ * mc_addr - the multicast address to hash
+ *
+ * Returns:
+ *      The hash value
+ *****************************************************************************/
+static uint32_t
+ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr)
+{
+	uint32_t hash_value = 0;
+
+	DEBUGFUNC("ixgb_hash_mc_addr");
+
+	/* The portion of the address that is used for the hash table is
+	 * determined by the mc_filter_type setting. */
+	switch(hw->mc_filter_type) {
+		/* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB -
+		 * According to H/W docs */
+	case 0:
+		/* [47:36] i.e. 0x563 for above example address */
+		hash_value =
+			((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4));
+		break;
+	case 1:			    /* [46:35] i.e. 0xAC6 for above
+					     * example address */
+		hash_value =
+			((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5));
+		break;
+	case 2:			    /* [45:34] i.e. 0x5D8 for above
+					     * example address */
+		hash_value =
+			((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6));
+		break;
+	case 3:			    /* [43:32] i.e. 0x634 for above
+					     * example address */
+		hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8));
+		break;
+	default:
+		/* Invalid mc_filter_type, what should we do? */
+		DEBUGOUT("MC filter type param set incorrectly\n");
+		ASSERT(0);
+		break;
+	}
+
+	hash_value &= 0xFFF;
+	return (hash_value);
+}
+
+/******************************************************************************
+ * Sets the bit in the multicast table corresponding to the hash value.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * hash_value - Multicast address hash value
+ *****************************************************************************/
+static void
+ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)
+{
+	uint32_t hash_bit, hash_reg;
+	uint32_t mta_reg;
+
+	/* The MTA is a register array of 128 32-bit registers. It is treated
+	 * like an array of 4096 bits.  We want to set bit
+	 * BitArray[hash_value]. So we figure out what register the bit is in,
+	 * read it, OR in the new bit, then write back the new value.  The
+	 * register is determined by the upper 7 bits of the hash value and the
+	 * bit within that register are determined by the lower 5 bits of the
+	 * value. */
+	hash_reg = (hash_value >> 5) & 0x7F;
+	hash_bit = hash_value & 0x1F;
+	mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
+	mta_reg |= (1 << hash_bit);
+	IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
+	return;
+}
+
+/******************************************************************************
+ * Puts an ethernet address into a receive address register.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * addr - Address to put into receive address register
+ * index - Receive address register to write
+ *****************************************************************************/
+void
+ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index)
+{
+	uint32_t rar_low, rar_high;
+
+	DEBUGFUNC("ixgb_rar_set");
+
+	/* HW expects these in little endian so we reverse the byte order from
+	 * network order (big endian) to little endian */
+	rar_low = ((uint32_t)addr[0] |
+	          ((uint32_t)addr[1] << 8) |
+	          ((uint32_t)addr[2] << 16) |
+	          ((uint32_t)addr[3] << 24));
+
+	rar_high = ((uint32_t)addr[4] |
+	           ((uint32_t)addr[5] << 8) |
+	            IXGB_RAH_AV);
+
+	IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
+	IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
+	return;
+}
+
+/******************************************************************************
+ * Writes a value to the specified offset in the VLAN filter table.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - Offset in VLAN filer table to write
+ * value - Value to write into VLAN filter table
+ *****************************************************************************/
+void
+ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value)
+{
+	IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+	return;
+}
+
+/******************************************************************************
+ * Clears the VLAN filer table
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+ixgb_clear_vfta(struct ixgb_hw *hw)
+{
+	uint32_t offset;
+
+	for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
+		IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
+	return;
+}
+
+/******************************************************************************
+ * Configures the flow control settings based on SW configuration.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+
+boolean_t
+ixgb_setup_fc(struct ixgb_hw *hw)
+{
+	uint32_t ctrl_reg;
+	uint32_t pap_reg = 0;	/* by default, assume no pause time */
+	boolean_t status = TRUE;
+
+	DEBUGFUNC("ixgb_setup_fc");
+
+	/* Get the current control reg 0 settings */
+	ctrl_reg = IXGB_READ_REG(hw, CTRL0);
+
+	/* Clear the Receive Pause Enable and Transmit Pause Enable bits */
+	ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
+
+	/* The possible values of the "flow_control" parameter are:
+	 * 0: Flow control is completely disabled
+	 * 1: Rx flow control is enabled (we can receive pause frames but not send
+	 *    pause frames).
+	 * 2: Tx flow control is enabled (we can send pause frames but we do not
+	 *    support receiving pause frames)
+	 * 3: Both Rx and TX flow control (symmetric) are enabled.
+	 * other: Invalid. */
+	switch(hw->fc.type) {
+	case ixgb_fc_none:		    /* 0 */
+		/* Set CMDC bit to disable Rx Flow control */
+		ctrl_reg |= (IXGB_CTRL0_CMDC);
+		break;
+	case ixgb_fc_rx_pause:		    /* 1 */
+		/* RX Flow control is enabled, and TX Flow control is disabled. */
+		ctrl_reg |= (IXGB_CTRL0_RPE);
+		break;
+	case ixgb_fc_tx_pause:		    /* 2 */
+		/* TX Flow control is enabled, and RX Flow control is disabled,
+		 * by a software over-ride. */
+		ctrl_reg |= (IXGB_CTRL0_TPE);
+		pap_reg = hw->fc.pause_time;
+		break;
+	case ixgb_fc_full:		    /* 3 */
+		/* Flow control (both RX and TX) is enabled by a software
+		 * over-ride. */
+		ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
+		pap_reg = hw->fc.pause_time;
+		break;
+	default:
+		/* We should never get here.  The value should be 0-3. */
+		DEBUGOUT("Flow control param set incorrectly\n");
+		ASSERT(0);
+		break;
+	}
+
+	/* Write the new settings */
+	IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
+
+	if(pap_reg != 0) {
+		IXGB_WRITE_REG(hw, PAP, pap_reg);
+	}
+
+	/* Set the flow control receive threshold registers.  Normally, these
+	 * registers will be set to a default threshold that may be adjusted
+	 * later by the driver's runtime code.  However, if the ability to
+	 * transmit pause frames in not enabled, then these registers will be
+	 * set to 0. */
+	if(!(hw->fc.type & ixgb_fc_tx_pause)) {
+		IXGB_WRITE_REG(hw, FCRTL, 0);
+		IXGB_WRITE_REG(hw, FCRTH, 0);
+	} else {
+		/* We need to set up the Receive Threshold high and low water
+		 * marks as well as (optionally) enabling the transmission of
+		 * XON frames. */
+		if(hw->fc.send_xon) {
+			IXGB_WRITE_REG(hw, FCRTL,
+				       (hw->fc.low_water | IXGB_FCRTL_XONE));
+		} else {
+			IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
+		}
+		IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
+	}
+	return (status);
+}
+
+/******************************************************************************
+ * Reads a word from a device over the Management Data Interface (MDI) bus.
+ * This interface is used to manage Physical layer devices.
+ *
+ * hw          - Struct containing variables accessed by hw code
+ * reg_address - Offset of device register being read.
+ * phy_address - Address of device on MDI.
+ *
+ * Returns:  Data word (16 bits) from MDI device.
+ *
+ * The 82597EX has support for several MDI access methods.  This routine
+ * uses the new protocol MDI Single Command and Address Operation.
+ * This requires that first an address cycle command is sent, followed by a
+ * read command.
+ *****************************************************************************/
+uint16_t
+ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
+		  uint32_t phy_address, uint32_t device_type)
+{
+	uint32_t i;
+	uint32_t data;
+	uint32_t command = 0;
+
+	ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
+	ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
+	ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
+
+	/* Setup and write the address cycle command */
+	command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT)  |
+	           (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
+	           (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
+	           (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
+
+	IXGB_WRITE_REG(hw, MSCA, command);
+
+    /**************************************************************
+    ** Check every 10 usec to see if the address cycle completed
+    ** The COMMAND bit will clear when the operation is complete.
+    ** This may take as long as 64 usecs (we'll wait 100 usecs max)
+    ** from the CPU Write to the Ready bit assertion.
+    **************************************************************/
+
+	for(i = 0; i < 10; i++) {
+		usec_delay(10);
+
+		command = IXGB_READ_REG(hw, MSCA);
+
+		if((command & IXGB_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
+
+	ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
+
+	/* Address cycle complete, setup and write the read command */
+	command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT)  |
+	           (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
+	           (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
+	           (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
+
+	IXGB_WRITE_REG(hw, MSCA, command);
+
+    /**************************************************************
+    ** Check every 10 usec to see if the read command completed
+    ** The COMMAND bit will clear when the operation is complete.
+    ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
+    ** from the CPU Write to the Ready bit assertion.
+    **************************************************************/
+
+	for(i = 0; i < 10; i++) {
+		usec_delay(10);
+
+		command = IXGB_READ_REG(hw, MSCA);
+
+		if((command & IXGB_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
+
+	ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
+
+	/* Operation is complete, get the data from the MDIO Read/Write Data
+	 * register and return. */
+	data = IXGB_READ_REG(hw, MSRWD);
+	data >>= IXGB_MSRWD_READ_DATA_SHIFT;
+	return ((uint16_t)data);
+}
+
+/******************************************************************************
+ * Writes a word to a device over the Management Data Interface (MDI) bus.
+ * This interface is used to manage Physical layer devices.
+ *
+ * hw          - Struct containing variables accessed by hw code
+ * reg_address - Offset of device register being read.
+ * phy_address - Address of device on MDI.
+ * device_type - Also known as the Device ID or DID.
+ * data        - 16-bit value to be written
+ *
+ * Returns:  void.
+ *
+ * The 82597EX has support for several MDI access methods.  This routine
+ * uses the new protocol MDI Single Command and Address Operation.
+ * This requires that first an address cycle command is sent, followed by a
+ * write command.
+ *****************************************************************************/
+void
+ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
+                   uint32_t phy_address, uint32_t device_type, uint16_t data)
+{
+	uint32_t i;
+	uint32_t command = 0;
+
+	ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
+	ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
+	ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
+
+	/* Put the data in the MDIO Read/Write Data register */
+	IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
+
+	/* Setup and write the address cycle command */
+	command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT)  |
+	           (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
+	           (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
+	           (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
+
+	IXGB_WRITE_REG(hw, MSCA, command);
+
+    /**************************************************************
+    ** Check every 10 usec to see if the address cycle completed
+    ** The COMMAND bit will clear when the operation is complete.
+    ** This may take as long as 64 usecs (we'll wait 100 usecs max)
+    ** from the CPU Write to the Ready bit assertion.
+    **************************************************************/
+
+	for(i = 0; i < 10; i++) {
+		usec_delay(10);
+
+		command = IXGB_READ_REG(hw, MSCA);
+
+		if((command & IXGB_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
+
+	ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
+
+	/* Address cycle complete, setup and write the write command */
+	command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT)  |
+	           (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
+	           (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
+	           (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
+
+	IXGB_WRITE_REG(hw, MSCA, command);
+
+    /**************************************************************
+    ** Check every 10 usec to see if the read command completed
+    ** The COMMAND bit will clear when the operation is complete.
+    ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
+    ** from the CPU Write to the Ready bit assertion.
+    **************************************************************/
+
+	for(i = 0; i < 10; i++) {
+		usec_delay(10);
+
+		command = IXGB_READ_REG(hw, MSCA);
+
+		if((command & IXGB_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
+
+	ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
+
+	/* Operation is complete, return. */
+}
+
+/******************************************************************************
+ * Checks to see if the link status of the hardware has changed.
+ *
+ * hw - Struct containing variables accessed by hw code
+ *
+ * Called by any function that needs to check the link status of the adapter.
+ *****************************************************************************/
+void
+ixgb_check_for_link(struct ixgb_hw *hw)
+{
+	uint32_t status_reg;
+	uint32_t xpcss_reg;
+
+	DEBUGFUNC("ixgb_check_for_link");
+
+	xpcss_reg = IXGB_READ_REG(hw, XPCSS);
+	status_reg = IXGB_READ_REG(hw, STATUS);
+
+	if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
+	   (status_reg & IXGB_STATUS_LU)) {
+		hw->link_up = TRUE;
+	} else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
+		  (status_reg & IXGB_STATUS_LU)) {
+		DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
+		hw->link_up = ixgb_link_reset(hw);
+	} else {
+		/*
+		 * 82597EX errata.  Since the lane deskew problem may prevent
+		 * link, reset the link before reporting link down.
+		 */
+		hw->link_up = ixgb_link_reset(hw);
+	}
+	/* Anything else for 10 Gig?? */
+}
+
+/******************************************************************************
+ * Check for a bad link condition that may have occured.
+ * The indication is that the RFC / LFC registers may be incrementing
+ * continually.  A full adapter reset is required to recover.
+ *
+ * hw - Struct containing variables accessed by hw code
+ *
+ * Called by any function that needs to check the link status of the adapter.
+ *****************************************************************************/
+boolean_t
+ixgb_check_for_bad_link(struct ixgb_hw *hw)
+{
+	uint32_t newLFC, newRFC;
+	boolean_t bad_link_returncode = FALSE;
+
+	if(hw->phy_type == ixgb_phy_type_txn17401) {
+		newLFC = IXGB_READ_REG(hw, LFC);
+		newRFC = IXGB_READ_REG(hw, RFC);
+		if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) {
+			DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n");
+			bad_link_returncode = TRUE;
+		}
+		hw->lastLFC = newLFC;
+		hw->lastRFC = newRFC;
+	}
+
+	return bad_link_returncode;
+}
+
+/******************************************************************************
+ * Clears all hardware statistics counters.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
+{
+	volatile uint32_t temp_reg;
+
+	DEBUGFUNC("ixgb_clear_hw_cntrs");
+
+	/* if we are stopped or resetting exit gracefully */
+	if(hw->adapter_stopped) {
+		DEBUGOUT("Exiting because the adapter is stopped!!!\n");
+		return;
+	}
+
+	temp_reg = IXGB_READ_REG(hw, TPRL);
+	temp_reg = IXGB_READ_REG(hw, TPRH);
+	temp_reg = IXGB_READ_REG(hw, GPRCL);
+	temp_reg = IXGB_READ_REG(hw, GPRCH);
+	temp_reg = IXGB_READ_REG(hw, BPRCL);
+	temp_reg = IXGB_READ_REG(hw, BPRCH);
+	temp_reg = IXGB_READ_REG(hw, MPRCL);
+	temp_reg = IXGB_READ_REG(hw, MPRCH);
+	temp_reg = IXGB_READ_REG(hw, UPRCL);
+	temp_reg = IXGB_READ_REG(hw, UPRCH);
+	temp_reg = IXGB_READ_REG(hw, VPRCL);
+	temp_reg = IXGB_READ_REG(hw, VPRCH);
+	temp_reg = IXGB_READ_REG(hw, JPRCL);
+	temp_reg = IXGB_READ_REG(hw, JPRCH);
+	temp_reg = IXGB_READ_REG(hw, GORCL);
+	temp_reg = IXGB_READ_REG(hw, GORCH);
+	temp_reg = IXGB_READ_REG(hw, TORL);
+	temp_reg = IXGB_READ_REG(hw, TORH);
+	temp_reg = IXGB_READ_REG(hw, RNBC);
+	temp_reg = IXGB_READ_REG(hw, RUC);
+	temp_reg = IXGB_READ_REG(hw, ROC);
+	temp_reg = IXGB_READ_REG(hw, RLEC);
+	temp_reg = IXGB_READ_REG(hw, CRCERRS);
+	temp_reg = IXGB_READ_REG(hw, ICBC);
+	temp_reg = IXGB_READ_REG(hw, ECBC);
+	temp_reg = IXGB_READ_REG(hw, MPC);
+	temp_reg = IXGB_READ_REG(hw, TPTL);
+	temp_reg = IXGB_READ_REG(hw, TPTH);
+	temp_reg = IXGB_READ_REG(hw, GPTCL);
+	temp_reg = IXGB_READ_REG(hw, GPTCH);
+	temp_reg = IXGB_READ_REG(hw, BPTCL);
+	temp_reg = IXGB_READ_REG(hw, BPTCH);
+	temp_reg = IXGB_READ_REG(hw, MPTCL);
+	temp_reg = IXGB_READ_REG(hw, MPTCH);
+	temp_reg = IXGB_READ_REG(hw, UPTCL);
+	temp_reg = IXGB_READ_REG(hw, UPTCH);
+	temp_reg = IXGB_READ_REG(hw, VPTCL);
+	temp_reg = IXGB_READ_REG(hw, VPTCH);
+	temp_reg = IXGB_READ_REG(hw, JPTCL);
+	temp_reg = IXGB_READ_REG(hw, JPTCH);
+	temp_reg = IXGB_READ_REG(hw, GOTCL);
+	temp_reg = IXGB_READ_REG(hw, GOTCH);
+	temp_reg = IXGB_READ_REG(hw, TOTL);
+	temp_reg = IXGB_READ_REG(hw, TOTH);
+	temp_reg = IXGB_READ_REG(hw, DC);
+	temp_reg = IXGB_READ_REG(hw, PLT64C);
+	temp_reg = IXGB_READ_REG(hw, TSCTC);
+	temp_reg = IXGB_READ_REG(hw, TSCTFC);
+	temp_reg = IXGB_READ_REG(hw, IBIC);
+	temp_reg = IXGB_READ_REG(hw, RFC);
+	temp_reg = IXGB_READ_REG(hw, LFC);
+	temp_reg = IXGB_READ_REG(hw, PFRC);
+	temp_reg = IXGB_READ_REG(hw, PFTC);
+	temp_reg = IXGB_READ_REG(hw, MCFRC);
+	temp_reg = IXGB_READ_REG(hw, MCFTC);
+	temp_reg = IXGB_READ_REG(hw, XONRXC);
+	temp_reg = IXGB_READ_REG(hw, XONTXC);
+	temp_reg = IXGB_READ_REG(hw, XOFFRXC);
+	temp_reg = IXGB_READ_REG(hw, XOFFTXC);
+	temp_reg = IXGB_READ_REG(hw, RJC);
+	return;
+}
+
+/******************************************************************************
+ * Turns on the software controllable LED
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+ixgb_led_on(struct ixgb_hw *hw)
+{
+	uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
+
+	/* To turn on the LED, clear software-definable pin 0 (SDP0). */
+	ctrl0_reg &= ~IXGB_CTRL0_SDP0;
+	IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
+	return;
+}
+
+/******************************************************************************
+ * Turns off the software controllable LED
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+ixgb_led_off(struct ixgb_hw *hw)
+{
+	uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
+
+	/* To turn off the LED, set software-definable pin 0 (SDP0). */
+	ctrl0_reg |= IXGB_CTRL0_SDP0;
+	IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
+	return;
+}
+
+/******************************************************************************
+ * Gets the current PCI bus type, speed, and width of the hardware
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_get_bus_info(struct ixgb_hw *hw)
+{
+	uint32_t status_reg;
+
+	status_reg = IXGB_READ_REG(hw, STATUS);
+
+	hw->bus.type =
+		(status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_bus_type_pcix :
+		ixgb_bus_type_pci;
+
+	if(hw->bus.type == ixgb_bus_type_pci) {
+		hw->bus.speed =
+			(status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_bus_speed_66 :
+			ixgb_bus_speed_33;
+	} else {
+		switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
+		case IXGB_STATUS_PCIX_SPD_66:
+			hw->bus.speed = ixgb_bus_speed_66;
+			break;
+		case IXGB_STATUS_PCIX_SPD_100:
+			hw->bus.speed = ixgb_bus_speed_100;
+			break;
+		case IXGB_STATUS_PCIX_SPD_133:
+			hw->bus.speed = ixgb_bus_speed_133;
+			break;
+		default:
+			hw->bus.speed = ixgb_bus_speed_reserved;
+			break;
+		}
+	}
+
+	hw->bus.width =
+		(status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 :
+		ixgb_bus_width_32;
+
+	return;
+}
+
+/******************************************************************************
+ * Tests a MAC address to ensure it is a valid Individual Address
+ *
+ * mac_addr - pointer to MAC address.
+ *
+ *****************************************************************************/
+boolean_t
+mac_addr_valid(uint8_t *mac_addr)
+{
+	boolean_t is_valid = TRUE;
+
+	DEBUGFUNC("mac_addr_valid");
+
+	/* Make sure it is not a multicast address */
+	if(IS_MULTICAST(mac_addr)) {
+		DEBUGOUT("MAC address is multicast\n");
+		is_valid = FALSE;
+	}
+	/* Not a broadcast address */
+	else if(IS_BROADCAST(mac_addr)) {
+		DEBUGOUT("MAC address is broadcast\n");
+		is_valid = FALSE;
+	}
+	/* Reject the zero address */
+	else if (mac_addr[0] == 0 &&
+	         mac_addr[1] == 0 &&
+	         mac_addr[2] == 0 &&
+	         mac_addr[3] == 0 &&
+	         mac_addr[4] == 0 &&
+	         mac_addr[5] == 0) {
+		DEBUGOUT("MAC address is all zeros\n");
+		is_valid = FALSE;
+	}
+	return (is_valid);
+}
+
+/******************************************************************************
+ * Resets the 10GbE link.  Waits the settle time and returns the state of
+ * the link.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+boolean_t
+ixgb_link_reset(struct ixgb_hw *hw)
+{
+	boolean_t link_status = FALSE;
+	uint8_t wait_retries = MAX_RESET_ITERATIONS;
+	uint8_t lrst_retries = MAX_RESET_ITERATIONS;
+
+	do {
+		/* Reset the link */
+		IXGB_WRITE_REG(hw, CTRL0,
+			       IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
+
+		/* Wait for link-up and lane re-alignment */
+		do {
+			usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
+			link_status =
+				((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) &&
+				 (IXGB_READ_REG(hw, XPCSS) &
+				  IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
+		} while(!link_status && --wait_retries);
+
+	} while(!link_status && --lrst_retries);
+
+	return link_status;
+}
+
+/******************************************************************************
+ * Resets the 10GbE optics module.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+ixgb_optics_reset(struct ixgb_hw *hw)
+{
+	if(hw->phy_type == ixgb_phy_type_txn17401) {
+		uint16_t mdio_reg;
+
+		ixgb_write_phy_reg(hw,
+		                   MDIO_PMA_PMD_CR1,
+		                   IXGB_PHY_ADDRESS,
+		                   MDIO_PMA_PMD_DID,
+		                   MDIO_PMA_PMD_CR1_RESET);
+
+		mdio_reg = ixgb_read_phy_reg(hw,
+		                             MDIO_PMA_PMD_CR1,
+		                             IXGB_PHY_ADDRESS,
+		                             MDIO_PMA_PMD_DID);
+	}
+
+	return;
+}
diff --git a/sys/dev/pci/ixgb_hw.h b/sys/dev/pci/ixgb_hw.h
new file mode 100644
index 00000000000..3c6203d5e0f
--- /dev/null
+++ b/sys/dev/pci/ixgb_hw.h
@@ -0,0 +1,864 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2005, Intel Corporation
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived from
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/* $OpenBSD: ixgb_hw.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */ 
+
+#ifndef _IXGB_HW_H_
+#define _IXGB_HW_H_
+
+#include <dev/pci/if_ixgb_osdep.h>
+
+/* Enums */
+typedef enum {
+	ixgb_mac_unknown = 0,
+	ixgb_82597,
+	ixgb_num_macs
+} ixgb_mac_type;
+
+/* Types of physical layer modules */
+typedef enum {
+	ixgb_phy_type_unknown = 0,
+	ixgb_phy_type_g6005,	/* 850nm, MM fiber, XPAK transceiver */
+	ixgb_phy_type_g6104,	/* 1310nm, SM fiber, XPAK transceiver */
+	ixgb_phy_type_txn17201,	/* 850nm, MM fiber, XPAK transceiver */
+	ixgb_phy_type_txn17401	/* 1310nm, SM fiber, XENPAK transceiver */
+} ixgb_phy_type;
+
+/* XPAK transceiver vendors, for the SR adapters */
+typedef enum {
+	ixgb_xpak_vendor_intel,
+	ixgb_xpak_vendor_infineon
+} ixgb_xpak_vendor;
+
+/* Media Types */
+typedef enum {
+	ixgb_media_type_unknown = 0,
+	ixgb_media_type_fiber = 1,
+	ixgb_media_type_copper = 2,
+	ixgb_num_media_types
+} ixgb_media_type;
+
+/* Flow Control Settings */
+typedef enum {
+	ixgb_fc_none = 0,
+	ixgb_fc_rx_pause = 1,
+	ixgb_fc_tx_pause = 2,
+	ixgb_fc_full = 3,
+	ixgb_fc_default = 0xFF
+} ixgb_fc_type;
+
+/* PCI bus types */
+typedef enum {
+	ixgb_bus_type_unknown = 0,
+	ixgb_bus_type_pci,
+	ixgb_bus_type_pcix
+} ixgb_bus_type;
+
+/* PCI bus speeds */
+typedef enum {
+	ixgb_bus_speed_unknown = 0,
+	ixgb_bus_speed_33,
+	ixgb_bus_speed_66,
+	ixgb_bus_speed_100,
+	ixgb_bus_speed_133,
+	ixgb_bus_speed_reserved
+} ixgb_bus_speed;
+
+/* PCI bus widths */
+typedef enum {
+	ixgb_bus_width_unknown = 0,
+	ixgb_bus_width_32,
+	ixgb_bus_width_64
+} ixgb_bus_width;
+
+#define IXGB_ETH_LENGTH_OF_ADDRESS   6
+
+#define IXGB_EEPROM_SIZE    64	/* Size in words */
+
+#define SPEED_10000  10000
+#define FULL_DUPLEX  2
+
+#define MIN_NUMBER_OF_DESCRIPTORS       8
+#define MAX_NUMBER_OF_DESCRIPTORS  0xFFF8	/* 13 bits in RDLEN/TDLEN, 128B
+                                             * aligned */
+
+#define IXGB_DELAY_BEFORE_RESET        10	/* allow 10ms after idling
+                                             * rx/tx units */
+#define IXGB_DELAY_AFTER_RESET          1	/* allow 1ms after the reset */
+#define IXGB_DELAY_AFTER_EE_RESET      10	/* allow 10ms after the EEPROM
+                                             * reset */
+
+#define IXGB_DELAY_USECS_AFTER_LINK_RESET    13	/* allow 13 microseconds after
+                                                 * the reset */
+					   /* NOTE: this is MICROSECONDS */
+#define MAX_RESET_ITERATIONS            8	/* number of iterations to get
+                                             * things right */
+
+/* General Registers */
+#define IXGB_CTRL0   0x00000	/* Device Control Register 0 - RW */
+#define IXGB_CTRL1   0x00008	/* Device Control Register 1 - RW */
+#define IXGB_STATUS  0x00010	/* Device Status Register - RO */
+#define IXGB_EECD    0x00018	/* EEPROM/Flash Control/Data Register - RW */
+#define IXGB_MFRMS   0x00020	/* Maximum Frame Size - RW */
+
+/* Interrupt */
+#define IXGB_ICR     0x00080	/* Interrupt Cause Read - R/clr */
+#define IXGB_ICS     0x00088	/* Interrupt Cause Set - RW */
+#define IXGB_IMS     0x00090	/* Interrupt Mask Set/Read - RW */
+#define IXGB_IMC     0x00098	/* Interrupt Mask Clear - WO */
+
+/* Receive */
+#define IXGB_RCTL    0x00100	/* RX Control - RW */
+#define IXGB_FCRTL   0x00108	/* Flow Control Receive Threshold Low - RW */
+#define IXGB_FCRTH   0x00110	/* Flow Control Receive Threshold High - RW */
+#define IXGB_RDBAL   0x00118	/* RX Descriptor Base Low - RW */
+#define IXGB_RDBAH   0x0011C	/* RX Descriptor Base High - RW */
+#define IXGB_RDLEN   0x00120	/* RX Descriptor Length - RW */
+#define IXGB_RDH     0x00128	/* RX Descriptor Head - RW */
+#define IXGB_RDT     0x00130	/* RX Descriptor Tail - RW */
+#define IXGB_RDTR    0x00138	/* RX Delay Timer Ring - RW */
+#define IXGB_RXDCTL  0x00140	/* Receive Descriptor Control - RW */
+#define IXGB_RAIDC   0x00148	/* Receive Adaptive Interrupt Delay Ctrl RW */
+#define IXGB_RXCSUM  0x00158	/* Receive Checksum Control - RW */
+#define IXGB_RA      0x00180	/* Receive Address Array Base - RW */
+#define IXGB_RAL     0x00180	/* Receive Address Low [0:15] - RW */
+#define IXGB_RAH     0x00184	/* Receive Address High [0:15] - RW */
+#define IXGB_MTA     0x00200	/* Multicast Table Array [0:127] - RW */
+#define IXGB_VFTA    0x00400	/* VLAN Filter Table Array [0:127] - RW */
+#define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
+
+/* Transmit */
+#define IXGB_TCTL    0x00600	/* TX Control - RW */
+#define IXGB_TDBAL   0x00608	/* TX Descriptor Base Low - RW */
+#define IXGB_TDBAH   0x0060C	/* TX Descriptor Base High - RW */
+#define IXGB_TDLEN   0x00610	/* TX Descriptor Length - RW */
+#define IXGB_TDH     0x00618	/* TX Descriptor Head - RW */
+#define IXGB_TDT     0x00620	/* TX Descriptor Tail - RW */
+#define IXGB_TIDV    0x00628	/* TX Interrupt Delay Value - RW */
+#define IXGB_TXDCTL  0x00630	/* Transmit Descriptor Control - RW */
+#define IXGB_TSPMT   0x00638	/* TCP Segmentation PAD & Min Threshold - RW */
+#define IXGB_PAP     0x00640	/* Pause and Pace - RW */
+#define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
+
+/* Physical */
+#define IXGB_PCSC1   0x00700	/* PCS Control 1 - RW */
+#define IXGB_PCSC2   0x00708	/* PCS Control 2 - RW */
+#define IXGB_PCSS1   0x00710	/* PCS Status 1 - RO */
+#define IXGB_PCSS2   0x00718	/* PCS Status 2 - RO */
+#define IXGB_XPCSS   0x00720	/* 10GBASE-X PCS Status (or XGXS Lane Status) - 
+				 * RO */
+#define IXGB_UCCR    0x00728	/* Unilink Circuit Control Register */
+#define IXGB_XPCSTC  0x00730	/* 10GBASE-X PCS Test Control */
+#define IXGB_MACA    0x00738	/* MDI Autoscan Command and Address - RW */
+#define IXGB_APAE    0x00740	/* Autoscan PHY Address Enable - RW */
+#define IXGB_ARD     0x00748	/* Autoscan Read Data - RO */
+#define IXGB_AIS     0x00750	/* Autoscan Interrupt Status - RO */
+#define IXGB_MSCA    0x00758	/* MDI Single Command and Address - RW */
+#define IXGB_MSRWD   0x00760	/* MDI Single Read and Write Data - RW, RO */
+
+/* Wake-up */
+#define IXGB_WUFC    0x00808	/* Wake Up Filter Control - RW */
+#define IXGB_WUS     0x00810	/* Wake Up Status - RO */
+#define IXGB_FFLT    0x01000	/* Flexible Filter Length Table - RW */
+#define IXGB_FFMT    0x01020	/* Flexible Filter Mask Table - RW */
+#define IXGB_FTVT    0x01420	/* Flexible Filter Value Table - RW */
+
+/* Statistics */
+#define IXGB_TPRL    0x02000	/* Total Packets Received (Low) */
+#define IXGB_TPRH    0x02004	/* Total Packets Received (High) */
+#define IXGB_GPRCL   0x02008	/* Good Packets Received Count (Low) */
+#define IXGB_GPRCH   0x0200C	/* Good Packets Received Count (High) */
+#define IXGB_BPRCL   0x02010	/* Broadcast Packets Received Count (Low) */
+#define IXGB_BPRCH   0x02014	/* Broadcast Packets Received Count (High) */
+#define IXGB_MPRCL   0x02018	/* Multicast Packets Received Count (Low) */
+#define IXGB_MPRCH   0x0201C	/* Multicast Packets Received Count (High) */
+#define IXGB_UPRCL   0x02020	/* Unicast Packets Received Count (Low) */
+#define IXGB_UPRCH   0x02024	/* Unicast Packets Received Count (High) */
+#define IXGB_VPRCL   0x02028	/* VLAN Packets Received Count (Low) */
+#define IXGB_VPRCH   0x0202C	/* VLAN Packets Received Count (High) */
+#define IXGB_JPRCL   0x02030	/* Jumbo Packets Received Count (Low) */
+#define IXGB_JPRCH   0x02034	/* Jumbo Packets Received Count (High) */
+#define IXGB_GORCL   0x02038	/* Good Octets Received Count (Low) */
+#define IXGB_GORCH   0x0203C	/* Good Octets Received Count (High) */
+#define IXGB_TORL    0x02040	/* Total Octets Received (Low) */
+#define IXGB_TORH    0x02044	/* Total Octets Received (High) */
+#define IXGB_RNBC    0x02048	/* Receive No Buffers Count */
+#define IXGB_RUC     0x02050	/* Receive Undersize Count */
+#define IXGB_ROC     0x02058	/* Receive Oversize Count */
+#define IXGB_RLEC    0x02060	/* Receive Length Error Count */
+#define IXGB_CRCERRS 0x02068	/* CRC Error Count */
+#define IXGB_ICBC    0x02070	/* Illegal control byte in mid-packet Count */
+#define IXGB_ECBC    0x02078	/* Error Control byte in mid-packet Count */
+#define IXGB_MPC     0x02080	/* Missed Packets Count */
+#define IXGB_TPTL    0x02100	/* Total Packets Transmitted (Low) */
+#define IXGB_TPTH    0x02104	/* Total Packets Transmitted (High) */
+#define IXGB_GPTCL   0x02108	/* Good Packets Transmitted Count (Low) */
+#define IXGB_GPTCH   0x0210C	/* Good Packets Transmitted Count (High) */
+#define IXGB_BPTCL   0x02110	/* Broadcast Packets Transmitted Count (Low) */
+#define IXGB_BPTCH   0x02114	/* Broadcast Packets Transmitted Count (High) */
+#define IXGB_MPTCL   0x02118	/* Multicast Packets Transmitted Count (Low) */
+#define IXGB_MPTCH   0x0211C	/* Multicast Packets Transmitted Count (High) */
+#define IXGB_UPTCL   0x02120	/* Unicast Packets Transmitted Count (Low) */
+#define IXGB_UPTCH   0x02124	/* Unicast Packets Transmitted Count (High) */
+#define IXGB_VPTCL   0x02128	/* VLAN Packets Transmitted Count (Low) */
+#define IXGB_VPTCH   0x0212C	/* VLAN Packets Transmitted Count (High) */
+#define IXGB_JPTCL   0x02130	/* Jumbo Packets Transmitted Count (Low) */
+#define IXGB_JPTCH   0x02134	/* Jumbo Packets Transmitted Count (High) */
+#define IXGB_GOTCL   0x02138	/* Good Octets Transmitted Count (Low) */
+#define IXGB_GOTCH   0x0213C	/* Good Octets Transmitted Count (High) */
+#define IXGB_TOTL    0x02140	/* Total Octets Transmitted Count (Low) */
+#define IXGB_TOTH    0x02144	/* Total Octets Transmitted Count (High) */
+#define IXGB_DC      0x02148	/* Defer Count */
+#define IXGB_PLT64C  0x02150	/* Packet Transmitted was < 64 bytes Count */
+#define IXGB_TSCTC   0x02170	/* TCP Segmentation Context Transmitted Count */
+#define IXGB_TSCTFC  0x02178	/* TCP Segmentation Context Tx Fail Count */
+#define IXGB_IBIC    0x02180	/* Illegal byte during Idle stream count */
+#define IXGB_RFC     0x02188	/* Remote Fault Count */
+#define IXGB_LFC     0x02190	/* Local Fault Count */
+#define IXGB_PFRC    0x02198	/* Pause Frame Receive Count */
+#define IXGB_PFTC    0x021A0	/* Pause Frame Transmit Count */
+#define IXGB_MCFRC   0x021A8	/* MAC Control Frames (non-Pause) Received
+				 * Count */
+#define IXGB_MCFTC   0x021B0	/* MAC Control Frames (non-Pause) Transmitted
+				 * Count */
+#define IXGB_XONRXC  0x021B8	/* XON Received Count */
+#define IXGB_XONTXC  0x021C0	/* XON Transmitted Count */
+#define IXGB_XOFFRXC 0x021C8	/* XOFF Received Count */
+#define IXGB_XOFFTXC 0x021D0	/* XOFF Transmitted Count */
+#define IXGB_RJC     0x021D8	/* Receive Jabber Count */
+
+
+/* CTRL0 Bit Masks */
+#define IXGB_CTRL0_LRST     0x00000008
+#define IXGB_CTRL0_JFE      0x00000010
+#define IXGB_CTRL0_XLE      0x00000020
+#define IXGB_CTRL0_MDCS     0x00000040
+#define IXGB_CTRL0_CMDC     0x00000080
+#define IXGB_CTRL0_SDP0     0x00040000
+#define IXGB_CTRL0_SDP1     0x00080000
+#define IXGB_CTRL0_SDP2     0x00100000
+#define IXGB_CTRL0_SDP3     0x00200000
+#define IXGB_CTRL0_SDP0_DIR 0x00400000
+#define IXGB_CTRL0_SDP1_DIR 0x00800000
+#define IXGB_CTRL0_SDP2_DIR 0x01000000
+#define IXGB_CTRL0_SDP3_DIR 0x02000000
+#define IXGB_CTRL0_RST      0x04000000
+#define IXGB_CTRL0_RPE      0x08000000
+#define IXGB_CTRL0_TPE      0x10000000
+#define IXGB_CTRL0_VME      0x40000000
+
+/* CTRL1 Bit Masks */
+#define IXGB_CTRL1_GPI0_EN     0x00000001
+#define IXGB_CTRL1_GPI1_EN     0x00000002
+#define IXGB_CTRL1_GPI2_EN     0x00000004
+#define IXGB_CTRL1_GPI3_EN     0x00000008
+#define IXGB_CTRL1_SDP4        0x00000010
+#define IXGB_CTRL1_SDP5        0x00000020
+#define IXGB_CTRL1_SDP6        0x00000040
+#define IXGB_CTRL1_SDP7        0x00000080
+#define IXGB_CTRL1_SDP4_DIR    0x00000100
+#define IXGB_CTRL1_SDP5_DIR    0x00000200
+#define IXGB_CTRL1_SDP6_DIR    0x00000400
+#define IXGB_CTRL1_SDP7_DIR    0x00000800
+#define IXGB_CTRL1_EE_RST      0x00002000
+#define IXGB_CTRL1_RO_DIS      0x00020000
+#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
+#define IXGB_CTRL1_PCIXHM_1_2  0x00000000
+#define IXGB_CTRL1_PCIXHM_5_8  0x00400000
+#define IXGB_CTRL1_PCIXHM_3_4  0x00800000
+#define IXGB_CTRL1_PCIXHM_7_8  0x00C00000
+
+/* STATUS Bit Masks */
+#define IXGB_STATUS_LU            0x00000002
+#define IXGB_STATUS_AIP           0x00000004
+#define IXGB_STATUS_TXOFF         0x00000010
+#define IXGB_STATUS_XAUIME        0x00000020
+#define IXGB_STATUS_RES           0x00000040
+#define IXGB_STATUS_RIS           0x00000080
+#define IXGB_STATUS_RIE           0x00000100
+#define IXGB_STATUS_RLF           0x00000200
+#define IXGB_STATUS_RRF           0x00000400
+#define IXGB_STATUS_PCI_SPD       0x00000800
+#define IXGB_STATUS_BUS64         0x00001000
+#define IXGB_STATUS_PCIX_MODE     0x00002000
+#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
+#define IXGB_STATUS_PCIX_SPD_66   0x00000000
+#define IXGB_STATUS_PCIX_SPD_100  0x00004000
+#define IXGB_STATUS_PCIX_SPD_133  0x00008000
+#define IXGB_STATUS_REV_ID_MASK   0x000F0000
+#define IXGB_STATUS_REV_ID_SHIFT  16
+
+/* EECD Bit Masks */
+#define IXGB_EECD_SK       0x00000001
+#define IXGB_EECD_CS       0x00000002
+#define IXGB_EECD_DI       0x00000004
+#define IXGB_EECD_DO       0x00000008
+#define IXGB_EECD_FWE_MASK 0x00000030
+#define IXGB_EECD_FWE_DIS  0x00000010
+#define IXGB_EECD_FWE_EN   0x00000020
+
+/* MFRMS */
+#define IXGB_MFRMS_SHIFT 16
+
+/* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
+#define IXGB_INT_TXDW     0x00000001
+#define IXGB_INT_TXQE     0x00000002
+#define IXGB_INT_LSC      0x00000004
+#define IXGB_INT_RXSEQ    0x00000008
+#define IXGB_INT_RXDMT0   0x00000010
+#define IXGB_INT_RXO      0x00000040
+#define IXGB_INT_RXT0     0x00000080
+#define IXGB_INT_AUTOSCAN 0x00000200
+#define IXGB_INT_GPI0     0x00000800
+#define IXGB_INT_GPI1     0x00001000
+#define IXGB_INT_GPI2     0x00002000
+#define IXGB_INT_GPI3     0x00004000
+
+/* RCTL Bit Masks */
+#define IXGB_RCTL_RXEN        0x00000002
+#define IXGB_RCTL_SBP         0x00000004
+#define IXGB_RCTL_UPE         0x00000008
+#define IXGB_RCTL_MPE         0x00000010
+#define IXGB_RCTL_RDMTS_MASK  0x00000300
+#define IXGB_RCTL_RDMTS_1_2   0x00000000
+#define IXGB_RCTL_RDMTS_1_4   0x00000100
+#define IXGB_RCTL_RDMTS_1_8   0x00000200
+#define IXGB_RCTL_MO_MASK     0x00003000
+#define IXGB_RCTL_MO_47_36    0x00000000
+#define IXGB_RCTL_MO_46_35    0x00001000
+#define IXGB_RCTL_MO_45_34    0x00002000
+#define IXGB_RCTL_MO_43_32    0x00003000
+#define IXGB_RCTL_MO_SHIFT    12
+#define IXGB_RCTL_BAM         0x00008000
+#define IXGB_RCTL_BSIZE_MASK  0x00030000
+#define IXGB_RCTL_BSIZE_2048  0x00000000
+#define IXGB_RCTL_BSIZE_4096  0x00010000
+#define IXGB_RCTL_BSIZE_8192  0x00020000
+#define IXGB_RCTL_BSIZE_16384 0x00030000
+#define IXGB_RCTL_VFE         0x00040000
+#define IXGB_RCTL_CFIEN       0x00080000
+#define IXGB_RCTL_CFI         0x00100000
+#define IXGB_RCTL_RPDA_MASK   0x00600000
+#define IXGB_RCTL_RPDA_MC_MAC 0x00000000
+#define IXGB_RCTL_MC_ONLY     0x00400000
+#define IXGB_RCTL_CFF         0x00800000
+#define IXGB_RCTL_SECRC       0x04000000
+#define IXGB_RDT_FPDB         0x80000000
+
+#define IXGB_RCTL_IDLE_RX_UNIT 0
+
+/* FCRTL Bit Masks */
+#define IXGB_FCRTL_XONE       0x80000000
+
+/* RXDCTL Bit Masks */
+#define IXGB_RXDCTL_PTHRESH_MASK  0x000001FF
+#define IXGB_RXDCTL_PTHRESH_SHIFT 0
+#define IXGB_RXDCTL_HTHRESH_MASK  0x0003FE00
+#define IXGB_RXDCTL_HTHRESH_SHIFT 9
+#define IXGB_RXDCTL_WTHRESH_MASK  0x07FC0000
+#define IXGB_RXDCTL_WTHRESH_SHIFT 18
+
+/* RAIDC Bit Masks */
+#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
+#define IXGB_RAIDC_DELAY_MASK    0x000FF800
+#define IXGB_RAIDC_DELAY_SHIFT   11
+#define IXGB_RAIDC_POLL_MASK     0x1FF00000
+#define IXGB_RAIDC_POLL_SHIFT    20
+#define IXGB_RAIDC_RXT_GATE      0x40000000
+#define IXGB_RAIDC_EN            0x80000000
+
+#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND      1220
+#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND      244
+#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND     122
+#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND     61
+
+/* RXCSUM Bit Masks */
+#define IXGB_RXCSUM_IPOFL 0x00000100
+#define IXGB_RXCSUM_TUOFL 0x00000200
+
+/* RAH Bit Masks */
+#define IXGB_RAH_ASEL_MASK 0x00030000
+#define IXGB_RAH_ASEL_DEST 0x00000000
+#define IXGB_RAH_ASEL_SRC  0x00010000
+#define IXGB_RAH_AV        0x80000000
+
+/* TCTL Bit Masks */
+#define IXGB_TCTL_TCE  0x00000001
+#define IXGB_TCTL_TXEN 0x00000002
+#define IXGB_TCTL_TPDE 0x00000004
+
+#define IXGB_TCTL_IDLE_TX_UNIT  0
+
+/* TXDCTL Bit Masks */
+#define IXGB_TXDCTL_PTHRESH_MASK  0x0000007F
+#define IXGB_TXDCTL_HTHRESH_MASK  0x00007F00
+#define IXGB_TXDCTL_HTHRESH_SHIFT 8
+#define IXGB_TXDCTL_WTHRESH_MASK  0x007F0000
+#define IXGB_TXDCTL_WTHRESH_SHIFT 16
+
+/* TSPMT Bit Masks */
+#define IXGB_TSPMT_TSMT_MASK   0x0000FFFF
+#define IXGB_TSPMT_TSPBP_MASK  0xFFFF0000
+#define IXGB_TSPMT_TSPBP_SHIFT 16
+
+/* PAP Bit Masks */
+#define IXGB_PAP_TXPC_MASK 0x0000FFFF
+#define IXGB_PAP_TXPV_MASK 0x000F0000
+#define IXGB_PAP_TXPV_10G  0x00000000
+#define IXGB_PAP_TXPV_1G   0x00010000
+#define IXGB_PAP_TXPV_2G   0x00020000
+#define IXGB_PAP_TXPV_3G   0x00030000
+#define IXGB_PAP_TXPV_4G   0x00040000
+#define IXGB_PAP_TXPV_5G   0x00050000
+#define IXGB_PAP_TXPV_6G   0x00060000
+#define IXGB_PAP_TXPV_7G   0x00070000
+#define IXGB_PAP_TXPV_8G   0x00080000
+#define IXGB_PAP_TXPV_9G   0x00090000
+#define IXGB_PAP_TXPV_WAN  0x000F0000
+
+/* PCSC1 Bit Masks */
+#define IXGB_PCSC1_LOOPBACK 0x00004000
+
+/* PCSC2 Bit Masks */
+#define IXGB_PCSC2_PCS_TYPE_MASK  0x00000003
+#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
+
+/* PCSS1 Bit Masks */
+#define IXGB_PCSS1_LOCAL_FAULT    0x00000080
+#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
+
+/* PCSS2 Bit Masks */
+#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
+#define IXGB_PCSS2_DEV_PRES      0x00004000
+#define IXGB_PCSS2_TX_LF         0x00000800
+#define IXGB_PCSS2_RX_LF         0x00000400
+#define IXGB_PCSS2_10GBW         0x00000004
+#define IXGB_PCSS2_10GBX         0x00000002
+#define IXGB_PCSS2_10GBR         0x00000001
+
+/* XPCSS Bit Masks */
+#define IXGB_XPCSS_ALIGN_STATUS 0x00001000
+#define IXGB_XPCSS_PATTERN_TEST 0x00000800
+#define IXGB_XPCSS_LANE_3_SYNC  0x00000008
+#define IXGB_XPCSS_LANE_2_SYNC  0x00000004
+#define IXGB_XPCSS_LANE_1_SYNC  0x00000002
+#define IXGB_XPCSS_LANE_0_SYNC  0x00000001
+
+/* XPCSTC Bit Masks */
+#define IXGB_XPCSTC_BERT_TRIG       0x00200000
+#define IXGB_XPCSTC_BERT_SST        0x00100000
+#define IXGB_XPCSTC_BERT_PSZ_MASK   0x000C0000
+#define IXGB_XPCSTC_BERT_PSZ_SHIFT  17
+#define IXGB_XPCSTC_BERT_PSZ_INF    0x00000003
+#define IXGB_XPCSTC_BERT_PSZ_68     0x00000001
+#define IXGB_XPCSTC_BERT_PSZ_1028   0x00000000
+
+/* MSCA bit Masks */
+
+/* New Protocol Address */
+#define IXGB_MSCA_NP_ADDR_MASK      0x0000FFFF
+#define IXGB_MSCA_NP_ADDR_SHIFT     0
+
+/* Either Device Type or Register Address,depending on ST_CODE */
+#define IXGB_MSCA_DEV_TYPE_MASK     0x001F0000
+#define IXGB_MSCA_DEV_TYPE_SHIFT    16
+#define IXGB_MSCA_PHY_ADDR_MASK     0x03E00000
+#define IXGB_MSCA_PHY_ADDR_SHIFT    21
+#define IXGB_MSCA_OP_CODE_MASK      0x0C000000
+
+/* OP_CODE == 00, Address cycle, New Protocol           */
+
+/* OP_CODE == 01, Write operation                       */
+
+/* OP_CODE == 10, Read operation                        */
+
+/* OP_CODE == 11, Read, auto increment, New Protocol    */
+#define IXGB_MSCA_ADDR_CYCLE        0x00000000
+#define IXGB_MSCA_WRITE             0x04000000
+#define IXGB_MSCA_READ              0x08000000
+#define IXGB_MSCA_READ_AUTOINC      0x0C000000
+#define IXGB_MSCA_OP_CODE_SHIFT     26
+#define IXGB_MSCA_ST_CODE_MASK      0x30000000
+
+/* ST_CODE == 00, New Protocol  */
+
+/* ST_CODE == 01, Old Protocol  */
+#define IXGB_MSCA_NEW_PROTOCOL      0x00000000
+#define IXGB_MSCA_OLD_PROTOCOL      0x10000000
+#define IXGB_MSCA_ST_CODE_SHIFT     28
+
+/* Initiate command, self-clearing when command completes */
+#define IXGB_MSCA_MDI_COMMAND       0x40000000
+
+/*MDI In Progress Enable. */
+#define IXGB_MSCA_MDI_IN_PROG_EN    0x80000000
+
+/* MSRWD bit masks */
+#define IXGB_MSRWD_WRITE_DATA_MASK  0x0000FFFF
+#define IXGB_MSRWD_WRITE_DATA_SHIFT 0
+#define IXGB_MSRWD_READ_DATA_MASK   0xFFFF0000
+#define IXGB_MSRWD_READ_DATA_SHIFT  16
+
+/* Definitions for the optics devices on the MDIO bus. */
+#define IXGB_PHY_ADDRESS        0x0	/* Single PHY, multiple "Devices" */
+
+/* Standard five-bit Device IDs.  See IEEE 802.3ae, clause 45 */
+#define MDIO_PMA_PMD_DID        0x01
+#define MDIO_WIS_DID            0x02
+#define MDIO_PCS_DID            0x03
+#define MDIO_XGXS_DID           0x04
+
+/* Standard PMA/PMD registers and bit definitions. */
+
+/* Note: This is a very limited set of definitions,      */
+
+/* only implemented features are defined.                */
+#define MDIO_PMA_PMD_CR1        0x0000
+#define MDIO_PMA_PMD_CR1_RESET  0x8000
+
+#define MDIO_PMA_PMD_XPAK_VENDOR_NAME       0x803A	/* XPAK/XENPAK devices
+							 * only */
+
+/* Vendor-specific MDIO registers */
+#define G6XXX_PMA_PMD_VS1                   0xC001	/* Vendor-specific
+							 * register */
+#define G6XXX_XGXS_XAUI_VS2                 0x18	/* Vendor-specific
+							 * register */
+
+#define G6XXX_PMA_PMD_VS1_PLL_RESET         0x80
+#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET  0x00
+#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK      0x0F	/* XAUI lanes
+							 * synchronized */
+
+/* Layout of a single receive descriptor.  The controller assumes that this
+ * structure is packed into 16 bytes, which is a safe assumption with most
+ * compilers.  However, some compilers may insert padding between the fields,
+ * in which case the structure must be packed in some compiler-specific
+ * manner. */
+struct ixgb_rx_desc {
+	uint64_t buff_addr;
+	uint16_t length;
+	uint16_t reserved;
+	uint8_t status;
+	uint8_t errors;
+	uint16_t special;
+};
+
+#define IXGB_RX_DESC_STATUS_DD    0x01
+#define IXGB_RX_DESC_STATUS_EOP   0x02
+#define IXGB_RX_DESC_STATUS_IXSM  0x04
+#define IXGB_RX_DESC_STATUS_VP    0x08
+#define IXGB_RX_DESC_STATUS_TCPCS 0x20
+#define IXGB_RX_DESC_STATUS_IPCS  0x40
+#define IXGB_RX_DESC_STATUS_PIF   0x80
+
+#define IXGB_RX_DESC_ERRORS_CE   0x01
+#define IXGB_RX_DESC_ERRORS_SE   0x02
+#define IXGB_RX_DESC_ERRORS_P    0x08
+#define IXGB_RX_DESC_ERRORS_TCPE 0x20
+#define IXGB_RX_DESC_ERRORS_IPE  0x40
+#define IXGB_RX_DESC_ERRORS_RXE  0x80
+
+#define IXGB_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF	/* VLAN ID is in lower 12 bits */
+#define IXGB_RX_DESC_SPECIAL_PRI_MASK   0xE000	/* Priority is in upper 3 bits */
+#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT  0x000D	/* Priority is in upper 3 of 16 
+						 */
+
+/* Layout of a single transmit descriptor.  The controller assumes that this
+ * structure is packed into 16 bytes, which is a safe assumption with most
+ * compilers.  However, some compilers may insert padding between the fields,
+ * in which case the structure must be packed in some compiler-specific
+ * manner. */
+struct ixgb_tx_desc {
+	uint64_t buff_addr;
+	uint32_t cmd_type_len;
+	uint8_t status;
+	uint8_t popts;
+	uint16_t vlan;
+};
+
+#define IXGB_TX_DESC_LENGTH_MASK    0x000FFFFF
+#define IXGB_TX_DESC_TYPE_MASK      0x00F00000
+#define IXGB_TX_DESC_TYPE_SHIFT     20
+#define IXGB_TX_DESC_CMD_MASK       0xFF000000
+#define IXGB_TX_DESC_CMD_SHIFT      24
+#define IXGB_TX_DESC_CMD_EOP        0x01000000
+#define IXGB_TX_DESC_CMD_TSE        0x04000000
+#define IXGB_TX_DESC_CMD_RS         0x08000000
+#define IXGB_TX_DESC_CMD_VLE        0x40000000
+#define IXGB_TX_DESC_CMD_IDE        0x80000000
+
+#define IXGB_TX_DESC_TYPE           0x00100000
+
+#define IXGB_TX_DESC_STATUS_DD  0x01
+
+#define IXGB_TX_DESC_POPTS_IXSM 0x01
+#define IXGB_TX_DESC_POPTS_TXSM 0x02
+/* Priority is in upper 3 of 16 */
+#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT  IXGB_RX_DESC_SPECIAL_PRI_SHIFT
+
+struct ixgb_context_desc {
+	uint8_t ipcss;
+	uint8_t ipcso;
+	uint16_t ipcse;
+	uint8_t tucss;
+	uint8_t tucso;
+	uint16_t tucse;
+	uint32_t cmd_type_len;
+	uint8_t status;
+	uint8_t hdr_len;
+	uint16_t mss;
+};
+
+#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
+#define IXGB_CONTEXT_DESC_CMD_IP  0x02000000
+#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
+#define IXGB_CONTEXT_DESC_CMD_RS  0x08000000
+#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
+
+#define IXGB_CONTEXT_DESC_TYPE 0x00000000
+
+#define IXGB_CONTEXT_DESC_STATUS_DD 0x01
+
+/* Filters */
+#define IXGB_RAR_ENTRIES 3	/* Number of entries in Rx Address array */
+#define IXGB_MC_TBL_SIZE          128	/* Multicast Filter Table (4096 bits) */
+#define IXGB_VLAN_FILTER_TBL_SIZE 128	/* VLAN Filter Table (4096 bits) */
+
+#define IXGB_MEMORY_REGISTER_BASE_ADDRESS   0
+#define ENET_HEADER_SIZE            14
+#define ENET_FCS_LENGTH             4
+#define IXGB_MAX_NUM_MULTICAST_ADDRESSES    128
+#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS    60
+#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS    1514
+#define IXGB_MAX_JUMBO_FRAME_SIZE       0x3F00
+
+/* Phy Addresses */
+#define IXGB_OPTICAL_PHY_ADDR 0x0	/* Optical Module phy address */
+#define IXGB_XAUII_PHY_ADDR   0x1	/* Xauii transceiver phy address */
+#define IXGB_DIAG_PHY_ADDR    0x1F	/* Diagnostic Device phy address */
+
+/* This structure takes a 64k flash and maps it for identification commands */
+struct ixgb_flash_buffer {
+	uint8_t manufacturer_id;
+	uint8_t device_id;
+	uint8_t filler1[0x2AA8];
+	uint8_t cmd2;
+	uint8_t filler2[0x2AAA];
+	uint8_t cmd1;
+	uint8_t filler3[0xAAAA];
+};
+
+/*
+ * This is a little-endian specific check.
+ */
+#define IS_MULTICAST(Address) \
+    (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
+
+/*
+ * Check whether an address is broadcast.
+ */
+#define IS_BROADCAST(Address)               \
+    ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
+
+/* Flow control parameters */
+struct ixgb_fc {
+	uint32_t high_water;	/* Flow Control High-water */
+	uint32_t low_water;	/* Flow Control Low-water */
+	uint16_t pause_time;	/* Flow Control Pause timer */
+	boolean_t send_xon;	/* Flow control send XON */
+	ixgb_fc_type type;	/* Type of flow control */
+};
+
+/* The historical defaults for the flow control values are given below. */
+#define FC_DEFAULT_HI_THRESH        (0x8000)	/* 32KB */
+#define FC_DEFAULT_LO_THRESH        (0x4000)	/* 16KB */
+#define FC_DEFAULT_TX_TIMER         (0x100)	/* ~130 us */
+
+/* Phy definitions */
+#define IXGB_MAX_PHY_REG_ADDRESS    0xFFFF
+#define IXGB_MAX_PHY_ADDRESS        31
+#define IXGB_MAX_PHY_DEV_TYPE       31
+
+/* Bus parameters */
+struct ixgb_bus {
+	ixgb_bus_speed speed;
+	ixgb_bus_width width;
+	ixgb_bus_type type;
+};
+
+struct ixgb_hw {
+	uint8_t *hw_addr;	/* Base Address of the hardware */
+	void *back;	/* Pointer to OS-dependent struct */
+	struct ixgb_fc fc;	/* Flow control parameters */
+	struct ixgb_bus bus;	/* Bus parameters */
+	uint32_t phy_id;	/* Phy Identifier */
+	uint32_t phy_addr;	/* XGMII address of Phy */
+	ixgb_mac_type mac_type;	/* Identifier for MAC controller */
+	ixgb_phy_type phy_type;	/* Transceiver/phy identifier */
+	uint32_t max_frame_size;	/* Maximum frame size supported */
+	uint32_t mc_filter_type;	/* Multicast filter hash type */
+	uint32_t num_mc_addrs;	/* Number of current Multicast addrs */
+	/* Individual address currently programmed in MAC */
+	uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];	
+	uint32_t num_tx_desc;	/* Number of Transmit descriptors */
+	uint32_t num_rx_desc;	/* Number of Receive descriptors */
+	uint32_t rx_buffer_size;	/* Size of Receive buffer */
+	boolean_t link_up;	/* TRUE if link is valid */
+	boolean_t adapter_stopped;	/* State of adapter */
+	uint16_t device_id;	/* device id from PCI configuration space */
+	uint16_t vendor_id;	/* vendor id from PCI configuration space */
+	uint8_t revision_id;	/* revision id from PCI configuration space */
+	uint16_t subsystem_vendor_id;	/* subsystem vendor id from PCI
+					 * configuration space */
+	uint16_t subsystem_id;	/* subsystem id from PCI configuration space */
+	uint32_t bar0;	/* Base Address registers */
+	uint32_t bar1;
+	uint32_t bar2;
+	uint32_t bar3;
+	uint16_t pci_cmd_word;	/* PCI command register id from PCI
+				 * configuration space */
+	uint16_t eeprom[IXGB_EEPROM_SIZE];	/* EEPROM contents read at init 
+						 * time */
+	unsigned long io_base;	/* Our I/O mapped location */
+	uint32_t lastLFC;
+	uint32_t lastRFC;
+};
+
+/* Statistics reported by the hardware */
+struct ixgb_hw_stats {
+	uint64_t tprl;
+	uint64_t tprh;
+	uint64_t gprcl;
+	uint64_t gprch;
+	uint64_t bprcl;
+	uint64_t bprch;
+	uint64_t mprcl;
+	uint64_t mprch;
+	uint64_t uprcl;
+	uint64_t uprch;
+	uint64_t vprcl;
+	uint64_t vprch;
+	uint64_t jprcl;
+	uint64_t jprch;
+	uint64_t gorcl;
+	uint64_t gorch;
+	uint64_t torl;
+	uint64_t torh;
+	uint64_t rnbc;
+	uint64_t ruc;
+	uint64_t roc;
+	uint64_t rlec;
+	uint64_t crcerrs;
+	uint64_t icbc;
+	uint64_t ecbc;
+	uint64_t mpc;
+	uint64_t tptl;
+	uint64_t tpth;
+	uint64_t gptcl;
+	uint64_t gptch;
+	uint64_t bptcl;
+	uint64_t bptch;
+	uint64_t mptcl;
+	uint64_t mptch;
+	uint64_t uptcl;
+	uint64_t uptch;
+	uint64_t vptcl;
+	uint64_t vptch;
+	uint64_t jptcl;
+	uint64_t jptch;
+	uint64_t gotcl;
+	uint64_t gotch;
+	uint64_t totl;
+	uint64_t toth;
+	uint64_t dc;
+	uint64_t plt64c;
+	uint64_t tsctc;
+	uint64_t tsctfc;
+	uint64_t ibic;
+	uint64_t rfc;
+	uint64_t lfc;
+	uint64_t pfrc;
+	uint64_t pftc;
+	uint64_t mcfrc;
+	uint64_t mcftc;
+	uint64_t xonrxc;
+	uint64_t xontxc;
+	uint64_t xoffrxc;
+	uint64_t xofftxc;
+	uint64_t rjc;
+};
+
+/* Function Prototypes */
+extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
+extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
+extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
+extern void ixgb_check_for_link(struct ixgb_hw *hw);
+extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
+extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index);
+extern void ixgb_init_rx_addrs(struct ixgb_hw *hw);
+extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
+extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
+extern boolean_t mac_addr_valid(uint8_t *mac_addr);
+
+extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,
+				  uint32_t phy_addr, uint32_t device_type);
+
+extern void ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,
+			       uint32_t phy_addr, uint32_t device_type,
+			       uint16_t data);
+
+
+/* Filters (multicast, vlan, receive) */
+extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
+				     uint32_t mc_addr_count, uint32_t pad);
+
+/* Vfta functions */
+extern void ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset,
+			    uint32_t value);
+
+extern void ixgb_clear_vfta(struct ixgb_hw *hw);
+
+/* Access functions to eeprom data */
+void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
+uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
+uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
+boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
+uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);
+
+/* Everything else */
+void ixgb_led_on(struct ixgb_hw *hw);
+void ixgb_led_off(struct ixgb_hw *hw);
+void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t *value);
+
+#endif /* _IXGB_HW_H_ */
diff --git a/sys/dev/pci/ixgb_ids.h b/sys/dev/pci/ixgb_ids.h
new file mode 100644
index 00000000000..bb562efc67c
--- /dev/null
+++ b/sys/dev/pci/ixgb_ids.h
@@ -0,0 +1,56 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2005, Intel Corporation
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived from
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/* $OpenBSD: ixgb_ids.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */
+
+#ifndef _IXGB_IDS_H_
+#define _IXGB_IDS_H_
+
+/**********************************************************************
+** The Device and Vendor IDs for 10 Gigabit MACs
+**********************************************************************/
+
+#define INTEL_VENDOR_ID         0x8086
+#define INTEL_SUBVENDOR_ID      0x8086
+
+#define IXGB_DEVICE_ID_82597EX      0x1048
+#define IXGB_DEVICE_ID_82597EX_SR   0x1A48
+#define IXGB_DEVICE_ID_82597EX_LR   0x1B48
+#define IXGB_SUBDEVICE_ID_A11F  0xA11F
+#define IXGB_SUBDEVICE_ID_A01F  0xA01F
+
+#define IXGB_DEVICE_ID_82597EX_CX4   0x109E
+#define IXGB_SUBDEVICE_ID_A00C  0xA00C
+
+#endif /* #ifndef _IXGB_IDS_H_ */
+/* End of File */