diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2019-08-18 15:51:19 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2019-08-18 15:51:19 +0000 |
| commit | 5672dbf75d2b1da85e2167ee9d04edfe49ebedcd (patch) | |
| tree | b4bd73fdccc13aa4354f0f7d9c9c8069e559030c /sys | |
| parent | 1b6babe38aa2f3ed5c9dc0fd33a2c991b58b5b3f (diff) | |
In polled mode, wait on STOP detected bit to be set in the interrupt status
register like we do for non-polled mode. This seems to increase the
reliability of i2c transfers on the controller integrated on the Ampare
eMAG processor.
ok jcs@, mlarkin@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/ic/dwiic.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/sys/dev/ic/dwiic.c b/sys/dev/ic/dwiic.c index 80b598f08ce..89de133ee1b 100644 --- a/sys/dev/ic/dwiic.c +++ b/sys/dev/ic/dwiic.c @@ -1,4 +1,4 @@ -/* $OpenBSD: dwiic.c,v 1.6 2019/08/06 06:56:29 kettenis Exp $ */ +/* $OpenBSD: dwiic.c,v 1.7 2019/08/18 15:51:18 kettenis Exp $ */ /* * Synopsys DesignWare I2C controller * @@ -407,14 +407,13 @@ dwiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, if (I2C_OP_STOP_P(op) && I2C_OP_WRITE_P(op)) { if (flags & I2C_F_POLL) { - /* wait for bus to be idle */ for (retries = 100; retries > 0; retries--) { - st = dwiic_read(sc, DW_IC_STATUS); - if (!(st & DW_IC_STATUS_ACTIVITY)) + st = dwiic_read(sc, DW_IC_RAW_INTR_STAT); + if (st & DW_IC_INTR_STOP_DET) break; DELAY(1000); } - if (st & DW_IC_STATUS_ACTIVITY) + if (!(st & DW_IC_INTR_STOP_DET)) printf("%s: timed out waiting for bus idle\n", sc->sc_dev.dv_xname); } else { |