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authorJonathan Gray <jsg@cvs.openbsd.org>2023-02-23 02:17:39 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2023-02-23 02:17:39 +0000
commit7c6c562880ac4685e9ced76a13f2877fe78b05ce (patch)
tree3d3f8ab99f11fa9cd440624bf5e056e3e22b4ce9 /sys
parent240ef875dab2c3f9cf462c9226f1b19c7080701d (diff)
drm/amd/display: Reset DMUB mailbox SW state after HW reset
From Nicholas Kazlauskas 488770cbddd8a873fb3bb8866e8a46211570c367 in linux-6.1.y/6.1.13 154711aa5759ef9b45903124fa813c4c29ee681c in mainline linux
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c b/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
index 4a122925c3a..92c18bfb98b 100644
--- a/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
+++ b/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
@@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
if (dmub->hw_funcs.reset)
dmub->hw_funcs.reset(dmub);
+ /* reset the cache of the last wptr as well now that hw is reset */
+ dmub->inbox1_last_wptr = 0;
+
cw0.offset.quad_part = inst_fb->gpu_addr;
cw0.region.base = DMUB_CW0_BASE;
cw0.region.top = cw0.region.base + inst_fb->size - 1;
@@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
if (dmub->hw_funcs.reset)
dmub->hw_funcs.reset(dmub);
+ /* mailboxes have been reset in hw, so reset the sw state as well */
+ dmub->inbox1_last_wptr = 0;
+ dmub->inbox1_rb.wrpt = 0;
+ dmub->inbox1_rb.rptr = 0;
+ dmub->outbox0_rb.wrpt = 0;
+ dmub->outbox0_rb.rptr = 0;
+ dmub->outbox1_rb.wrpt = 0;
+ dmub->outbox1_rb.rptr = 0;
+
dmub->hw_init = false;
return DMUB_STATUS_OK;