more special regs definitions; use names from pctr.h for those it uses

2 files changed, 207 insertions, 15 deletions

diff --git a/sys/arch/i386/include/pctr.h b/sys/arch/i386/include/pctr.h
index 15c1f3dfbb2..0bf1097a752 100644
--- a/sys/arch/i386/include/pctr.h
+++ b/sys/arch/i386/include/pctr.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pctr.h,v 1.9 1998/05/25 08:02:24 downsj Exp $	*/
+/*	$OpenBSD: pctr.h,v 1.10 2001/01/26 23:32:14 mickey Exp $	*/
 
 /*
  * Pentium performance counter driver for OpenBSD.
@@ -73,15 +73,6 @@ struct pctrst {
 
 #ifdef _KERNEL
 
-#define MSR_TSC 0x10          /* MSR for TSC */
-#define P5MSR_CTRSEL 0x11     /* MSR for selecting both counters on P5 */
-#define P5MSR_CTR0 0x12       /* Value of Ctr0 on P5 */
-#define P5MSR_CTR1 0x13       /* Value of Ctr1 on P5 */
-#define P6MSR_CTRSEL0 0x186   /* MSR for programming CTR0 on P6 */
-#define P6MSR_CTRSEL1 0x187   /* MSR for programming CTR0 on P6 */
-#define P6MSR_CTR0 0xc1       /* Ctr0 on P6 */
-#define P6MSR_CTR1 0xc2       /* Ctr1 on P6 */
-
 #define rdmsr(msr)						\
 ({								\
   pctrval v;							\
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 0848bc8015e..84dcf069abd 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.9 2000/11/10 15:33:06 provos Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.10 2001/01/26 23:32:14 mickey Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -109,29 +109,56 @@
 #define CPUID_PAT	0x00010000	/* has page attribute table */
 #define CPUID_PSE36	0x00020000	/* has 36bit page size extension */
 #define CPUID_SER	0x00040000	/* has processor serial number */
+#define CPUID_B19	0x00080000	/* reserved */
+#define CPUID_B20	0x00100000	/* reserved */
+#define CPUID_B21	0x00200000	/* reserved */
+#define CPUID_B22	0x00400000	/* reserved */
 #define CPUID_MMX	0x00800000	/* has MMX instructions */
 #define CPUID_FXSR	0x01000000	/* has FXRSTOR instruction (Intel) */
 #define CPUID_EMMX	0x01000000	/* has extended MMX (Cyrix; obsolete) */
 #define CPUID_SIMD	0x02000000	/* has SIMD instructions (Intel) */
 #define CPUID_3DNOW	0x80000000	/* has 3DNow! instructions (AMD) */
+/* bits 26->31 also reserved. */
+
+#define CPUID_FLAGS1	"\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
+			    "\10MCE\11CX8\12APIC\13SYS1\14SYS2\15MTRR"
+#define CPUID_MASK1	0x00001fff
+#define CPUID_FLAGS2	"\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24B19" \
+			    "\25B20\26B21\27B22\30MMX\31FXSR\32SIMD\33B26" \
+			    "\34B27\35B28\36B29\37B30\40B31"
+#define CPUID_MASK2	0xffffe000
 
 /*
  * Model-specific registers for the i386 family
  */
 #define MSR_P5_MC_ADDR		0x000
 #define MSR_P5_MC_TYPE		0x001
+#define MSR_TSC			0x010
+#define	P5MSR_CTRSEL		0x011	/* P5 only (trap on P6) */
+#define	P5MSR_CTR0		0x012	/* P5 only (trap on P6) */
+#define	P5MSR_CTR1		0x013	/* P5 only (trap on P6) */
 #define MSR_APICBASE		0x01b
 #define MSR_EBL_CR_POWERON	0x02a
+#define	MSR_TEST_CTL		0x033
 #define MSR_BIOS_UPDT_TRIG	0x079
+#define	MSR_BBL_CR_D0		0x088	/* PII+ only */
+#define	MSR_BBL_CR_D1		0x089	/* PII+ only */
+#define	MSR_BBL_CR_D2		0x08a	/* PII+ only */
 #define MSR_BIOS_SIGN		0x08b
-#define MSR_PERFCTR0		0x0c1
-#define MSR_PERFCTR1		0x0c2
+#define P6MSR_CTR0		0x0c1
+#define P6MSR_CTR1		0x0c2
 #define MSR_MTRRcap		0x0fe
+#define	MSR_BBL_CR_ADDR		0x116	/* PII+ only */
+#define	MSR_BBL_CR_DECC		0x118	/* PII+ only */
+#define	MSR_BBL_CR_CTL		0x119	/* PII+ only */
+#define	MSR_BBL_CR_TRIG		0x11a	/* PII+ only */
+#define	MSR_BBL_CR_BUSY		0x11b	/* PII+ only */
+#define	MSR_BBL_CR_CTR3		0x11e	/* PII+ only */
 #define MSR_MCG_CAP		0x179
 #define MSR_MCG_STATUS		0x17a
 #define MSR_MCG_CTL		0x17b
-#define MSR_EVNTSEL0		0x186
-#define MSR_EVNTSEL1		0x187
+#define P6MSR_CTRSEL0		0x186
+#define P6MSR_CTRSEL1		0x187
 #define MSR_DEBUGCTLMSR		0x1d9
 #define MSR_LASTBRANCHFROMIP	0x1db
 #define MSR_LASTBRANCHTOIP	0x1dc
@@ -139,9 +166,32 @@
 #define MSR_LASTINTTOIP		0x1de
 #define MSR_ROB_CR_BKUPTMPDR6	0x1e0
 #define MSR_MTRRVarBase		0x200
+#define	MSR_MTRRphysMask0	0x201
+#define	MSR_MTRRphysBase1	0x202
+#define	MSR_MTRRphysMask1	0x203
+#define	MSR_MTRRphysBase2	0x204
+#define	MSR_MTRRphysMask2	0x205
+#define	MSR_MTRRphysBase3	0x206
+#define	MSR_MTRRphysMask3	0x207
+#define	MSR_MTRRphysBase4	0x208
+#define	MSR_MTRRphysMask4	0x209
+#define	MSR_MTRRphysBase5	0x20a
+#define	MSR_MTRRphysMask5	0x20b
+#define	MSR_MTRRphysBase6	0x20c
+#define	MSR_MTRRphysMask6	0x20d
+#define	MSR_MTRRphysBase7	0x20e
+#define	MSR_MTRRphysMask7	0x20f
 #define MSR_MTRR64kBase		0x250
 #define MSR_MTRR16kBase		0x258
+#define	MSR_MTRRfix16K_A0000	0x259
 #define MSR_MTRR4kBase		0x268
+#define	MSR_MTRRfix4K_C8000	0x269
+#define	MSR_MTRRfix4K_D0000	0x26a
+#define	MSR_MTRRfix4K_D8000	0x26b
+#define	MSR_MTRRfix4K_E0000	0x26c
+#define	MSR_MTRRfix4K_E8000	0x26d
+#define	MSR_MTRRfix4K_F0000	0x26e
+#define	MSR_MTRRfix4K_F8000	0x26f
 #define MSR_MTRRdefType		0x2ff
 #define MSR_MC0_CTL		0x400
 #define MSR_MC0_STATUS		0x401
@@ -204,3 +254,154 @@
 #define NCR_SIZE_32M	14
 #define NCR_SIZE_4G	15
 
+/*
+ * Performance monitor events.
+ *
+ * Note that 586-class and 686-class CPUs have different performance
+ * monitors available, and they are accessed differently:
+ *
+ *	686-class: `rdpmc' instruction
+ *	586-class: `rdmsr' instruction, CESR MSR
+ *
+ * The descriptions of these events are too lenghy to include here.
+ * See Appendix A of "Intel Architecture Software Developer's
+ * Manual, Volume 3: System Programming" for more information.
+ */
+
+/*
+ * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
+ * is CTR1.
+ */
+
+#define	PMC5_CESR_EVENT			0x003f
+#define	PMC5_CESR_OS			0x0040
+#define	PMC5_CESR_USR			0x0080
+#define	PMC5_CESR_E			0x0100
+#define	PMC5_CESR_P			0x0200
+
+/*
+ * 686-class Event Selector MSR format.
+ */
+
+#define	PMC6_EVTSEL_EVENT		0x000000ff
+#define	PMC6_EVTSEL_UNIT		0x0000ff00
+#define	PMC6_EVTSEL_UNIT_SHIFT		8
+#define	PMC6_EVTSEL_USR			(1 << 16)
+#define	PMC6_EVTSEL_OS			(1 << 17)
+#define	PMC6_EVTSEL_E			(1 << 18)
+#define	PMC6_EVTSEL_PC			(1 << 19)
+#define	PMC6_EVTSEL_INT			(1 << 20)
+#define	PMC6_EVTSEL_EN			(1 << 22)	/* PerfEvtSel0 only */
+#define	PMC6_EVTSEL_INV			(1 << 23)
+#define	PMC6_EVTSEL_COUNTER_MASK	0xff000000
+#define	PMC6_EVTSEL_COUNTER_MASK_SHIFT	24
+
+/* Data Cache Unit */
+#define	PMC6_DATA_MEM_REFS		0x43
+#define	PMC6_DCU_LINES_IN		0x45
+#define	PMC6_DCU_M_LINES_IN		0x46
+#define	PMC6_DCU_M_LINES_OUT		0x47
+#define	PMC6_DCU_MISS_OUTSTANDING	0x48
+
+/* Instruction Fetch Unit */
+#define	PMC6_IFU_IFETCH			0x80
+#define	PMC6_IFU_IFETCH_MISS		0x81
+#define	PMC6_ITLB_MISS			0x85
+#define	PMC6_IFU_MEM_STALL		0x86
+#define	PMC6_ILD_STALL			0x87
+
+/* L2 Cache */
+#define	PMC6_L2_IFETCH			0x28
+#define	PMC6_L2_LD			0x29
+#define	PMC6_L2_ST			0x2a
+#define	PMC6_L2_LINES_IN		0x24
+#define	PMC6_L2_LINES_OUT		0x26
+#define	PMC6_L2_M_LINES_INM		0x25
+#define	PMC6_L2_M_LINES_OUTM		0x27
+#define	PMC6_L2_RQSTS			0x2e
+#define	PMC6_L2_ADS			0x21
+#define	PMC6_L2_DBUS_BUSY		0x22
+#define	PMC6_L2_DBUS_BUSY_RD		0x23
+
+/* External Bus Logic */
+#define	PMC6_BUS_DRDY_CLOCKS		0x62
+#define	PMC6_BUS_LOCK_CLOCKS		0x63
+#define	PMC6_BUS_REQ_OUTSTANDING	0x60
+#define	PMC6_BUS_TRAN_BRD		0x65
+#define	PMC6_BUS_TRAN_RFO		0x66
+#define	PMC6_BUS_TRANS_WB		0x67
+#define	PMC6_BUS_TRAN_IFETCH		0x68
+#define	PMC6_BUS_TRAN_INVAL		0x69
+#define	PMC6_BUS_TRAN_PWR		0x6a
+#define	PMC6_BUS_TRANS_P		0x6b
+#define	PMC6_BUS_TRANS_IO		0x6c
+#define	PMC6_BUS_TRAN_DEF		0x6d
+#define	PMC6_BUS_TRAN_BURST		0x6e
+#define	PMC6_BUS_TRAN_ANY		0x70
+#define	PMC6_BUS_TRAN_MEM		0x6f
+#define	PMC6_BUS_DATA_RCV		0x64
+#define	PMC6_BUS_BNR_DRV		0x61
+#define	PMC6_BUS_HIT_DRV		0x7a
+#define	PMC6_BUS_HITM_DRDV		0x7b
+#define	PMC6_BUS_SNOOP_STALL		0x7e
+
+/* Floating Point Unit */
+#define	PMC6_FLOPS			0xc1
+#define	PMC6_FP_COMP_OPS_EXE		0x10
+#define	PMC6_FP_ASSIST			0x11
+#define	PMC6_MUL			0x12
+#define	PMC6_DIV			0x12
+#define	PMC6_CYCLES_DIV_BUSY		0x14
+
+/* Memory Ordering */
+#define	PMC6_LD_BLOCKS			0x03
+#define	PMC6_SB_DRAINS			0x04
+#define	PMC6_MISALIGN_MEM_REF		0x05
+#define	PMC6_EMON_KNI_PREF_DISPATCHED	0x07	/* P-III only */
+#define	PMC6_EMON_KNI_PREF_MISS		0x4b	/* P-III only */
+
+/* Instruction Decoding and Retirement */
+#define	PMC6_INST_RETIRED		0xc0
+#define	PMC6_UOPS_RETIRED		0xc2
+#define	PMC6_INST_DECODED		0xd0
+#define	PMC6_EMON_KNI_INST_RETIRED	0xd8
+#define	PMC6_EMON_KNI_COMP_INST_RET	0xd9
+
+/* Interrupts */
+#define	PMC6_HW_INT_RX			0xc8
+#define	PMC6_CYCLES_INT_MASKED		0xc6
+#define	PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
+
+/* Branches */
+#define	PMC6_BR_INST_RETIRED		0xc4
+#define	PMC6_BR_MISS_PRED_RETIRED	0xc5
+#define	PMC6_BR_TAKEN_RETIRED		0xc9
+#define	PMC6_BR_MISS_PRED_TAKEN_RET	0xca
+#define	PMC6_BR_INST_DECODED		0xe0
+#define	PMC6_BTB_MISSES			0xe2
+#define	PMC6_BR_BOGUS			0xe4
+#define	PMC6_BACLEARS			0xe6
+
+/* Stalls */
+#define	PMC6_RESOURCE_STALLS		0xa2
+#define	PMC6_PARTIAL_RAT_STALLS		0xd2
+
+/* Segment Register Loads */
+#define	PMC6_SEGMENT_REG_LOADS		0x06
+
+/* Clocks */
+#define	PMC6_CPU_CLK_UNHALTED		0x79
+
+/* MMX Unit */
+#define	PMC6_MMX_INSTR_EXEC		0xb0	/* Celeron, P-II, P-IIX only */
+#define	PMC6_MMX_SAT_INSTR_EXEC		0xb1	/* P-II and P-III only */
+#define	PMC6_MMX_UOPS_EXEC		0xb2	/* P-II and P-III only */
+#define	PMC6_MMX_INSTR_TYPE_EXEC	0xb3	/* P-II and P-III only */
+#define	PMC6_FP_MMX_TRANS		0xcc	/* P-II and P-III only */
+#define	PMC6_MMX_ASSIST			0xcd	/* P-II and P-III only */
+#define	PMC6_MMX_INSTR_RET		0xc3	/* P-II only */
+
+/* Segment Register Renaming */
+#define	PMC6_SEG_RENAME_STALLS		0xd4	/* P-II and P-III only */
+#define	PMC6_SEG_REG_RENAMES		0xd5	/* P-II and P-III only */
+#define	PMC6_RET_SEG_RENAMES		0xd6	/* P-II and P-III only */