drm/i915/gvt: Clear d3_entered on elsp cmd submission.

From Colin Xu
1df4fe5a8871f49d34d681ff5b7f93a84d50af4b in linux 5.10.y/5.10.54
c90b4503ccf42d9d367e843c223df44aa550e82a in mainline linux

1 files changed, 15 insertions, 0 deletions

diff --git a/sys/dev/pci/drm/i915/gvt/handlers.c b/sys/dev/pci/drm/i915/gvt/handlers.c
index eb342a75994..0b1ea29dcff 100644
--- a/sys/dev/pci/drm/i915/gvt/handlers.c
+++ b/sys/dev/pci/drm/i915/gvt/handlers.c
@@ -1728,6 +1728,21 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	if (drm_WARN_ON(&i915->drm, !engine))
 		return -EINVAL;
 
+	/*
+	 * Due to d3_entered is used to indicate skipping PPGTT invalidation on
+	 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after
+	 * vGPU reset if in resuming.
+	 * In S0ix exit, the device power state also transite from D3 to D0 as
+	 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After
+	 * S0ix exit, all engines continue to work. However the d3_entered
+	 * remains set which will break next vGPU reset logic (miss the expected
+	 * PPGTT invalidation).
+	 * Engines can only work in D0. Thus the 1st elsp write gives GVT a
+	 * chance to clear d3_entered.
+	 */
+	if (vgpu->d3_entered)
+		vgpu->d3_entered = false;
+
 	execlist = &vgpu->submission.execlist[engine->id];
 
 	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;