basic chip setup

3 files changed, 225 insertions, 69 deletions

diff --git a/sys/arch/sparc/dev/be.c b/sys/arch/sparc/dev/be.c
index a4090cbc31e..695041e0c60 100644
--- a/sys/arch/sparc/dev/be.c
+++ b/sys/arch/sparc/dev/be.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: be.c,v 1.3 1998/07/05 06:50:20 deraadt Exp $	*/
+/*	$OpenBSD: be.c,v 1.4 1998/07/05 09:25:53 deraadt Exp $	*/
 
 /*
  * Copyright (c) 1998 Theo de Raadt.  All rights reserved.
@@ -70,6 +70,7 @@ int	bematch __P((struct device *, void *, void *));
 void	beattach __P((struct device *, struct device *, void *));
 
 void	beinit __P((struct besoftc *));
+void	be_meminit __P((struct besoftc *));
 void	bestart __P((struct ifnet *));
 void	bestop __P((struct besoftc *));
 void	bewatchdog __P((struct ifnet *));
@@ -80,6 +81,8 @@ int	betint __P((struct besoftc *));
 int	berint __P((struct besoftc *));
 int	beqint __P((struct besoftc *));
 int	beeint __P((struct besoftc *));
+void	be_tcvr_init __P((struct besoftc *sc));
+void	be_tcvr_setspeed __P((struct besoftc *sc));
 
 struct cfdriver be_cd = {
 	NULL, "be", DV_IFNET
@@ -136,6 +139,13 @@ beattach(parent, self, aux)
 	sc->sc_memsize = qec->sc_bufsiz;
 	sc->sc_conf3 = getpropint(ca->ca_ra.ra_node, "busmaster-regval", 0);
 
+	sc->sc_burst = getpropint(ca->ca_ra.ra_node, "burst-sizes", -1);
+	if (sc->sc_burst == -1)
+		sc->sc_burst = qec->sc_burst;
+
+	/* Clamp at parent's burst sizes */
+	sc->sc_burst &= qec->sc_burst;
+
 	sc->sc_ih.ih_fun = beintr;
 	sc->sc_ih.ih_arg = sc;
 	intr_establish(pri, &sc->sc_ih);
@@ -154,6 +164,8 @@ beattach(parent, self, aux)
 	if_attach(ifp);
 	ether_ifattach(ifp);
 
+	bpfattach(&sc->sc_arpcom.ac_if.if_bpf, ifp, DLT_EN10MB,
+	    sizeof(struct ether_header));
 	printf("\n");
 }
 
@@ -253,11 +265,10 @@ int
 beintr(v)
 	void *v;
 {
-	int r = 0;
 	struct besoftc *sc = (struct besoftc *)v;
 	u_int32_t why;
+	int r = 0;
 
-#if 1
 	why = sc->sc_qr->stat;
 
 	if (why & QEC_STAT_TX)
@@ -270,8 +281,6 @@ beintr(v)
 		r |= beeint(sc);
 	if (r)
 		printf("%s: intr: why=%08x\n", sc->sc_dev.dv_xname, why);
-
-#endif
 	return (r);
 }
 
@@ -315,10 +324,6 @@ beioctl(ifp, cmd, data)
 	int s, error = 0;
 
 	s = splnet();
-	if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
-		splx(s);
-		return error;
-	}
 
 	switch (cmd) {
 	case SIOCSIFADDR:
@@ -405,85 +410,123 @@ beioctl(ifp, cmd, data)
 		}
 		break;
 	default:
+		if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
+			splx(s);
+			return error;
+		}
 		error = EINVAL;
+		break;
 	}
 	splx(s);
 	return error;
 }
 
 void
+be_tcvr_init(sc)
+	struct besoftc *sc;
+{
+}
+
+void
+be_tcvr_setspeed(sc)
+	struct besoftc *sc;
+{
+}
+
+void
 beinit(sc)
 	struct besoftc *sc;
 {
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	int s = splimp();
+	int i;
 
 	bestop(sc);
-#if 0
+
+	/* init QEC */
 	sc->sc_qr->msize = sc->sc_memsize;
 	sc->sc_qr->rsize = sc->sc_memsize / 2;
 	sc->sc_qr->tsize = sc->sc_memsize / 2;
 	sc->sc_qr->psize = 2048;
-	/*sc->sc_qr->ctrl = QEC_CTRL_BMODE | QEC_CTRL_B32;*/
+	if (sc->sc_burst & SBUS_BURST_64)
+		i = QEC_CTRL_B64;
+	else if (sc->sc_burst & SBUS_BURST_32)
+		i = QEC_CTRL_B32;
+	else
+		i = QEC_CTRL_B16;
+	sc->sc_qr->ctrl = QEC_CTRL_BMODE | i;
+
+	/* Allocate memory if not done yet */
+	if (sc->sc_desc_dva == NULL)
+		sc->sc_desc_dva = (struct be_desc *)dvma_malloc(
+		    sizeof(struct be_desc), &sc->sc_desc, M_NOWAIT);
+	if (sc->sc_bufs_dva == NULL)
+		sc->sc_bufs_dva = (struct be_bufs *)dvma_malloc(
+		    sizeof(struct be_bufs), &sc->sc_bufs, M_NOWAIT);
+
+	/* chain descriptors into buffers */
+	sc->sc_txnew = 0;
+	sc->sc_rxnew = 0;
+	sc->sc_txold = 0;
+	sc->sc_rxold = 0;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		sc->sc_desc->be_rxd[i].rx_addr =
+		    (u_int32_t)&sc->sc_bufs_dva->rx_buf[i][0];
+		sc->sc_desc->be_rxd[i].rx_flags = 0;
+	}
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		sc->sc_desc->be_txd[i].tx_addr = 0;
+		sc->sc_desc->be_txd[i].tx_flags = 0;
+	}
 
-	be_meminit(sc);
+	be_tcvr_init(sc);
+	be_tcvr_setspeed(sc);
 
-	be_write32(&treg->int_mask, 0xffff);
+	bestop(sc);
 
-	c = be_read32(&treg->cfg);
-	if (sc->sc_flags & HFLAG_FENABLE)
-		be_write32(&treg->cfg, c & ~(TCV_CFG_BENABLE));
-	else
-		be_write32(&treg->cfg, c | TCV_CFG_BENABLE);
+	sc->sc_br->mac_addr2 = (sc->sc_arpcom.ac_enaddr[4] << 8) |
+	    sc->sc_arpcom.ac_enaddr[5];
+	sc->sc_br->mac_addr1 = (sc->sc_arpcom.ac_enaddr[2] << 8) |
+	    sc->sc_arpcom.ac_enaddr[3];
+	sc->sc_br->mac_addr0 = (sc->sc_arpcom.ac_enaddr[0] << 8) |
+	    sc->sc_arpcom.ac_enaddr[1];
 
-	be_tcvr_check(sc);
-	switch (sc->tcvr_type) {
-	case none:
-		printf("%s: no transceiver type!\n", sc->sc_dev.dv_xname);
-		return;
-	case internal:
-		be_write32(&breg->xif_cfg, 0);
-		break;
-	case external:
-		be_write32(&breg->xif_cfg, BIGMAC_XCFG_MIIDISAB);
-		break;
-	}
-	be_tcvr_reset(sc);
-
-	be_reset_tx(sc);
-	be_reset_rx(sc);
-
-	be_write32(&breg->jsize, BE_DEFAULT_JSIZE);
-	be_write32(&breg->ipkt_gap1, BE_DEFAULT_IPKT_GAP1);
-	be_write32(&breg->ipkt_gap2, BE_DEFAULT_IPKT_GAP2);
-	be_write32(&breg->htable3, 0);
-	be_write32(&breg->htable2, 0);
-	be_write32(&breg->htable1, 0);
-	be_write32(&breg->htable0, 0);
-
-	be_write32(&erxreg->rx_ring,
-		sc->sc_block_addr +
-		((u_long) &sc->sc_block->be_rxd[0]) - ((u_long)sc->sc_block));
-	be_write32(&etxreg->tx_ring,
-		sc->sc_block_addr +
-		((u_long) &sc->sc_block->be_txd[0]) - ((u_long)sc->sc_block));
+	sc->sc_br->htable3 = 0;
+	sc->sc_br->htable2 = 0;
+	sc->sc_br->htable1 = 0;
+	sc->sc_br->htable0 = 0;
 
-	if (sc->sc_burst & SBUS_BURST_64)
-		be_write32(&greg->cfg, GREG_CFG_BURST64);
-	else if (sc->sc_burst & SBUS_BURST_32)
-		be_write32(&greg->cfg, GREG_CFG_BURST32);
-	else if (sc->sc_burst & SBUS_BURST_16)
-		be_write32(&greg->cfg, GREG_CFG_BURST16);
-	else {
-		printf("%s: burst size unknown\n", sc->sc_dev.dv_xname);
-		be_write32(&greg->cfg, 0);
-	}
+	sc->sc_br->rx_cfg = BE_RXCFG_HENABLE | BE_RXCFG_FIFO;
+	DELAY(20);
 
-	/* XXX TODO: set interrupt mask: (GOTFRAME | RCNTEXP) */
-	be_write32(&greg->imask, GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR);
+	sc->sc_br->tx_cfg = BE_TXCFG_FIFO;
+	sc->sc_br->rand_seed = 0xbd;
 
-	be_write32(&etxreg->tx_rsize, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
-	be_write32(&etxreg->cfg, be_read32(&etxreg->cfg) | ETX_CFG_DMAENABLE);
-	be_write32(&breg->rx_cfg, BIGMAC_RXCFG_HENABLE);
+	sc->sc_br->xif_cfg = BE_XCFG_ODENABLE | BE_XCFG_RESV;
 
-	be_auto_negotiate(sc);
-#endif
+	sc->sc_cr->rxds = (u_int32_t)&sc->sc_desc_dva->be_rxd[0];
+	sc->sc_cr->txds = (u_int32_t)&sc->sc_desc_dva->be_txd[0];
+
+	sc->sc_cr->rxwbufptr = 0;
+	sc->sc_cr->rxrbufptr = 0;
+	sc->sc_cr->txwbufptr = sc->sc_memsize;
+	sc->sc_cr->txrbufptr = sc->sc_memsize;
+	
+	sc->sc_br->imask = 0;
+
+	sc->sc_cr->rimask = 0;
+	sc->sc_cr->timask = 0;
+	sc->sc_cr->qmask = 0;
+	sc->sc_cr->bmask = 0;
+
+	sc->sc_br->jsize = 4;
+
+	sc->sc_cr->ccnt = 0;
+
+	sc->sc_br->tx_cfg |= BE_TXCFG_ENABLE;
+	sc->sc_br->rx_cfg |= BE_RXCFG_ENABLE;
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+	splx(s);
 }
diff --git a/sys/arch/sparc/dev/bereg.h b/sys/arch/sparc/dev/bereg.h
index 66e30a46b44..408a1e94407 100644
--- a/sys/arch/sparc/dev/bereg.h
+++ b/sys/arch/sparc/dev/bereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bereg.h,v 1.1 1998/07/04 07:57:52 deraadt Exp $	*/
+/*	$OpenBSD: bereg.h,v 1.2 1998/07/05 09:25:55 deraadt Exp $	*/
 
 /*
  * Copyright (c) 1998 Theo de Raadt.  All rights reserved.
@@ -77,6 +77,67 @@ struct be_bregs {
 	volatile u_int32_t afilter_mask;     /* Address filter mask */
 };
 
+/* BE XIF config register. */
+#define BE_XCFG_ODENABLE   0x00000001 /* Output driver enable */
+#define BE_XCFG_RESV       0x00000002 /* Reserved, write always as 1 */
+#define BE_XCFG_MLBACK     0x00000004 /* Loopback-mode MII enable */
+#define BE_XCFG_SMODE      0x00000008 /* Enable serial mode */
+
+/* BE status register. */
+#define BE_STAT_GOTFRAME   0x00000001 /* Received a frame */
+#define BE_STAT_RCNTEXP    0x00000002 /* Receive frame counter expired */
+#define BE_STAT_ACNTEXP    0x00000004 /* Align-error counter expired */
+#define BE_STAT_CCNTEXP    0x00000008 /* CRC-error counter expired */
+#define BE_STAT_LCNTEXP    0x00000010 /* Length-error counter expired */
+#define BE_STAT_RFIFOVF    0x00000020 /* Receive FIFO overflow */
+#define BE_STAT_CVCNTEXP   0x00000040 /* Code-violation counter expired */
+#define BE_STAT_SENTFRAME  0x00000100 /* Transmitted a frame */
+#define BE_STAT_TFIFO_UND  0x00000200 /* Transmit FIFO underrun */
+#define BE_STAT_MAXPKTERR  0x00000400 /* Max-packet size error */
+#define BE_STAT_NCNTEXP    0x00000800 /* Normal-collision counter expired */
+#define BE_STAT_ECNTEXP    0x00001000 /* Excess-collision counter expired */
+#define BE_STAT_LCCNTEXP   0x00002000 /* Late-collision counter expired */
+#define BE_STAT_FCNTEXP    0x00004000 /* First-collision counter expired */
+#define BE_STAT_DTIMEXP    0x00008000 /* Defer-timer expired */
+
+/* BE interrupt mask register. */
+#define BE_IMASK_GOTFRAME  0x00000001 /* Received a frame */
+#define BE_IMASK_RCNTEXP   0x00000002 /* Receive frame counter expired */
+#define BE_IMASK_ACNTEXP   0x00000004 /* Align-error counter expired */
+#define BE_IMASK_CCNTEXP   0x00000008 /* CRC-error counter expired */
+#define BE_IMASK_LCNTEXP   0x00000010 /* Length-error counter expired */
+#define BE_IMASK_RFIFOVF   0x00000020 /* Receive FIFO overflow */
+#define BE_IMASK_CVCNTEXP  0x00000040 /* Code-violation counter expired */
+#define BE_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
+#define BE_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
+#define BE_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
+#define BE_IMASK_NCNTEXP   0x00000800 /* Normal-collision counter expired */
+#define BE_IMASK_ECNTEXP   0x00001000 /* Excess-collision counter expired */
+#define BE_IMASK_LCCNTEXP  0x00002000 /* Late-collision counter expired */
+#define BE_IMASK_FCNTEXP   0x00004000 /* First-collision counter expired */
+#define BE_IMASK_DTIMEXP   0x00008000 /* Defer-timer expired */
+
+/* BE transmit config register. */
+#define BE_TXCFG_ENABLE    0x00000001 /* Enable the transmitter */
+#define BE_TXCFG_FIFO      0x00000010 /* Default tx fthresh... */
+#define BE_TXCFG_SMODE     0x00000020 /* Enable slow transmit mode */
+#define BE_TXCFG_CIGN      0x00000040 /* Ignore transmit collisions */
+#define BE_TXCFG_FCSOFF    0x00000080 /* Do not emit FCS */
+#define BE_TXCFG_DBACKOFF  0x00000100 /* Disable backoff */
+#define BE_TXCFG_FULLDPLX  0x00000200 /* Enable full-duplex */
+
+/* BE receive config register. */
+#define BE_RXCFG_ENABLE    0x00000001 /* Enable the receiver */
+#define BE_RXCFG_FIFO      0x0000000e /* Default rx fthresh... */
+#define BE_RXCFG_PSTRIP    0x00000020 /* Pad byte strip enable */
+#define BE_RXCFG_PMISC     0x00000040 /* Enable promiscous mode */
+#define BE_RXCFG_DERR      0x00000080 /* Disable error checking */
+#define BE_RXCFG_DCRCS     0x00000100 /* Disable CRC stripping */
+#define BE_RXCFG_ME        0x00000200 /* Receive packets addressed to me */
+#define BE_RXCFG_PGRP      0x00000400 /* Enable promisc group mode */
+#define BE_RXCFG_HENABLE   0x00000800 /* Enable the hash filter */
+#define BE_RXCFG_AENABLE   0x00001000 /* Enable the address filter */
+
 struct be_cregs {
 	volatile u_int32_t ctrl;       /* Control */
 	volatile u_int32_t stat;       /* Status */
@@ -85,7 +146,7 @@ struct be_cregs {
 	volatile u_int32_t rimask;     /* RX Interrupt Mask */
 	volatile u_int32_t timask;     /* TX Interrupt Mask */
 	volatile u_int32_t qmask;      /* QEC Error Interrupt Mask */
-	volatile u_int32_t bmask;      /* BigMAC Error Interrupt Mask */
+	volatile u_int32_t bmask;      /* BE Error Interrupt Mask */
 	volatile u_int32_t rxwbufptr;  /* Local memory rx write ptr */
 	volatile u_int32_t rxrbufptr;  /* Local memory rx read ptr */
 	volatile u_int32_t txwbufptr;  /* Local memory tx write ptr */
@@ -97,3 +158,48 @@ struct be_tregs {
 	u_int32_t	tcvr_pal;
 	u_int32_t	mgmt_pal;
 };
+
+struct be_rxd {
+	u_int32_t rx_flags;
+	u_int32_t rx_addr;
+};
+
+#define RXD_OWN      0x80000000 /* Ownership. */
+#define RXD_UPDATE   0x10000000 /* Being Updated? */
+#define RXD_LENGTH   0x000007ff /* Packet Length. */
+
+struct be_txd {
+	u_int32_t tx_flags;
+	u_int32_t tx_addr;
+};
+
+#define TXD_OWN      0x80000000 /* Ownership. */
+#define TXD_SOP      0x40000000 /* Start Of Packet */
+#define TXD_EOP      0x20000000 /* End Of Packet */
+#define TXD_UPDATE   0x10000000 /* Being Updated? */
+#define TXD_LENGTH   0x000007ff /* Packet Length. */
+
+
+
+
+#define TX_RING_MAXSIZE   256
+#define RX_RING_MAXSIZE   256
+#define TX_RING_SIZE      256
+#define RX_RING_SIZE      256
+
+#define SUN4C_PKT_BUF_SZ        1546
+#define SUN4C_RX_BUFF_SIZE      SUN4C_PKT_BUF_SZ
+#define SUN4C_TX_BUFF_SIZE      SUN4C_PKT_BUF_SZ
+#define SUN4C_RX_RING_SIZE      16
+#define SUN4C_TX_RING_SIZE      16
+
+struct be_desc {
+	struct be_rxd be_rxd[RX_RING_MAXSIZE];
+	struct be_txd be_txd[TX_RING_MAXSIZE];
+};
+
+struct be_bufs {
+	char	tx_buf[SUN4C_TX_RING_SIZE][SUN4C_TX_BUFF_SIZE];
+	char	pad[2];
+	char	rx_buf[SUN4C_RX_RING_SIZE][SUN4C_RX_BUFF_SIZE];
+};
diff --git a/sys/arch/sparc/dev/bevar.h b/sys/arch/sparc/dev/bevar.h
index 4673bec4927..9f526f82578 100644
--- a/sys/arch/sparc/dev/bevar.h
+++ b/sys/arch/sparc/dev/bevar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bevar.h,v 1.3 1998/07/05 06:50:21 deraadt Exp $	*/
+/*	$OpenBSD: bevar.h,v 1.4 1998/07/05 09:25:56 deraadt Exp $	*/
 
 /*
  * Copyright (c) 1998 Theo de Raadt.  All rights reserved.
@@ -46,4 +46,11 @@ struct besoftc {
 	u_int	sc_rev;
 
 	int	sc_promisc;
+	int	sc_burst;
+
+	int	sc_txnew, sc_txold;
+	int	sc_rxnew, sc_rxold;
+
+	struct	be_desc *sc_desc, *sc_desc_dva;
+	struct	be_bufs	*sc_bufs, *sc_bufs_dva;
 };