Support for the SMC 91Cxx family of ethernet chips from NetBSD.

3 files changed, 1799 insertions, 0 deletions

diff --git a/sys/dev/ic/smc91cxx.c b/sys/dev/ic/smc91cxx.c
new file mode 100644
index 00000000000..08f58e61085
--- /dev/null
+++ b/sys/dev/ic/smc91cxx.c
@@ -0,0 +1,1284 @@
+/*	$OpenBSD: smc91cxx.c,v 1.1 1998/09/11 06:55:27 fgsch Exp $	*/
+/*	$NetBSD: smc91cxx.c,v 1.11 1998/08/08 23:51:41 mycroft Exp $	*/
+
+/*-
+ * Copyright (c) 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*      
+ * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
+ * All rights reserved.
+ *      
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Gardner Buchanan.
+ * 4. The name of Gardner Buchanan may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *       
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *      
+ *   from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp
+ */      
+
+/*
+ * Core driver for the SMC 91Cxx family of Ethernet chips.
+ *
+ * Memory allocation interrupt logic is drived from an SMC 91C90 driver
+ * written for NetBSD/amiga by Michael Hitch.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h> 
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+#include <sys/syslog.h>
+#include <sys/socket.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/ioctl.h> 
+#include <sys/errno.h>
+#if NRND > 0
+#include <sys/rnd.h>
+#endif
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#ifdef __NetBSD__
+#include <net/if_ether.h>
+#include <net/if_media.h> 
+#endif
+
+#ifdef INET
+#include <netinet/in.h> 
+#ifdef __NetBSD__
+#include <netinet/if_inarp.h>
+#else
+#include <netinet/if_ether.h>
+#endif
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#endif
+
+#ifdef NS
+#include <netns/ns.h>
+#include <netns/ns_if.h>
+#endif
+
+#if defined(CCITT) && defined(LLC)
+#include <sys/socketvar.h>
+#include <netccitt/x25.h>
+#include <netccitt/pk.h>
+#include <netccitt/pk_var.h>
+#include <netccitt/pk_extern.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+#endif
+
+#include <dev/ic/smc91cxxreg.h>
+#include <dev/ic/smc91cxxvar.h>
+
+/* XXX Hardware padding doesn't work yet(?) */
+#define	SMC91CXX_SW_PAD
+
+#define ETHER_ADDR_LEN		6
+
+const char *smc91cxx_idstrs[] = {
+	NULL,				/* 0 */
+	NULL,				/* 1 */
+	NULL,				/* 2 */
+	"SMC91C90/91C92",		/* 3 */
+	"SMC91C94",			/* 4 */
+	"SMC91C95",			/* 5 */
+	NULL,				/* 6 */
+	"SMC91C100",			/* 7 */
+	NULL,				/* 8 */
+	NULL,				/* 9 */
+	NULL,				/* 10 */
+	NULL,				/* 11 */
+	NULL,				/* 12 */
+	NULL,				/* 13 */
+	NULL,				/* 14 */
+	NULL,				/* 15 */
+};
+
+#ifdef __NetBSD__
+/* Supported media types. */
+const int smc91cxx_media[] = {
+	IFM_ETHER|IFM_10_T,
+	IFM_ETHER|IFM_10_5,
+};
+#define	NSMC91CxxMEDIA	(sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0]))
+#endif
+
+struct cfdriver sm_cd = {
+	NULL, "sm", DV_IFNET
+};
+
+#ifdef __NetBSD__
+int	smc91cxx_mediachange __P((struct ifnet *));
+void	smc91cxx_mediastatus __P((struct ifnet *, struct ifmediareq *));
+
+int	smc91cxx_set_media __P((struct smc91cxx_softc *, int));
+#endif
+
+void	smc91cxx_init __P((struct smc91cxx_softc *));
+void	smc91cxx_read __P((struct smc91cxx_softc *));
+void	smc91cxx_reset __P((struct smc91cxx_softc *));
+void	smc91cxx_start __P((struct ifnet *));
+void	smc91cxx_resume __P((struct smc91cxx_softc *));
+void	smc91cxx_stop __P((struct smc91cxx_softc *));
+void	smc91cxx_watchdog __P((struct ifnet *));
+int	smc91cxx_ioctl __P((struct ifnet *, u_long, caddr_t));
+
+int	smc91cxx_enable __P((struct smc91cxx_softc *));
+void	smc91cxx_disable __P((struct smc91cxx_softc *));
+
+/* XXX Should be in a common header file. */
+#define	ETHER_MAX_LEN	1518
+#define	ETHER_MIN_LEN	64
+#define	ETHER_CRC_LEN	4
+
+static __inline int ether_cmp __P((void *, void *));
+static __inline int
+ether_cmp(va, vb)
+	void *va, *vb;
+{
+	u_int8_t *a = va;
+	u_int8_t *b = vb;
+
+	return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) ||
+		(a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0]));
+}
+
+void
+smc91cxx_attach(sc, myea)
+	struct smc91cxx_softc *sc;
+	u_int8_t *myea;
+{
+#ifdef __NetBSD__
+	struct ifnet *ifp = &sc->sc_ec.ec_if;
+#else
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+#endif
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	const char *idstr;
+	u_int16_t tmp;
+#ifdef __NetBSD__
+	u_int8_t enaddr[ETHER_ADDR_LEN];
+#endif
+	int i, aui;
+
+	/* Make sure the chip is stopped. */
+	smc91cxx_stop(sc);
+
+	SMC_SELECT_BANK(sc, 3);
+	tmp = bus_space_read_2(bst, bsh, REVISION_REG_W);
+	idstr = smc91cxx_idstrs[RR_ID(tmp)];
+	printf("%s: ", sc->sc_dev.dv_xname);
+	if (idstr != NULL)
+		printf("%s, ", idstr);
+	else
+		printf("unknown chip id %d, ", RR_ID(tmp));
+	printf("revision %d\n", RR_REV(tmp));
+
+	/* Read the station address from the chip. */
+	SMC_SELECT_BANK(sc, 1);
+	if (myea == NULL) {
+#ifdef __NetBSD__
+		myea = enaddr;
+#endif
+		for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
+			tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i);
+#ifdef __NetBSD__
+			myea[i + 1] = (tmp >> 8) & 0xff;
+			myea[i] = tmp & 0xff;
+#else
+			sc->sc_arpcom.ac_enaddr[i + 1] = (tmp >>8) & 0xff;
+			sc->sc_arpcom.ac_enaddr[i] = tmp & 0xff;
+#endif
+		}
+#ifdef __NetBSD__
+	}
+#else
+	} else {
+		bcopy(myea, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
+	}
+#endif
+	printf("%s: MAC address %s, ", sc->sc_dev.dv_xname,
+#ifdef __NetBSD__
+	    ether_sprintf(myea));
+#else
+	    ether_sprintf(sc->sc_arpcom.ac_enaddr));
+#endif
+
+	/* ..and default media. */
+	tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
+	printf("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ?
+	    "AUI" : "UTP");
+
+	/* Initialize the ifnet structure. */
+	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+	ifp->if_softc = sc;
+	ifp->if_start = smc91cxx_start;
+	ifp->if_ioctl = smc91cxx_ioctl;
+	ifp->if_watchdog = smc91cxx_watchdog;
+	ifp->if_flags =
+	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
+
+	/* Attach the interface. */
+	if_attach(ifp);
+#ifdef __NetBSD__
+	ether_ifattach(ifp, myea);
+#else
+	ether_ifattach(ifp);
+#endif
+
+#ifdef __NetBSD__
+	/* Initialize the media structures. */
+	ifmedia_init(&sc->sc_media, 0, smc91cxx_mediachange,
+	    smc91cxx_mediastatus);
+	for (i = 0; i < NSMC91CxxMEDIA; i++)
+		ifmedia_add(&sc->sc_media, smc91cxx_media[i], 0, NULL);
+	ifmedia_set(&sc->sc_media, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T));
+#endif
+
+#if NBPFILTER > 0
+	bpfattach(&sc->sc_arpcom.ac_if.if_bpf, ifp, DLT_EN10MB,
+		sizeof(struct ether_header));
+#endif
+
+#if NRND > 0
+	rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET);
+#endif
+}
+
+#ifdef __NetBSD__
+/*
+ * Change media according to request.
+ */
+int
+smc91cxx_mediachange(ifp)
+	struct ifnet *ifp;
+{
+	struct smc91cxx_softc *sc = ifp->if_softc;
+
+	return (smc91cxx_set_media(sc, sc->sc_media.ifm_media));
+}
+
+int
+smc91cxx_set_media(sc, media)
+	struct smc91cxx_softc *sc;
+	int media;
+{
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	u_int16_t tmp;
+
+	/*
+	 * If the interface is not currently powered on, just return.
+	 * When it is enabled later, smc91cxx_init() will properly set
+	 * up the media for us.
+	 */
+	if (sc->sc_enabled == 0)
+		return (0);
+
+	if (IFM_TYPE(media) != IFM_ETHER)
+		return (EINVAL);
+
+	switch (IFM_SUBTYPE(media)) {
+	case IFM_10_T:
+	case IFM_10_5:
+		SMC_SELECT_BANK(sc, 1);
+		tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
+		if (IFM_SUBTYPE(media) == IFM_10_5)
+			tmp |= CR_AUI_SELECT;
+		else
+			tmp &= ~CR_AUI_SELECT;
+		bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp);
+		delay(20000);	/* XXX is this needed? */
+		break;
+
+	default:
+		return (EINVAL);
+	}
+
+	return (0);
+}
+
+/*
+ * Notify the world which media we're using.
+ */
+void
+smc91cxx_mediastatus(ifp, ifmr)
+	struct ifnet *ifp;
+	struct ifmediareq *ifmr;
+{
+	struct smc91cxx_softc *sc = ifp->if_softc;
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	u_int16_t tmp;
+
+	if (sc->sc_enabled == 0) {
+		ifmr->ifm_active = IFM_ETHER | IFM_NONE;
+		ifmr->ifm_status = 0;
+		return;
+	}
+
+	SMC_SELECT_BANK(sc, 1);
+	tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
+	ifmr->ifm_active =
+	    IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T);
+}
+#endif
+
+/*
+ * Reset and initialize the chip.
+ */
+void
+smc91cxx_init(sc)
+	struct smc91cxx_softc *sc;
+{
+#ifdef __NetBSD__
+	struct ifnet *ifp = &sc->sc_ec.ec_if;
+#endif
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	u_int16_t tmp;
+#ifdef __NetBSD__
+	u_int8_t *enaddr;
+#endif
+	int s, i;
+
+	s = splnet();
+
+	/*
+	 * This resets the registersmostly to defaults, but doesn't
+	 * affect the EEPROM.  After the reset cycle, we pause briefly
+	 * for the chip to recover.
+	 *
+	 * XXX how long are we really supposed to delay?  --thorpej
+	 */
+	SMC_SELECT_BANK(sc, 0);
+	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET);
+	delay(100);
+	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
+	delay(200);
+
+	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
+
+	/* Set the Ethernet address. */
+	SMC_SELECT_BANK(sc, 1);
+#ifdef __NetBSD__
+	enaddr = (u_int8_t *)LLADDR(ifp->if_sadl);
+	for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
+		tmp = enaddr[i + 1] << 8 | enaddr[i];
+		bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp);
+	}
+#else
+	for (i = 0; i < ETHER_ADDR_LEN; i++ )
+		bus_space_write_1(bst, bsh, IAR_ADDR0_REG_W + i,
+		    sc->sc_arpcom.ac_enaddr[i]);
+#endif
+
+	/*
+	 * Set the control register to automatically release successfully
+	 * transmitted packets (making the best use of our limited memory)
+	 * and enable the EPH interrupt on certain TX errors.
+	 */
+	bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE |
+	    CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE));
+
+	/*
+	 * Reset the MMU and wait for it to be un-busy.
+	 */
+	SMC_SELECT_BANK(sc, 2);
+	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET);
+	while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
+		/* XXX bound this loop! */ ;
+
+	/*
+	 * Disable all interrupts.
+	 */
+	bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
+
+	/*
+	 * Set current media.
+	 */
+#ifdef __NetBSD__
+	smc91cxx_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
+#endif
+
+	/*
+	 * Set the receive filter.  We want receive enable and auto
+	 * strip of CRC from received packet.  If we are in promisc. mode,
+	 * then set that bit as well.
+	 *
+	 * XXX Initialize multicast filter.  For now, we just accept
+	 * XXX all multicast.
+	 */
+	SMC_SELECT_BANK(sc, 0);
+
+	tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL;
+	if (ifp->if_flags & IFF_PROMISC)
+		tmp |= RCR_PROMISC;
+
+	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp);
+
+	/*
+	 * Set transmitter control to "enabled".
+	 */
+	tmp = TCR_ENABLE;
+
+#ifndef SMC91CXX_SW_PAD
+	/*
+	 * Enable hardware padding of transmitted packets.
+	 * XXX doesn't work?
+	 */
+	tmp |= TCR_PAD_ENABLE;
+#endif
+
+	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp);
+
+	/*
+	 * Now, enable interrupts.
+	 */
+	SMC_SELECT_BANK(sc, 2);
+
+	bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
+	    IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT);
+
+	/* Interface is now running, with no output active. */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	/*
+	 * Attempt to start any pending transmission.
+	 */
+	smc91cxx_start(ifp);
+
+	splx(s);
+}
+
+/*
+ * Start output on an interface.
+ * Must be called at splnet or interrupt level.
+ */
+void
+smc91cxx_start(ifp)
+	struct ifnet *ifp;
+{
+	struct smc91cxx_softc *sc = ifp->if_softc;
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	u_int len;
+	struct mbuf *m, *top;
+	u_int16_t length, npages;
+	u_int8_t packetno;
+	int timo, pad;
+
+	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
+		return;
+
+ again:
+	/*
+	 * Peek at the next packet.
+	 */
+	if ((m = ifp->if_snd.ifq_head) == NULL)
+		return;
+
+	/*
+	 * Compute the frame length and set pad to give an overall even
+	 * number of bytes.  Below, we assume that the packet length
+	 * is even.
+	 */
+	for (len = 0, top = m; m != NULL; m = m->m_next)
+		len += m->m_len;
+	pad = (len & 1);
+
+	/*
+	 * We drop packets that are too large.  Perhaps we should
+	 * truncate them instead?
+	 */
+	if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) {
+		printf("%s: large packet discarded\n", sc->sc_dev.dv_xname);
+		ifp->if_oerrors++;
+		IF_DEQUEUE(&ifp->if_snd, m);
+		m_freem(m);
+		goto readcheck;
+	}
+
+#ifdef SMC91CXX_SW_PAD
+	/*
+	 * Not using hardware padding; pad to ETHER_MIN_LEN.
+	 */
+	if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN))
+		pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
+#endif
+
+	length = pad + len;
+
+	/*
+	 * The MMU has a 256 byte page size.  The MMU expects us to
+	 * ask for "npages - 1".  We include space for the status word,
+	 * byte count, and control bytes in the allocation request.
+	 */
+	npages = (length + 6) >> 8;
+
+	/*
+	 * Now allocate the memory.
+	 */
+	SMC_SELECT_BANK(sc, 2);
+	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages);
+
+	timo = MEMORY_WAIT_TIME;
+	do {
+		if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT)
+			break;
+		delay(1);
+	} while (--timo);
+
+	packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B);
+
+	if (packetno & ARR_FAILED || timo == 0) {
+		/*
+		 * No transmit memory is available.  Record the number
+		 * of requestd pages and enable the allocation completion
+		 * interrupt.  Set up the watchdog timer in case we miss
+		 * the interrupt.  Mark the interface as active so that
+		 * no one else attempts to transmit while we're allocating
+		 * memory.
+		 */
+		bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
+		    bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT);
+
+		ifp->if_timer = 5;
+		ifp->if_flags |= IFF_OACTIVE;
+
+		return;
+	}
+
+	/*
+	 * We have a packet number - set the data window.
+	 */
+	bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno);
+
+	/*
+	 * Point to the beginning of the packet.
+	 */
+	bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */);
+
+	/*
+	 * Send the packet length (+6 for stats, length, and control bytes)
+	 * and the status word (set to zeros).
+	 */
+	bus_space_write_2(bst, bsh, DATA_REG_W, 0);
+	bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff);
+	bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff);
+
+	/*
+	 * Get the packet from the kernel.  This will include the Ethernet
+	 * frame header, MAC address, etc.
+	 */
+	IF_DEQUEUE(&ifp->if_snd, m);
+
+	/*
+	 * Push the packet out to the card.
+	 */
+	for (top = m; m != NULL; m = m->m_next) {
+		/* Words... */
+		bus_space_write_multi_2(bst, bsh, DATA_REG_W,
+		    mtod(m, u_int16_t *), m->m_len >> 1);
+
+		/* ...and the remaining byte, if any. */
+		if (m->m_len & 1)
+			bus_space_write_1(bst, bsh, DATA_REG_B,
+			  *(u_int8_t *)(mtod(m, u_int8_t *) + (m->m_len - 1)));
+	}
+
+#ifdef SMC91CXX_SW_PAD
+	/*
+	 * Push out padding.
+	 */
+	while (pad > 1) {
+		bus_space_write_2(bst, bsh, DATA_REG_W, 0);
+		pad -= 2;
+	}
+	if (pad)
+		bus_space_write_1(bst, bsh, DATA_REG_B, 0);
+#endif
+
+	/*
+	 * Push out control byte and unused packet byte.  The control byte
+	 * is 0, meaning the packet is even lengthed and no special
+	 * CRC handling is necessary.
+	 */
+	bus_space_write_2(bst, bsh, DATA_REG_W, 0);
+
+	/*
+	 * Enable transmit interrupts and let the chip go.  Set a watchdog
+	 * in case we miss the interrupt.
+	 */
+	bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
+	    bus_space_read_1(bst, bsh, INTR_MASK_REG_B) |
+	    IM_TX_INT | IM_TX_EMPTY_INT);
+
+	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE);
+
+	ifp->if_timer = 5;
+
+#if NBPFILTER > 0
+	/* Hand off a copy to the bpf. */
+	if (ifp->if_bpf)
+		bpf_mtap(ifp->if_bpf, top);
+#endif
+
+	ifp->if_opackets++;
+	m_freem(top);
+
+ readcheck:
+	/*
+	 * Check for incoming pcakets.  We don't want to overflow the small
+	 * RX FIFO.  If nothing has arrived, attempt to queue another
+	 * transmit packet.
+	 */
+	if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY)
+		goto again;
+}
+
+/*
+ * Interrupt service routine.
+ */
+int
+smc91cxx_intr(arg)
+	void *arg;
+{
+	struct smc91cxx_softc *sc = arg;
+#ifdef __NetBSD__
+	struct ifnet *ifp = &sc->sc_ec.ec_if;
+#else
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+#endif
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	u_int8_t mask, interrupts, status;
+	u_int16_t packetno, tx_status, card_stats;
+
+	if (sc->sc_enabled == 0)
+		return (0);
+
+	SMC_SELECT_BANK(sc, 2);
+
+	/*
+	 * Obtain the current interrupt mask.
+	 */
+	mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B);
+
+	/*
+	 * Get the set of interrupt which occurred and eliminate any
+	 * which are not enabled.
+	 */
+	interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B);
+	status = interrupts & mask;
+
+	/* Ours? */
+	if (status == 0)
+		return (0);
+
+	/*
+	 * It's ours; disable all interrupts while we process them.
+	 */
+	bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
+
+	/*
+	 * Receive overrun interrupts.
+	 */
+	if (status & IM_RX_OVRN_INT) {
+		bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT);
+		ifp->if_ierrors++;
+	}
+
+	/*
+	 * Receive interrupts.
+	 */
+	if (status & IM_RCV_INT) {
+#if 1 /* DIAGNOSTIC */
+		packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
+		if (packetno & FIFO_REMPTY)
+			printf("%s: receive interrupt on empty fifo\n",
+			    sc->sc_dev.dv_xname);
+		else
+#endif
+		smc91cxx_read(sc);
+	}
+
+	/*
+	 * Memory allocation interrupts.
+	 */
+	if (status & IM_ALLOC_INT) {
+		/* Disable this interrupt. */
+		mask &= ~IM_ALLOC_INT;
+
+		/*
+		 * Release the just-allocated memory.  We will reallocate
+		 * it through the normal start logic.
+		 */
+		while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
+			/* XXX bound this loop! */ ;
+		bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT);
+
+		ifp->if_flags &= ~IFF_OACTIVE;
+		ifp->if_timer = 0;
+	}
+
+	/*
+	 * Transmit complete interrupt.  Handle transmission error messages.
+	 * This will only be called on error condition because of AUTO RELEASE
+	 * mode.
+	 */
+	if (status & IM_TX_INT) {
+		bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT);
+
+		packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) &
+		    FIFO_TX_MASK;
+
+		/*
+		 * Select this as the packet to read from.
+		 */
+		bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno);
+
+		/*
+		 * Position the pointer to the beginning of the packet.
+		 */
+		bus_space_write_2(bst, bsh, POINTER_REG_W,
+		    PTR_AUTOINC | PTR_READ /* | 0x0000 */);
+
+		/*
+		 * Fetch the TX status word.  This will be a copy of
+		 * the EPH_STATUS_REG_W at the time of the transmission
+		 * failure.
+		 */
+		tx_status = bus_space_read_2(bst, bsh, DATA_REG_W);
+
+		if (tx_status & EPHSR_TX_SUC)
+			printf("%s: successful packet caused TX interrupt?!\n",
+			    sc->sc_dev.dv_xname);
+		else
+			ifp->if_oerrors++;
+
+		if (tx_status & EPHSR_LATCOL)
+			ifp->if_collisions++;
+
+		/*
+		 * Some of these errors disable the transmitter; reenable it.
+		 */
+		SMC_SELECT_BANK(sc, 0);
+#ifdef SMC91CXX_SW_PAD
+		bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE);
+#else
+		bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W,
+		    TCR_ENABLE | TCR_PAD_ENABLE);
+#endif
+
+		/*
+		 * Kill the failed packet and wait for the MMU to unbusy.
+		 */
+		SMC_SELECT_BANK(sc, 2);
+		while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
+			/* XXX bound this loop! */ ;
+		bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT);
+
+		ifp->if_timer = 0;
+	}
+
+	/*
+	 * Transmit underrun interrupts.  We use this opportunity to
+	 * update transmit statistics from the card.
+	 */
+	if (status & IM_TX_EMPTY_INT) {
+		bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
+
+		/* Disable this interrupt. */
+		mask &= ~IM_TX_EMPTY_INT;
+
+		SMC_SELECT_BANK(sc, 0);
+		card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W);
+
+		/* Single collisions. */
+		ifp->if_collisions += card_stats & ECR_COLN_MASK;
+
+		/* Multiple collisions. */
+		ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
+
+		SMC_SELECT_BANK(sc, 2);
+
+		ifp->if_timer = 0;
+	}
+
+	/*
+	 * Other errors.  Reset the interface.
+	 */
+	if (status & IM_EPH_INT) {
+		smc91cxx_stop(sc);
+		smc91cxx_init(sc);
+	}
+
+	/*
+	 * Attempt to queue more packets for transmission.
+	 */
+	smc91cxx_start(ifp);
+
+	/*
+	 * Reenable the interrupts we wish to receive now that processing
+	 * is complete.
+	 */
+	mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B);
+	bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask);
+
+#if NRND > 0
+	if (status)
+		rnd_add_uint32(&sc->rnd_source, status);
+#endif
+
+	return (1);
+}
+
+/*
+ * Read a packet from the card and pass it up to the kernel.
+ * NOTE!  WE EXPECT TO BE IN REGISTER WINDOW 2!
+ */
+void
+smc91cxx_read(sc)
+	struct smc91cxx_softc *sc;
+{
+#ifdef __NetBSD__
+	struct ifnet *ifp = &sc->sc_ec.ec_if;
+#else
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+#endif
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+	struct ether_header *eh;
+	struct mbuf *m;
+	u_int16_t status, packetno, packetlen;
+	u_int8_t *data;
+
+ again:
+	/*
+	 * Set data pointer to the beginning of the packet.  Since
+	 * PTR_RCV is set, the packet number will be found automatically
+	 * in FIFO_PORTS_REG_W, FIFO_RX_MASK.
+	 */
+	bus_space_write_2(bst, bsh, POINTER_REG_W,
+	    PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */);
+
+	/*
+	 * First two words are status and packet length.
+	 */
+	status = bus_space_read_2(bst, bsh, DATA_REG_W);
+	packetlen = bus_space_read_2(bst, bsh, DATA_REG_W);
+
+	/*
+	 * The packet length includes 3 extra words: status, length,
+	 * and an extra word that includes the control byte.
+	 */
+	packetlen -= 6;
+
+	/*
+	 * Account for receive errors and discard.
+	 */
+	if (status & RS_ERRORS) {
+		ifp->if_ierrors++;
+		goto out;
+	}
+
+	/*
+	 * Adjust for odd-length packet.
+	 */
+	if (status & RS_ODDFRAME)
+		packetlen++;
+
+	/*
+	 * Allocate a header mbuf.
+	 */
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m == NULL)
+		goto out;
+
+	m->m_pkthdr.rcvif = ifp;
+	m->m_pkthdr.len = m->m_len = packetlen;
+
+	/*
+	 * Always put the packet in a cluster.
+	 * XXX should chain small mbufs if less than threshold.
+	 */
+	MCLGET(m, M_DONTWAIT);
+	if ((m->m_flags & M_EXT) == 0) {
+		m_freem(m);
+		ifp->if_ierrors++;
+		printf("%s: can't allocate cluster for incoming packet\n",
+		    sc->sc_dev.dv_xname);
+		goto out;
+	}
+
+	/*
+	 * Pull the packet off the interface.
+	 */
+	eh = mtod(m, struct ether_header *);
+	data = mtod(m, u_int8_t *);
+	bus_space_read_multi_2(bst, bsh, DATA_REG_W, (u_int16_t *)data,
+	    packetlen >> 1);
+	if (packetlen & 1) {
+		data += packetlen & ~1;
+		*data = bus_space_read_1(bst, bsh, DATA_REG_B);
+	}
+
+	ifp->if_ipackets++;
+
+#if NBPFILTER > 0
+	/*
+	 * Hand the packet off to bpf listeners.  If there's a bpf listener,
+	 * we need to check if the packet is ours.
+	 */
+	if (ifp->if_bpf) {
+		bpf_mtap(ifp->if_bpf, m);
+
+		if ((ifp->if_flags & IFF_PROMISC) &&
+		    (eh->ether_dhost[0] & 1) == 0 &&	/* !mcast and !bcast */
+#ifdef __NetBSD__
+		    ether_cmp(eh->ether_dhost, LLADDR(ifp->if_sadl))) {
+#else
+		    ether_cmp(eh->ether_dhost, sc->sc_arpcom.ac_enaddr)) {
+#endif
+			m_freem(m);
+			goto out;
+		}
+	}
+#endif
+
+	/*
+	 * Strip the ethernet header.
+	 */
+	m->m_pkthdr.len = m->m_len = packetlen - sizeof(struct ether_header);
+	m->m_data += sizeof(struct ether_header);
+
+	ether_input(ifp, eh, m);
+
+ out:
+	/*
+	 * Tell the card to free the memory occupied by this packet.
+	 */
+	while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
+		/* XXX bound this loop! */ ;
+	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE);
+
+	/*
+	 * Check for another packet.
+	 */
+	packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
+	if (packetno & FIFO_REMPTY)
+		return;
+	goto again;
+}
+
+/*
+ * Process an ioctl request.
+ */
+int
+smc91cxx_ioctl(ifp, cmd, data)
+	struct ifnet *ifp;
+	u_long cmd;
+	caddr_t data;
+{
+	struct smc91cxx_softc *sc = ifp->if_softc;
+	struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ifreq *ifr = (struct ifreq *)data;
+	int s, error = 0;
+
+	s = splnet();
+
+	switch (cmd) {
+	case SIOCSIFADDR:
+		if ((error = smc91cxx_enable(sc)) != 0)
+			break;
+		ifp->if_flags |= IFF_UP;
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+		smc91cxx_init(sc);
+#ifdef __NetBSD__
+		arp_ifinit(ifp, ifa);
+#else
+		arp_ifinit(&sc->sc_arpcom, ifa);
+#endif
+		break;
+#endif
+#ifdef NS
+		case AF_NS:
+		    {
+			struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
+
+			if (ns_nullhost(*ina))
+				ina->x_host =
+				    *(union ns_host *)LLADDR(ifp->if_sadl);
+			else {
+				bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 
+				    ETHER_ADDR_LEN);
+			}
+
+			/*
+			 * Set new address.  Reset, because the receiver
+			 * has to be stopped before we can set the new
+			 * MAC address.
+			 */
+			smc91cxx_reset(sc);
+			break;
+		    }
+#endif
+		default:
+			smc91cxx_init(sc);
+			break;
+		}
+		break;
+
+#if defined(CCITT) && defined(LLC)
+	case SIOCSIFCONF_X25:
+		if ((error = smc91cxx_enable(sc)) != 0)
+			break;
+		ifp->if_flags |= IFF_UP;
+		ifa->ifa_rtrequest = cons_rtrequest;	/* XXX */
+		error = x25_llcglue(PRC_IFUP, ifa->ifa_addr);
+		if (error == 0)
+			smc91cxx_init(sc);
+		break;
+#endif
+
+	case SIOCSIFFLAGS:
+		if ((ifp->if_flags & IFF_UP) == 0 &&
+		    (ifp->if_flags & IFF_RUNNING) != 0) {
+			/*
+			 * If interface is marked down and it is running,
+			 * stop it.
+			 */
+			smc91cxx_stop(sc);
+			ifp->if_flags &= ~IFF_RUNNING;
+			smc91cxx_disable(sc);
+		} else if ((ifp->if_flags & IFF_UP) != 0 &&
+			   (ifp->if_flags & IFF_RUNNING) == 0) {
+			/*
+			 * If interface is marked up and it is stopped,
+			 * start it.
+			 */
+			if ((error = smc91cxx_enable(sc)) != 0)
+				break;
+			smc91cxx_init(sc);
+		} else if (sc->sc_enabled) {
+			/*
+			 * Reset the interface to pick up changes in any
+			 * other flags that affect hardware registers.
+			 */
+			smc91cxx_reset(sc);
+		}
+		break;
+
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		if (sc->sc_enabled == 0) {
+			error = EIO;
+			break;
+		}
+
+		error = (cmd == SIOCADDMULTI) ?
+#ifdef __NetBSD__
+		    ether_addmulti(ifr, &sc->sc_ec) :
+		    ether_delmulti(ifr, &sc->sc_ec);
+#else
+		    ether_addmulti(ifr, &sc->sc_arpcom) :
+		    ether_delmulti(ifr, &sc->sc_arpcom);
+#endif
+		if (error == ENETRESET) {
+			/*
+			 * Multicast list has changed; set the hardware
+			 * filter accordingly.
+			 */
+			smc91cxx_reset(sc);
+			error = 0;
+		}
+		break;
+
+#ifdef __NetBSD__
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
+		break;
+#endif
+
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	splx(s);
+	return (error);
+}
+
+/*
+ * Reset the interface.
+ */
+void
+smc91cxx_reset(sc)
+	struct smc91cxx_softc *sc;
+{
+	int s;
+
+	s = splnet();
+	smc91cxx_stop(sc);
+	smc91cxx_init(sc);
+	splx(s);
+}
+
+/*
+ * Watchdog timer.
+ */
+void
+smc91cxx_watchdog(ifp)
+	struct ifnet *ifp;
+{
+	struct smc91cxx_softc *sc = ifp->if_softc;
+
+	log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
+#ifdef __NetBSD__
+	ifp->if_oerrors++;
+#else
+	++sc->sc_arpcom.ac_if.if_oerrors;
+#endif
+
+	smc91cxx_reset(sc);
+}
+
+/*
+ * Stop output on the interface.
+ */
+void
+smc91cxx_stop(sc)
+	struct smc91cxx_softc *sc;
+{
+	bus_space_tag_t bst = sc->sc_bst;
+	bus_space_handle_t bsh = sc->sc_bsh;
+
+	/*
+	 * Clear interrupt mask; disable all interrupts.
+	 */
+	SMC_SELECT_BANK(sc, 2);
+	bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
+
+	/*
+	 * Disable transmitter and receiver.
+	 */
+	SMC_SELECT_BANK(sc, 0);
+	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
+	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
+
+	/*
+	 * Cancel watchdog timer.
+	 */
+#ifdef __NetBSD__
+	sc->sc_ec.ec_if.if_timer = 0;
+#else
+	sc->sc_arpcom.ac_if.if_timer = 0;
+#endif
+}
+
+/*
+ * Enable power on the interface.
+ */
+int
+smc91cxx_enable(sc)
+	struct smc91cxx_softc *sc;
+{
+
+	if (sc->sc_enabled == 0 && sc->sc_enable != NULL) {
+		if ((*sc->sc_enable)(sc) != 0) {
+			printf("%s: device enable failed\n",
+			    sc->sc_dev.dv_xname);
+			return (EIO);
+		}
+	}
+
+	sc->sc_enabled = 1;
+	return (0);
+}
+
+/*
+ * Disable power on the interface.
+ */
+void
+smc91cxx_disable(sc)
+	struct smc91cxx_softc *sc;
+{
+
+	if (sc->sc_enabled != 0 && sc->sc_disable != NULL) {
+		(*sc->sc_disable)(sc);
+		sc->sc_enabled = 0;
+	}
+}
diff --git a/sys/dev/ic/smc91cxxreg.h b/sys/dev/ic/smc91cxxreg.h
new file mode 100644
index 00000000000..9f041f70b1d
--- /dev/null
+++ b/sys/dev/ic/smc91cxxreg.h
@@ -0,0 +1,440 @@
+/*	$OpenBSD: smc91cxxreg.h,v 1.1 1998/09/11 06:55:29 fgsch Exp $	*/
+/*	$NetBSD: smc91cxxreg.h,v 1.2 1997/09/02 00:10:58 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Gardner Buchanan.
+ * 4. The name of Gardner Buchanan may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *   from FreeBSD Id: if_snreg.h,v 1.4 1996/03/18 15:47:30 gardner Exp
+ */
+
+/*
+ * This file contains register information and access macros for
+ * the SMC91xxx chipset.
+ *
+ * Information contained in this file was obtained from the SMC91C92
+ * and SMC91C94 manuals from SMC.  You will need one of these in order
+ * to make any meaningful changes to this driver.  Information about
+ * obtaining one can be found at http://www.smc.com in the components
+ * division.
+ *
+ * This FreeBSD driver is derived in part from the smc9194 Linux driver
+ * by Erik Stahlman.
+ */
+
+
+/*
+ * Wait time for memory to be free.  This probably shouldn't be
+ * tuned that much, as waiting for this means nothing else happens
+ * in the system
+ */
+#define	MEMORY_WAIT_TIME	1000
+
+
+/* The SMC91xxx uses 16 I/O ports */
+#define	SMC_IOSIZE		16
+
+
+/*
+ * A description of the SMC registers is probably in order here,
+ * although for details, the SMC datasheet is invaluable.
+ * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet
+ * Controller With RAM", Rev. 12/0/94.  Constant definitions I give
+ * here are loosely based on the mnemonic names given to them in the
+ * data sheet, but there are many exceptions.
+ *
+ * Basically, the chip has 4 banks of registers (0 to 3), which
+ * are accessed by writing a number into the BANK_SELECT register
+ * (I also use a SMC_SELECT_BANK macro for this).  Registers are
+ * either Byte or Word sized.  My constant definitions end in _B
+ * or _W as appropriate.
+ *
+ * The banks are arranged so that for most purposes, bank 2 is all
+ * that is needed for normal run time tasks.
+ */
+
+
+/*
+ * Bank Select Register.  This also doubles as
+ * a chip identification register.  This register
+ * is mapped at the same position in all banks.
+ */
+#define	BANK_SELECT_REG_W	0x0e
+#define	BSR_DETECT_MASK		0xff00
+#define	BSR_DETECT_VALUE	0x3300
+
+
+/*
+ * BANK 0
+ */
+
+/*
+ * Transmit Control Register controls some aspects of the transmit
+ * behavior of the Ethernet Protocol Handler.
+ */
+#define	TXMIT_CONTROL_REG_W	0x00
+
+#define	TCR_ENABLE	0x0001	/* if this is 1, we can transmit */
+#define	TCR_LOOP	0x0002	/* Enable internal analogue loopback */
+#define	TCR_FORCOL	0x0004	/* Force Collision on next TX */
+#define	TCR_PAD_ENABLE	0x0080	/* Pad short packets to 64 bytes */
+#define	TCR_NOCRC	0x0100	/* Do not append CRC */
+#define	TCR_MON_CSN	0x0400	/* monitors the carrier status */
+#define	TCR_FDUPLX	0x0800	/* receive packets sent out */
+#define	TCR_STP_SQET	0x1000	/* stop transmitting if Signal quality error */
+#define	TCR_EPH_LOOP	0x2000	/* Enable internal digital loopback */
+
+
+/*
+ * Status of the last transmitted frame and instantaneous status of
+ * the Ethernet Protocol Handler jumbled together.  In auto-release
+ * mode this information is simply discarded after each TX.  This info
+ * is copied to the status word of in-memory packets after transmit
+ * where relevent statuses can be checked.
+ */
+#define	EPH_STATUS_REG_W 0x02
+
+#define	EPHSR_TX_SUC	0x0001	/* Transmit was successful */
+#define	EPHSR_SNGLCOL	0x0002	/* Single collision occurred */
+#define	EPHSR_MULCOL	0x0004	/* Multiple Collisions occurred */
+#define	EPHSR_LTX_MULT	0x0008	/* Transmit was a multicast */
+#define	EPHSR_16COL	0x0010	/* 16 Collisions occurred, TX disabled */
+#define	EPHSR_SQET	0x0020	/* SQE Test failed, TX disabled */
+#define	EPHSR_LTX_BRD	0x0040	/* Transmit was a broadcast */
+#define	EPHSR_DEFR	0x0080	/* TX deferred due to carrier det. */
+#define	EPHSR_LATCOL	0x0200	/* Late collision detected, TX disabled */
+#define	EPHSR_LOST_CAR	0x0400	/* Lost carrier sense, TX disabled */
+#define	EPHSR_EXC_DEF	0x0800	/* Excessive deferrals in TX >2 MAXETHER
+				 * times */
+#define	EPHSR_CTR_ROL	0x1000	/* Some ECR Counter(s) rolled over */
+#define	EPHSR_RX_OVRN	0x2000	/* Receiver overrun, packets dropped */
+#define	EPHSR_LINK_OK	0x4000	/* Link integrity is OK */
+#define	EPHSR_TXUNRN	0x8000	/* Transmit underrun */
+
+
+/*
+ * Receiver Control Register controls some aspects of the receive
+ * behavior of the Ethernet Protocol Handler.
+ */
+#define	RECV_CONTROL_REG_W 0x04
+
+#define	RCR_RX_ABORT	0x0001	/* Received huge packet */
+#define	RCR_PROMISC	0x0002	/* enable promiscuous mode */
+#define	RCR_ALMUL	0x0004	/* receive all multicast packets */
+#define	RCR_ENABLE	0x0100	/* IFF this is set, we can recieve packets */
+#define	RCR_STRIP_CRC	0x0200	/* strips CRC */
+#define	RCR_GAIN_BITS	0x0c00	/* PLL Gain control (for testing) */
+#define	RCR_FILT_CAR	0x4000	/* Enable 12 bit carrier filter */
+#define	RCR_SOFTRESET	0x8000	/* Resets the EPH logic */
+
+
+/*
+ * TX Statistics counters
+ */
+#define	COUNTER_REG_W	0x06
+
+#define	ECR_COLN_MASK	0x000f	/* Vanilla collisions */
+#define	ECR_MCOLN_MASK	0x00f0	/* Multiple collisions */
+#define	ECR_DTX_MASK	0x0f00	/* Deferred transmits */
+#define	ECR_EXDTX_MASK	0xf000	/* Excessively deferred transmits */
+
+
+/*
+ * Memory Information
+ */
+#define	MEM_INFO_REG_W	0x08
+
+#define	MIR_FREE_MASK	0xff00	/* Free memory pages available */
+#define	MIR_TOTAL_MASK	0x00ff	/* Total memory pages available */
+
+
+/*
+ * Memory Configuration
+ */
+#define	MEM_CFG_REG_W	0x0a
+
+#define	MCR_TXRSV_MASK	0x001f	/* Count of pages reserved for transmit */
+
+
+/*
+ * Bank 0, Register 0x0c is unused in the SMC91C92
+ */
+
+
+/*
+ * BANK 1
+ */
+
+/*
+ * Adapter configuration
+ */
+#define	CONFIG_REG_W	0x00
+
+#define	CR_INT_SEL0	0x0002	/* Interrupt selector */
+#define	CR_INT_SEL1	0x0004	/* Interrupt selector */
+#define	CR_DIS_LINK	0x0040	/* Disable 10BaseT Link Test */
+#define	CR_16BIT	0x0080	/* Bus width */
+#define	CR_AUI_SELECT	0x0100	/* Use external (AUI) Transceiver */
+#define	CR_SET_SQLCH	0x0200	/* Squelch level */
+#define	CR_FULL_STEP	0x0400	/* AUI signalling mode */
+#define	CR_NOW_WAIT_ST	0x1000	/* Disable bus wait states */
+
+
+/*
+ * The contents of this port are used by the adapter
+ * to decode its I/O address.  We use it as a varification
+ * that the adapter is detected properly when probing.
+ */
+#define	BASE_ADDR_REG_W	0x02	/* The selected I/O Base addr. */
+
+
+/*
+ * These registers hold the Ethernet MAC address.
+ */
+#define	IAR_ADDR0_REG_W	0x04	/* My Ethernet address */
+#define	IAR_ADDR1_REG_W	0x06	/* My Ethernet address */
+#define	IAR_ADDR2_REG_W	0x08	/* My Ethernet address */
+
+
+/*
+ * General purpose register used for talking to the EEPROM.
+ */
+#define	GENERAL_REG_W	0x0a
+
+
+/*
+ * Control register used for talking to the EEPROM and
+ * setting some EPH functions.
+ */
+#define	CONTROL_REG_W	0x0c
+
+#define	CTR_STORE	 0x0001	/* Store something to EEPROM */
+#define	CTR_RELOAD	 0x0002	/* Read EEPROM into registers */
+#define	CTR_EEPROM_SEL	 0x0004	/* Select registers for Reload/Store */
+#define	CTR_TE_ENABLE	 0x0020	/* Enable TX Error detection via EPH_INT */
+#define	CTR_CR_ENABLE	 0x0040	/* Enable Counter Rollover via EPH_INT */
+#define	CTR_LE_ENABLE	 0x0080	/* Enable Link Error detection via EPH_INT */
+#define	CTR_AUTO_RELEASE 0x0800	/* Enable auto release mode for TX */
+#define	CTR_POWERDOWN	 0x2000	/* Enter powerdown mode */
+#define	CTR_RCV_BAD	 0x4000	/* Enable receipt of frames with bad CRC */
+
+
+/*
+ * BANK 2
+ */
+
+
+/*
+ * Memory Management Unit Control Register
+ * Controls allocation of memory to receive and
+ * transmit functions.
+ */
+#define	MMU_CMD_REG_W	0x00
+
+#define	MMUCR_BUSY	0x0001	/* MMU busy performing a release */
+
+/*
+ * MMU Commands:
+ */
+#define	MMUCR_NOP	0x0000	/* Do nothing */
+#define	MMUCR_ALLOC	0x0020	/* Or with number of 256 byte packets - 1 */
+#define	MMUCR_RESET	0x0040	/* Reset MMU State */
+#define	MMUCR_REMOVE	0x0060	/* Dequeue (but not free) current RX packet */
+#define	MMUCR_RELEASE	0x0080	/* Dequeue and free the current RX packet */
+#define	MMUCR_FREEPKT	0x00a0	/* Release packet in PNR register */
+#define	MMUCR_ENQUEUE	0x00c0	/* Enqueue the packet for transmit */
+#define	MMUCR_RESETTX	0x00e0	/* Reset transmit queues */
+
+/*
+ * Packet Number at TX Area
+ */
+#define	PACKET_NUM_REG_B 0x02
+
+/*
+ * Packet number resulting from MMUCR_ALLOC
+ */
+#define	ALLOC_RESULT_REG_B 0x03
+#define	ARR_FAILED	0x80
+
+/*
+ * Transmit and receive queue heads
+ */
+#define	FIFO_PORTS_REG_W 0x04
+#define	FIFO_REMPTY	0x8000
+#define	FIFO_TEMPTY	0x0080
+#define	FIFO_RX_MASK	0x7f00
+#define	FIFO_TX_MASK	0x007f
+
+
+/*
+ * The address within the packet for reading/writing.  The
+ * PTR_RCV bit is tricky.  When PTR_RCV==1, the packet number
+ * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK.
+ * When PTR_RCV==0, the packet number to be written is found
+ * in the PACKET_NUM_REG_B.
+ */
+#define	POINTER_REG_W	0x06
+
+#define	PTR_READ	0x2000	/* Intended access mode */
+#define	PTR_AUTOINC	0x4000	/* Do auto inc after read/write */
+#define	PTR_RCV		0x8000	/* FIFO_RX is packet, otherwise PNR is packet */
+
+/*
+ * Data I/O register to be used in conjunction with
+ * The pointer register to read and write data from the
+ * card.  The same register can be used for byte and word
+ * ops.
+ */
+#define	DATA_REG_W	0x08
+#define	DATA_REG_B	0x08
+#define	DATA_1_REG_B	0x08
+#define	DATA_2_REG_B	0x0a
+
+
+/*
+ * Sense interrupt status (READ)
+ */
+#define	INTR_STAT_REG_B	0x0c
+
+
+/*
+ * Acknowledge interrupt sources (WRITE)
+ */
+#define	INTR_ACK_REG_B	0x0c
+
+
+/*
+ * Interrupt mask.  Bit set indicates interrupt allowed.
+ */
+#define	INTR_MASK_REG_B	0x0d
+
+/*
+ * Interrupts
+ */
+#define	IM_RCV_INT	0x01	/* A packet has been received */
+#define	IM_TX_INT	0x02	/* Packet TX complete */
+#define	IM_TX_EMPTY_INT	0x04	/* No packets left to TX  */
+#define	IM_ALLOC_INT	0x08	/* Memory allocation completed */
+#define	IM_RX_OVRN_INT	0x10	/* Receiver was overrun */
+#define	IM_EPH_INT	0x20	/* Misc. EPH conditions (see CONTROL_REG_W) */
+#define	IM_ERCV_INT	0x40	/* not on SMC9192 */
+
+
+/*
+ * BANK 3
+ */
+
+
+/*
+ * Multicast subscriptions.
+ * The multicast handling in the SMC90Cxx is quite complicated.  A table
+ * of multicast address subscriptions is provided and a clever way of
+ * speeding the search of that table by hashing is implemented in the
+ * hardware.  I have ignored this and simply subscribed to all multicasts
+ * and let the kernel deal with the results.
+ */
+#define	MULTICAST1_REG_W 0x00
+#define	MULTICAST2_REG_W 0x02
+#define	MULTICAST3_REG_W 0x04
+#define	MULTICAST4_REG_W 0x06
+
+/*
+ * These registers do not exist on SMC9192, or at least
+ * are not documented in the SMC91C92 data sheet.
+ * The REVISION_REG_W register does however seem to work.
+ */
+#define	MGMT_REG_W	0x08
+
+#define	REVISION_REG_W	0x0a	/* (hi: chip id low: rev #) */
+#define	RR_REV(x)	((x) & 0x0f)
+#define	RR_ID(x)	(((x) >> 4) & 0x0f)
+
+#define	ERCV_REG_W	0x0c
+
+/*
+ * These are constants expected to be found in the
+ * chip id register.
+ */
+#define	CHIP_9190	3
+#define	CHIP_9194	4
+#define	CHIP_9195	5
+#define	CHIP_91100	7
+
+
+/*
+ * When packets are stuffed into the card or sucked out of the card
+ * they are set up more or less as follows:
+ *
+ * Addr msbyte   lsbyte
+ * 00   SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status
+ * 02   RRRRR             - RESERVED (unused)
+ * 02        CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored)
+ * 04   DDDDDDDD DDDDDDDD - DESTINATION ADDRESS
+ * 06   DDDDDDDD DDDDDDDD        (48 bit Ethernet MAC Address)
+ * 08   DDDDDDDD DDDDDDDD
+ * 0A   SSSSSSSS SSSSSSSS - SOURCE ADDRESS
+ * 0C   SSSSSSSS SSSSSSSS        (48 bit Ethernet MAC Address)
+ * 0E   SSSSSSSS SSSSSSSS
+ * 10   PPPPPPPP PPPPPPPP
+ * ..   PPPPPPPP PPPPPPPP
+ * C-2  CCCCCCCC          - CONTROL BYTE
+ * C-2           PPPPPPPP - Last data byte (If odd length)
+ *
+ * The STATUS_WORD is derived from the EPH_STATUS_REG_W register
+ * during transmit and is composed of another set of bits described
+ * below during receive.
+ */
+
+
+/*
+ * Receive status bits.  These values are found in the status word
+ * field of a received packet.  For receive packets I use the RS_ODDFRAME
+ * to detect whether a frame has an extra byte on it.  The CTLB_ODD
+ * bit of the control byte tells the same thing.
+ */
+#define	RS_MULTICAST	0x0001	/* Packet is multicast */
+#define	RS_HASH_MASK	0x007e	/* Mask of multicast hash value */
+#define	RS_TOOSHORT	0x0400	/* Frame was a runt, <64 bytes */
+#define	RS_TOOLONG	0x0800	/* Frame was giant, >1518 */
+#define	RS_ODDFRAME	0x1000	/* Frame is odd lengthed */
+#define	RS_BADCRC	0x2000	/* Frame had CRC error */
+#define	RS_ALGNERR	0x8000	/* Frame had alignment error */
+#define	RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
+
+#define	RLEN_MASK	0x07ff	/* Significant length bits in RX length */
+
+/*
+ * The control byte has the following significant bits.
+ * For transmit, the CTLB_ODD bit specifies whether an extra byte
+ * is present in the frame.  Bit 0 of the byte count field is
+ * ignored.  I just pad every frame to even length and forget about
+ * it.
+ */
+#define	CTLB_CRC	0x10	/* Add CRC for this packet (TX only) */
+#define	CTLB_ODD	0x20	/* The packet length is ODD */
diff --git a/sys/dev/ic/smc91cxxvar.h b/sys/dev/ic/smc91cxxvar.h
new file mode 100644
index 00000000000..b67ffdc1a00
--- /dev/null
+++ b/sys/dev/ic/smc91cxxvar.h
@@ -0,0 +1,75 @@
+/*	$OpenBSD: smc91cxxvar.h,v 1.1 1998/09/11 06:55:30 fgsch Exp $	*/
+/*	$NetBSD: smc91cxxvar.h,v 1.4 1997/10/15 05:56:13 explorer Exp $	*/
+
+/*-
+ * Copyright (c) 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if NRND > 0
+#include <sys/rnd.h>
+#endif
+
+struct smc91cxx_softc {
+	struct	device sc_dev;		/* generic device glue */
+#ifdef __NetBSD__
+	struct	ethercom sc_ethercom;	/* ethernet common glue */
+#endif
+	struct	arpcom sc_arpcom;	/* ethernet common glue */
+
+	bus_space_tag_t sc_bst;		/* bus space */
+	bus_space_handle_t sc_bsh;
+
+#ifdef __NetBSD__
+	struct	ifmedia sc_media;	/* our media info */
+#endif
+	int sc_media;			/* our media info */
+
+	/* Power management hooks and state. */
+	int	(*sc_enable) __P((struct smc91cxx_softc *));
+	void	(*sc_disable) __P((struct smc91cxx_softc *));
+	int	sc_enabled;
+
+#if NRND > 0
+	rndsource_element_t rnd_source;
+#endif
+};
+
+#define	SMC_SELECT_BANK(sc, x)						\
+	bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh,			\
+	    BANK_SELECT_REG_W, (x))
+
+void	smc91cxx_attach __P((struct smc91cxx_softc *, u_int8_t *));
+int	smc91cxx_intr __P((void *));