diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2014-03-30 02:17:51 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2014-03-30 02:17:51 +0000 |
| commit | 85a8733c75e1e1a4c2f460186e4334aaaf9b742d (patch) | |
| tree | 816c1ff5ee5571e2149051fc4a13c8c393041ff1 /sys | |
| parent | ce18653fa53291538fc604f8f9221496b57dc039 (diff) | |
drm/radeon: disable pll sharing for DP on DCE4.1
From Alex Deucher
2e673e623ba5a604c02fadcad9bf75e6a0ee9705 in ubuntu 3.8
9ef4e1d000a5b335fcebfcf8aef3405e59574c89 in mainline linux
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/drm/radeon/atombios_crtc.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/sys/dev/pci/drm/radeon/atombios_crtc.c b/sys/dev/pci/drm/radeon/atombios_crtc.c index 74ec22493aa..617fb26e6af 100644 --- a/sys/dev/pci/drm/radeon/atombios_crtc.c +++ b/sys/dev/pci/drm/radeon/atombios_crtc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: atombios_crtc.c,v 1.4 2014/02/15 14:23:10 jsg Exp $ */ +/* $OpenBSD: atombios_crtc.c,v 1.5 2014/03/30 02:17:50 jsg Exp $ */ /* * Copyright 2007-8 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. @@ -1660,6 +1660,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) return ATOM_PPLL1; DRM_ERROR("unable to allocate a PPLL\n"); return ATOM_PPLL_INVALID; + } else if (ASIC_IS_DCE41(rdev)) { + /* Don't share PLLs on DCE4.1 chips */ + if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { + if (rdev->clock.dp_extclk) + /* skip PPLL programming if using ext clock */ + return ATOM_PPLL_INVALID; + } + pll_in_use = radeon_get_pll_use_mask(crtc); + if (!(pll_in_use & (1 << ATOM_PPLL1))) + return ATOM_PPLL1; + if (!(pll_in_use & (1 << ATOM_PPLL2))) + return ATOM_PPLL2; + DRM_ERROR("unable to allocate a PPLL\n"); + return ATOM_PPLL_INVALID; } else if (ASIC_IS_DCE4(rdev)) { /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, * depending on the asic: @@ -1687,7 +1701,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) if (pll != ATOM_PPLL_INVALID) return pll; } - } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ + } else { /* use the same PPLL for all monitors with the same clock */ pll = radeon_get_shared_nondp_ppll(crtc); if (pll != ATOM_PPLL_INVALID) |