regen

2 files changed, 262 insertions, 2 deletions

diff --git a/sys/dev/pci/pcidevs.h b/sys/dev/pci/pcidevs.h
index 40a9ad7c0f7..b9bb0336f6f 100644
--- a/sys/dev/pci/pcidevs.h
+++ b/sys/dev/pci/pcidevs.h
@@ -2,7 +2,7 @@
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	OpenBSD: pcidevs,v 1.1935 2020/10/04 10:35:35 jsg Exp 
+ *	OpenBSD: pcidevs,v 1.1936 2020/10/05 01:58:32 jsg Exp 
  */
 /*	$NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $	*/
 
@@ -5423,6 +5423,17 @@
 #define	PCI_PRODUCT_INTEL_RCUXX	0x9622		/* RCUxx I2O RAID */
 #define	PCI_PRODUCT_INTEL_RCU31	0x9641		/* RCU31 I2O RAID */
 #define	PCI_PRODUCT_INTEL_RCU31L	0x96a1		/* RCU31L I2O RAID */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_1	0x9a40		/* Xe Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_2	0x9a49		/* Xe Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_3	0x9a59		/* Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT1_1	0x9a60		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT1_2	0x9a68		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT1_3	0x9a70		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_4	0x9a78		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_5	0x9ac0		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_6	0x9ac9		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_7	0x9ad9		/* UHD Graphics */
+#define	PCI_PRODUCT_INTEL_TGL_GT2_8	0x9af8		/* UHD Graphics */
 #define	PCI_PRODUCT_INTEL_CML_U_GT1_1	0x9b21		/* UHD Graphics */
 #define	PCI_PRODUCT_INTEL_CML_U_GT2_1	0x9b41		/* UHD Graphics */
 #define	PCI_PRODUCT_INTEL_CORE10G_U_HB	0x9b61		/* Core 10G Host */
@@ -5596,12 +5607,53 @@
 #define	PCI_PRODUCT_INTEL_PINEVIEW_M_DMI	0xa010		/* Pineview DMI */
 #define	PCI_PRODUCT_INTEL_PINEVIEW_M_IGC_1	0xa011		/* Pineview Video */
 #define	PCI_PRODUCT_INTEL_PINEVIEW_M_IGC_2	0xa012		/* Pineview Video */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_ESPI	0xa082		/* 500 Series eSPI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_P2SB	0xa0a0		/* 500 Series P2SB */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PMC	0xa0a1		/* 500 Series PMC */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_SMB	0xa0a3		/* 500 Series SMBus */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_SPI_FLASH	0xa0a4		/* 500 Series SPI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_TH	0xa0a6		/* 500 Series TH */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_UART_1	0xa0a8		/* 500 Series UART */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_UART_2	0xa0a9		/* 500 Series UART */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_1	0xa0aa		/* 500 Series GSPI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_2	0xa0ab		/* 500 Series GSPI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_9	0xa0b0		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_10	0xa0b1		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_11	0xa0b2		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_12	0xa0b3		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_1	0xa0b8		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_2	0xa0b9		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_3	0xa0ba		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_4	0xa0bb		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_5	0xa0bc		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_6	0xa0bd		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_7	0xa0be		/* 500 Series PCIE */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_8	0xa0bf		/* 500 Series PCIE */
 #define	PCI_PRODUCT_INTEL_500SERIES_LP_I2C_1	0xa0c5		/* 500 Series I2C */
 #define	PCI_PRODUCT_INTEL_500SERIES_LP_I2C_2	0xa0c6		/* 500 Series I2C */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_UART_3	0xa0c7		/* 500 Series UART */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_HDA	0xa0c8		/* 500 Series HD Audio */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_THC_1	0xa0d0		/* 500 Series THC */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_THC_2	0xa0d1		/* 500 Series THC */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_AHCI	0xa0d3		/* 500 Series AHCI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_RAID	0xa0d7		/* 500 Series RAID */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_UART_4	0xa0da		/* 500 Series UART */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_HECI_1	0xa0e0		/* 500 Series HECI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_HECI_2	0xa0e1		/* 500 Series HECI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_IDER	0xa0e2		/* 500 Series IDE-R */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_KT	0xa0e3		/* 500 Series KT */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_HECI_3	0xa0e4		/* 500 Series HECI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_HECI_4	0xa0e5		/* 500 Series HECI */
 #define	PCI_PRODUCT_INTEL_500SERIES_LP_I2C_3	0xa0e8		/* 500 Series I2C */
 #define	PCI_PRODUCT_INTEL_500SERIES_LP_I2C_4	0xa0e9		/* 500 Series I2C */
 #define	PCI_PRODUCT_INTEL_500SERIES_LP_I2C_5	0xa0ea		/* 500 Series I2C */
 #define	PCI_PRODUCT_INTEL_500SERIES_LP_I2C_6	0xa0eb		/* 500 Series I2C */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_XHCI	0xa0ed		/* 500 Series xHCI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_XDCI	0xa0ee		/* 500 Series xDCI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_SRAM	0xa0ef		/* 500 Series Shared SRAM */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_3	0xa0fb		/* 500 Series GSPI */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_ISH	0xa0fc		/* 500 Series ISH */
+#define	PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_4	0xa0fd		/* 500 Series GSPI */
 #define	PCI_PRODUCT_INTEL_100SERIES_AHCI_1	0xa102		/* 100 Series AHCI */
 #define	PCI_PRODUCT_INTEL_100SERIES_AHCI_2	0xa103		/* 100 Series AHCI */
 #define	PCI_PRODUCT_INTEL_100SERIES_RAID_1	0xa105		/* 100 Series RAID */
diff --git a/sys/dev/pci/pcidevs_data.h b/sys/dev/pci/pcidevs_data.h
index d9086172f26..8ca7be07fc5 100644
--- a/sys/dev/pci/pcidevs_data.h
+++ b/sys/dev/pci/pcidevs_data.h
@@ -2,7 +2,7 @@
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	OpenBSD: pcidevs,v 1.1935 2020/10/04 10:35:35 jsg Exp 
+ *	OpenBSD: pcidevs,v 1.1936 2020/10/05 01:58:32 jsg Exp 
  */
 
 /*	$NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $	*/
@@ -19124,6 +19124,50 @@ static const struct pci_known_product pci_known_products[] = {
 	    "RCU31L I2O RAID",
 	},
 	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_1,
+	    "Xe Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_2,
+	    "Xe Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_3,
+	    "Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT1_1,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT1_2,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT1_3,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_4,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_5,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_6,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_7,
+	    "UHD Graphics",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_TGL_GT2_8,
+	    "UHD Graphics",
+	},
+	{
 	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT1_1,
 	    "UHD Graphics",
 	},
@@ -19816,6 +19860,94 @@ static const struct pci_known_product pci_known_products[] = {
 	    "Pineview Video",
 	},
 	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_ESPI,
+	    "500 Series eSPI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_P2SB,
+	    "500 Series P2SB",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PMC,
+	    "500 Series PMC",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB,
+	    "500 Series SMBus",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SPI_FLASH,
+	    "500 Series SPI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_TH,
+	    "500 Series TH",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_UART_1,
+	    "500 Series UART",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_UART_2,
+	    "500 Series UART",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_1,
+	    "500 Series GSPI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_2,
+	    "500 Series GSPI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_9,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_10,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_11,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_12,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_1,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_2,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_3,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_4,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_5,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_6,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_7,
+	    "500 Series PCIE",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_PCIE_8,
+	    "500 Series PCIE",
+	},
+	{
 	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_1,
 	    "500 Series I2C",
 	},
@@ -19824,6 +19956,58 @@ static const struct pci_known_product pci_known_products[] = {
 	    "500 Series I2C",
 	},
 	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_UART_3,
+	    "500 Series UART",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_HDA,
+	    "500 Series HD Audio",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_THC_1,
+	    "500 Series THC",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_THC_2,
+	    "500 Series THC",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_AHCI,
+	    "500 Series AHCI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_RAID,
+	    "500 Series RAID",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_UART_4,
+	    "500 Series UART",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_HECI_1,
+	    "500 Series HECI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_HECI_2,
+	    "500 Series HECI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_IDER,
+	    "500 Series IDE-R",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_KT,
+	    "500 Series KT",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_HECI_3,
+	    "500 Series HECI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_HECI_4,
+	    "500 Series HECI",
+	},
+	{
 	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_3,
 	    "500 Series I2C",
 	},
@@ -19840,6 +20024,30 @@ static const struct pci_known_product pci_known_products[] = {
 	    "500 Series I2C",
 	},
 	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_XHCI,
+	    "500 Series xHCI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_XDCI,
+	    "500 Series xDCI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SRAM,
+	    "500 Series Shared SRAM",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_3,
+	    "500 Series GSPI",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_ISH,
+	    "500 Series ISH",
+	},
+	{
+	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_GSPI_4,
+	    "500 Series GSPI",
+	},
+	{
 	    PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_AHCI_1,
 	    "100 Series AHCI",
 	},