diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2018-08-08 05:07:47 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2018-08-08 05:07:47 +0000 |
| commit | 9a78f3f40369e5ba28e96371c9c5f406ba245836 (patch) | |
| tree | 114b8b9839841574a34eaac0c958f497e93cbb5a /sys | |
| parent | 95cf33e4589b924bf45d1e2627a57c5e8c1769e3 (diff) | |
Recognise 'Speculative Store Bypass Disable' support cpuid bit.
Documented in 'Speculative Execution Side Channel Mitigations'
revision 2.0.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/amd64/amd64/identcpu.c | 3 | ||||
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 3 | ||||
| -rw-r--r-- | sys/arch/i386/include/specialreg.h | 3 |
3 files changed, 6 insertions, 3 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 4947ce0a79c..23610e396a8 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.104 2018/08/01 20:33:53 brynet Exp $ */ +/* $OpenBSD: identcpu.c,v 1.105 2018/08/08 05:07:46 jsg Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -210,6 +210,7 @@ const struct { { SEFF0EDX_IBRS, "IBRS,IBPB" }, { SEFF0EDX_STIBP, "STIBP" }, /* SEFF0EDX_ARCH_CAP (not printed) */ + { SEFF0EDX_SSBD, "SSBD" }, }, cpu_tpm_eaxfeatures[] = { { TPM_SENSOR, "SENSOR" }, { TPM_ARAT, "ARAT" }, diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 1b32d30fd9c..37e9bee8f2a 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.76 2018/07/23 23:25:03 brynet Exp $ */ +/* $OpenBSD: specialreg.h,v 1.77 2018/08/08 05:07:46 jsg Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -220,6 +220,7 @@ #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ #define SEFF0EDX_ARCH_CAP 0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */ +#define SEFF0EDX_SSBD 0x80000000 /* Spec Store Bypass Disable */ /* * Thermal and Power Management (CPUID function 0x6) EAX bits diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index ad4668bbb4b..a4b1e7f6591 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.67 2018/07/24 17:31:23 brynet Exp $ */ +/* $OpenBSD: specialreg.h,v 1.68 2018/08/08 05:07:46 jsg Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -172,6 +172,7 @@ #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ #define SEFF0EDX_ARCH_CAP 0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */ +#define SEFF0EDX_SSBD 0x80000000 /* Spec Store Bypass Disable */ /* * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) |