Add edma driver. This driver add support for am335x edma3 controller.

With some more work, it will allow us to speed-up ommmc driver.

ok patrick@.

10 files changed, 520 insertions, 9 deletions

diff --git a/sys/arch/armv7/omap/am335x.c b/sys/arch/armv7/omap/am335x.c
index 9ef70916a98..d3e39ef0880 100644
--- a/sys/arch/armv7/omap/am335x.c
+++ b/sys/arch/armv7/omap/am335x.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: am335x.c,v 1.2 2013/09/12 12:03:15 rapha Exp $ */
+/* $OpenBSD: am335x.c,v 1.3 2013/10/10 19:40:02 syl Exp $ */
 
 /*
  * Copyright (c) 2011 Uwe Stuehler <uwe@openbsd.org>
@@ -64,6 +64,15 @@
 #define GPIO2_IRQ	32
 #define GPIO3_IRQ	62
 
+#define TPCC_SIZE	0x100000
+#define TPCC_ADDR	0x49000000
+#define TPTC0_ADDR	0x49800000
+#define TPTC1_ADDR	0x49900000
+#define TPTC2_ADDR	0x49a00000
+#define EDMACOMP_IRQ	12
+#define EDMAMPERR_IRQ	13
+#define EDMAERR_IRQ	14
+
 #define UARTx_SIZE	0x90
 #define UART0_ADDR	0x44E09000
 #define UART1_ADDR	0x48022000
@@ -76,7 +85,7 @@
 #define UART2_IRQ	74
 #define UART3_IRQ	44
 #define UART4_IRQ	45
-#define UART5_IRQ	46	
+#define UART5_IRQ	46
 
 #define HSMMCx_SIZE	0x300
 #define HSMMC0_ADDR	0x48060000
@@ -118,6 +127,15 @@ struct omap_dev am335x_devs[] = {
 	},
 
 	/*
+	 * EDMA Controller
+	 */
+	{ .name = "edma",
+	  .unit = 0,
+	  .mem = { { TPCC_ADDR, TPCC_SIZE } },
+	  .irq = { EDMACOMP_IRQ }
+	},
+
+	/*
 	 * General Purpose Timers
 	 */
 
diff --git a/sys/arch/armv7/omap/am335x_prcmreg.h b/sys/arch/armv7/omap/am335x_prcmreg.h
index f7077423c15..49e34f7bd54 100644
--- a/sys/arch/armv7/omap/am335x_prcmreg.h
+++ b/sys/arch/armv7/omap/am335x_prcmreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: am335x_prcmreg.h,v 1.1 2013/09/04 14:38:30 patrick Exp $ */
+/* $OpenBSD: am335x_prcmreg.h,v 1.2 2013/10/10 19:40:02 syl Exp $ */
 /*
  * Copyright (c) 2013 Raphael Graf <r@undefined.ch>
  *
@@ -21,12 +21,16 @@
 
 #define PRCM_AM335X_CM_PER		0x0000
 #define PRCM_AM335X_USB0_CLKCTRL	0x001c
+#define PRCM_AM335X_TPTC0_CLKCTRL	0x0024
 #define PRCM_AM335X_MMC0_CLKCTRL	0x003c
 #define PRCM_AM335X_TIMER2_CLKCTRL	0x0080
 #define PRCM_AM335X_TIMER3_CLKCTRL	0x0084
 #define PRCM_AM335X_GPIO1_CLKCTRL	0x00ac
 #define PRCM_AM335X_GPIO2_CLKCTRL	0x00b0
 #define PRCM_AM335X_GPIO3_CLKCTRL	0x00b4
+#define PRCM_AM335X_TPCC_CLKCTRL	0x00bc
+#define PRCM_AM335X_TPTC1_CLKCTRL	0x00fc
+#define PRCM_AM335X_TPTC2_CLKCTRL	0x0100
 #define PRCM_AM335X_CM_WKUP		0x0400
 #define PRCM_AM335X_GPIO0_CLKCTRL	0x0408
 #define PRCM_AM335X_TIMER0_CLKCTRL	0x0410
diff --git a/sys/arch/armv7/omap/edma.c b/sys/arch/armv7/omap/edma.c
new file mode 100644
index 00000000000..534c2b52390
--- /dev/null
+++ b/sys/arch/armv7/omap/edma.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2013 Sylvestre Gallon <ccna.syl@gmail.com>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <machine/bus.h>
+
+#include <armv7/omap/omapvar.h>
+#include <armv7/omap/prcmvar.h>
+#include <armv7/omap/edmareg.h>
+#include <armv7/omap/edmavar.h>
+
+#define DEVNAME(s)		((s)->sc_dev.dv_xname)
+
+struct edma_softc *edma_sc;
+
+void	edma_attach(struct device *, struct device *, void *);
+int	edma_comp_intr(void *);
+
+struct cfattach edma_ca = {
+	sizeof(struct edma_softc), NULL, edma_attach
+};
+
+struct cfdriver edma_cd = {
+	NULL, "edma", DV_DULL
+};
+
+void
+edma_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct omap_attach_args *oaa = aux;
+	struct edma_softc *sc = (struct edma_softc *)self;
+	uint32_t rev;
+	int i;
+
+	sc->sc_iot = oaa->oa_iot;
+
+	/* Map Base address for TPCC and TPCTX */
+	if (bus_space_map(sc->sc_iot, oaa->oa_dev->mem[0].addr,
+	    oaa->oa_dev->mem[0].size, 0, &sc->sc_tpcc)) {
+		printf("%s: bus_space_map failed for TPCC\n", DEVNAME(sc));
+		return ;
+	}
+
+	/* Enable TPCC and TPTC0 in PRCM */
+	prcm_enablemodule(PRCM_TPCC);
+	prcm_enablemodule(PRCM_TPTC0);
+
+	rev = TPCC_READ_4(sc, EDMA_TPCC_PID);
+	printf(" rev %d.%d\n", rev >> 4 & 0xf, rev & 0xf);
+
+	/* XXX IPL_VM ? */
+	/* Enable interrupts line */
+	sc->sc_ih_comp = arm_intr_establish(oaa->oa_dev->irq[0], IPL_VM,
+	    edma_comp_intr, sc, DEVNAME(sc));
+	if (sc->sc_ih_comp == NULL) {
+		printf("%s: unable to establish interrupt comp\n", DEVNAME(sc));
+		bus_space_unmap(sc->sc_iot, sc->sc_tpcc,
+		    oaa->oa_dev->mem[0].size);
+		return ;
+	}
+
+	/* Set global softc */
+	edma_sc = sc;
+
+	/* Clear Event Missed Events */
+	TPCC_WRITE_4(sc, EDMA_TPCC_EMCR, 0xffffffff);
+	TPCC_WRITE_4(sc, EDMA_TPCC_EMCRH, 0xffffffff);
+	TPCC_WRITE_4(sc, EDMA_TPCC_CCERRCLR, 0xffffffff);
+
+	/* Identity Map Channels PaRAM */
+	for (i = 0; i < EDMA_NUM_DMA_CHANS; i++)
+		TPCC_WRITE_4(sc, EDMA_TPCC_DHCM(i), i << 5);
+
+	/*
+	 * Enable SHADOW Region 0 and only use this region
+	 * This is needed to have working intr...
+	 */
+	TPCC_WRITE_4(sc, EDMA_TPCC_DRAE0, 0xffffffff);
+	TPCC_WRITE_4(sc, EDMA_TPCC_DRAEH0, 0xffffffff);
+
+	return ;
+}
+
+int
+edma_comp_intr(void *arg)
+{
+	struct edma_softc *sc = arg;
+	uint32_t ipr, iprh;
+	int i;
+
+	ipr = TPCC_READ_4(sc, EDMA_TPCC_IPR);
+	iprh = TPCC_READ_4(sc, EDMA_TPCC_IPRH);
+
+	/* Lookup to intr in the first 32 chans */
+	for (i = 0; i < (EDMA_NUM_DMA_CHANS/2); i++) {
+		if (ISSET(ipr, (1<<i))) {
+			TPCC_WRITE_4(sc, EDMA_TPCC_ICR, (1<<i));
+			if (sc->sc_intr_cb[i])
+				sc->sc_intr_cb[i](sc->sc_intr_dat[i]);
+		}
+	}
+
+	for (i = 0; i < (EDMA_NUM_DMA_CHANS/2); i++) {
+		if (ISSET(iprh, (1<<i))) {
+			TPCC_WRITE_4(sc, EDMA_TPCC_ICRH, (1<<i));
+			if (sc->sc_intr_cb[i + 32])
+				sc->sc_intr_cb[i + 32](sc->sc_intr_dat[i + 32]);
+		}
+	}
+
+	/* Trig pending intr */
+	TPCC_WRITE_4(sc, EDMA_TPCC_IEVAL, 1);
+
+	return (1);
+}
+
+int
+edma_intr_dma_en(uint32_t ch, edma_intr_cb_t cb, void *dat)
+{
+	if (edma_sc == NULL || ch >= EDMA_NUM_DMA_CHANS)
+		return (EINVAL);
+
+	edma_sc->sc_intr_cb[ch] = cb;
+	edma_sc->sc_intr_dat[ch] = dat;
+
+	if (ch < 32) {
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_IESR, 1 << ch);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_IESR + EDMA_REG_X(0), 1 << ch);
+	} else {
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_IESRH, 1 << (ch - 32));
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_IESRH + EDMA_REG_X(0),
+		    1 << (ch - 32));
+	}
+
+	return (0);
+}
+
+int
+edma_intr_dma_dis(uint32_t ch)
+{
+	if (edma_sc == NULL || ch >= EDMA_NUM_DMA_CHANS)
+		return (EINVAL);
+
+	if (ch < 32)
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_IECR, 1 << ch);
+	else
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_IECRH, 1 << (ch - 32));
+	edma_sc->sc_intr_cb[ch] = NULL;
+	edma_sc->sc_intr_dat[ch] = NULL;
+
+	return (0);
+}
+
+int
+edma_trig_xfer_man(uint32_t ch)
+{
+	if (edma_sc == NULL || ch >= EDMA_NUM_DMA_CHANS)
+		return (EINVAL);
+
+	/*
+	 * Trig xfer
+	 * enable IEVAL only if there is an intr associated
+	 */
+	if (ch < 32) {
+		if (ISSET(TPCC_READ_4(edma_sc, EDMA_TPCC_IER), 1 << ch))
+			TPCC_WRITE_4(edma_sc, EDMA_TPCC_IEVAL, 1);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_ICR, 1 << ch);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_EMCR, 1 << ch);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_ESR, 1 << ch);
+	} else {
+		if (ISSET(TPCC_READ_4(edma_sc, EDMA_TPCC_IERH), 1 << (ch - 32)))
+			TPCC_WRITE_4(edma_sc, EDMA_TPCC_IEVAL, 1);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_ICRH, 1 << (ch - 32));
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_EMCRH, 1 << (ch - 32));
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_ESRH, 1 << (ch - 32));
+	}
+
+	return (0);
+}
+
+int
+edma_trig_xfer_by_dev(uint32_t ch)
+{
+	if (edma_sc == NULL || ch >= EDMA_NUM_DMA_CHANS)
+		return (EINVAL);
+
+	if (ch < 32) {
+		if (ISSET(TPCC_READ_4(edma_sc, EDMA_TPCC_IER), 1 << ch))
+			TPCC_WRITE_4(edma_sc, EDMA_TPCC_IEVAL, 1);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_ICR, 1 << ch);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_SECR, 1 << ch);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_EMCR, 1 << ch);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_EESR, 1 << ch);
+	} else {
+		if (ISSET(TPCC_READ_4(edma_sc, EDMA_TPCC_IERH), 1 << (ch - 32)))
+			TPCC_WRITE_4(edma_sc, EDMA_TPCC_IEVAL, 1);
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_ICRH, 1 << (ch - 32));
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_SECRH, 1 << (ch - 32));
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_EMCRH, 1 << (ch - 32));
+		TPCC_WRITE_4(edma_sc, EDMA_TPCC_EESRH, 1 << (ch - 32));
+	}
+	return (0);
+}
+
+void
+edma_param_write(uint32_t ch, struct edma_param *params)
+{
+	bus_space_write_region_4(edma_sc->sc_iot, edma_sc->sc_tpcc,
+	    EDMA_TPCC_OPT(ch), (uint32_t *)params, 8);
+}
+
+void
+edma_param_read(uint32_t ch, struct edma_param *params)
+{
+	bus_space_read_region_4(edma_sc->sc_iot, edma_sc->sc_tpcc,
+	    EDMA_TPCC_OPT(ch), (uint32_t *)params, 8);
+}
+
diff --git a/sys/arch/armv7/omap/edmareg.h b/sys/arch/armv7/omap/edmareg.h
new file mode 100644
index 00000000000..df9f1979a5f
--- /dev/null
+++ b/sys/arch/armv7/omap/edmareg.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2013 Sylvestre Gallon <ccna.syl@gmail.com>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMAREG_H__
+#define __EDMAREG_H__
+
+/*
+ * TPCC Registers
+ */
+
+#define EDMA_NUM_DMA_CHANS	64
+#define EDMA_NUM_QDMA_CHANS	8
+#define EDMA_REG_X(x)		(0x1000 + (0x200 * x))
+
+#define EDMA_TPCC_PID		0x0
+#define EDMA_TPCC_CCCFG		0x4
+#define EDMA_TPCC_SYSCFG	0x10
+#define EDMA_TPCC_DHCM(x)	(0x100 + (x * 4))
+#define EDMA_TPCC_QCHM(x)	(0x200 + (x * 4))
+#define EDMA_TPCC_DMAQNUM(x)	(0x240 + (x * 4))
+# define DMAQNUM_SET(c, q)	((0x7 & (q)) << (((c) % 8) * 4))
+# define DMAQNUM_CLR(c)		(~(0x7 << (((c) % 8) * 4)))
+#define EDMA_TPCC_QDMAQNUM	0x260
+# define QDMAQNUM_SET(c,q)	((0x7 & (q)) << ((c) * 4))
+# define QDMAQNUM_CLR(c)	(~(0x7 << ((c) * 4)))
+#define EDMA_TPCC_QUEPRI	0x284
+#define EDMA_TPCC_EMR		0x300
+#define EDMA_TPCC_EMRH		0x304
+#define EDMA_TPCC_EMCR		0x308
+#define EDMA_TPCC_EMCRH		0x30c
+#define EDMA_TPCC_QEMR		0x310
+#define EDMA_TPCC_QEMCR		0x314
+#define EDMA_TPCC_CCERR		0x318
+#define EDMA_TPCC_CCERRCLR	0x31c
+#define EDMA_TPCC_EEVAL		0x320
+#define EDMA_TPCC_DRAE0		0x340
+#define EDMA_TPCC_DRAEH0	0x344
+#define EDMA_TPCC_DRAE1		0x348
+#define EDMA_TPCC_DRAEH1	0x34c
+#define EDMA_TPCC_DRAE2		0x350
+#define EDMA_TPCC_DRAEH2	0x354
+#define EDMA_TPCC_DRAE3		0x358
+#define EDMA_TPCC_DRAEH3	0x35c
+#define EDMA_TPCC_DRAE4		0x360
+#define EDMA_TPCC_DRAEH4	0x364
+#define EDMA_TPCC_DRAE5		0x368
+#define EDMA_TPCC_DRAEH5	0x36c
+#define EDMA_TPCC_DRAE6		0x370
+#define EDMA_TPCC_DRAEH6	0x374
+#define EDMA_TPCC_DRAE7		0x378
+#define EDMA_TPCC_DRAEH7	0x37c
+#define EDMA_TPCC_QRAE(x)	(0x380 + (x * 4))
+#define EDMA_TPCC_QXEY(x,y)	(0x400 + (x * 0x40) + (y * 4))
+#define EDMA_TPCC_QSTAT(x)	(0x600 + (x * 4))
+#define EDMA_TPCC_QWAMTHRA	0x620
+#define EDMA_TPCC_CCSTAT	0x640
+#define EDMA_TPCC_MPFAR		0x800
+#define EDMA_TPCC_MPFSR		0x804
+#define EDMA_TPCC_MPFCR		0x808
+#define EDMA_TPCC_MPPAG		0x80c
+#define EDMA_TPCC_MPPA(x)	(0x810 + (x * 4))
+#define EDMA_TPCC_ER		0x1000
+#define EDMA_TPCC_ERH		0x1004
+#define EDMA_TPCC_ECR		0x1008
+#define EDMA_TPCC_ECRH		0x100c
+#define EDMA_TPCC_ESR		0x1010
+#define EDMA_TPCC_ESRH		0x1014
+#define EDMA_TPCC_CER		0x1018
+#define EDMA_TPCC_CERH		0x101c
+#define EDMA_TPCC_EER		0x1020
+#define EDMA_TPCC_EERH		0x1024
+#define EDMA_TPCC_EECR		0x1028
+#define EDMA_TPCC_EECRH		0x102c
+#define EDMA_TPCC_EESR		0x1030
+#define EDMA_TPCC_EESRH		0x1034
+#define EDMA_TPCC_SER		0x1038
+#define EDMA_TPCC_SERH		0x103c
+#define EDMA_TPCC_SECR		0x1040
+#define EDMA_TPCC_SECRH		0x1044
+#define EDMA_TPCC_IER		0x1050
+#define EDMA_TPCC_IERH		0x1054
+#define EDMA_TPCC_IECR		0x1058
+#define EDMA_TPCC_IECRH		0x105c
+#define EDMA_TPCC_IESR		0x1060
+#define EDMA_TPCC_IESRH		0x1064
+#define EDMA_TPCC_IPR		0x1068
+#define EDMA_TPCC_IPRH		0x106c
+#define EDMA_TPCC_ICR		0x1070
+#define EDMA_TPCC_ICRH		0x1074
+#define EDMA_TPCC_IEVAL		0x1078
+#define EDMA_TPCC_QER		0x1080
+#define EDMA_TPCC_QEER		0x1084
+#define EDMA_TPCC_QEECR		0x1088
+#define EDMA_TPCC_QEESR		0x108c
+#define EDMA_TPCC_QSER		0x1090
+#define EDMA_TPCC_QSECR		0x1094
+#define EDMA_TPCC_OPT(x)	(0x4000 + (x * 0x20))
+
+#define TPCC_READ_4(sc, reg)						\
+	(bus_space_read_4((sc)->sc_iot, (sc)->sc_tpcc, (reg)))
+#define TPCC_WRITE_4(sc, reg, val)					\
+	(bus_space_write_4((sc)->sc_iot, (sc)->sc_tpcc, (reg), (val)))
+#define TPCC_SET(sc, reg, val)						\
+	(TPCC_WRITE_4((sc), (reg), (TPCC_READ_4(sc, reg) | (val))))
+#define TPCC_FILTSET(sc, reg, val, filt)				\
+	(TPCC_WRITE_4((sc), (reg), (TPCC_READ_4(sc, reg) & (filt)) | (val)))
+
+/*
+ * TPTC Registers
+ */
+
+#define EDMA_TPTC_PID		0x0
+#define EDMA_TPTC_TCCFG		0x4
+#define EDMA_TPTC_SYSCFG	0x10
+#define EDMA_TPTC_TCSTAT	0x100
+#define EDMA_TPTC_ERRSTAT	0x120
+#define EDMA_TPTC_ERREN		0x124
+#define EDMA_TPTC_ERRCLR	0x128
+#define EDMA_TPTC_ERRDET	0x12c
+#define EDMA_TPTC_ERRCMD	0x130
+#define EDMA_TPTC_RDRATE	0x140
+#define EDMA_TPTC_SAOPT		0x240
+#define EDMA_TPTC_SASRC		0x244
+#define EDMA_TPTC_SACNT		0x248
+#define EDMA_TPTC_SADST		0x24c
+#define EDMA_TPTC_SABIDX	0x250
+#define EDMA_TPTC_SAMPPRXY	0x254
+#define EDMA_TPTC_SACNTRLD	0x258
+#define EDMA_TPTC_SASRCBREF	0x25c
+#define EDMA_TPTC_SADSTBREF	0x260
+#define EDMA_TPTC_DFCNTRLD	0x280
+#define EDMA_TPTC_DFSRCBREF	0x284
+#define EDMA_TPTC_DFDSTBREF	0x288
+#define EDMA_TPTC_DFOPT0	0x300
+#define EDMA_TPTC_DFSRC0	0x304
+#define EDMA_TPTC_DFCNT0	0x308
+#define EDMA_TPTC_DFDST0	0x30c
+#define EDMA_TPTC_DFBIDX0	0x310
+#define EDMA_TPTC_DFMPPRXY0	0x314
+#define EDMA_TPTC_DFOPT1	0x340
+#define EDMA_TPTC_DFSRC1	0x344
+#define EDMA_TPTC_DFCNT1	0x348
+#define EDMA_TPTC_DFDST1	0x34c
+#define EDMA_TPTC_DFBIDX1	0x350
+#define EDMA_TPTC_DFMPPRXY1	0x354
+#define EDMA_TPTC_DFOPT2	0x380
+#define EDMA_TPTC_DFSRC2	0x384
+#define EDMA_TPTC_DFCNT2	0x388
+#define EDMA_TPTC_DFDST2	0x38c
+#define EDMA_TPTC_DFBIDX2	0x390
+#define EDMA_TPTC_DFMPPRXY2	0x394
+#define EDMA_TPTC_DFOPT3	0x3c0
+#define EDMA_TPTC_DFSRC3	0x3c4
+#define EDMA_TPTC_DFCNT3	0x3c8
+#define EDMA_TPTC_DFDST3	0x3cc
+#define EDMA_TPTC_DFBIDX3	0x3d0
+#define EDMA_TPTC_DFMPPRXY3	0x3d4
+
+#define TPTC_READ_4(sc, i, reg)						\
+	(bus_space_read_4((sc)->sc_iot, (sc)->sc_tptc ## i, (reg)))
+#define TPTC_WRITE_4(sc, i, reg, val)					\
+	(bus_space_write_4((sc)->sc_iot, (sc)->sc_tptc ## i, (reg), (val)))
+
+#endif /* __EDMAREG_H__ */
diff --git a/sys/arch/armv7/omap/edmavar.h b/sys/arch/armv7/omap/edmavar.h
new file mode 100644
index 00000000000..ea1a6664b3d
--- /dev/null
+++ b/sys/arch/armv7/omap/edmavar.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2013 Sylvestre Gallon <ccna.syl@gmail.com>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMAVAR_H__
+#define __EDMAVAR_H__
+
+typedef	void (*edma_intr_cb_t)(void *);
+
+struct edma_softc {
+	struct device		sc_dev;
+
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_tpcc;
+
+	void			*sc_ih_comp;
+	edma_intr_cb_t		sc_intr_cb[64];
+	void			*sc_intr_dat[64];
+};
+
+/*
+ *	EDMA PaRAM dma descriptors
+ */
+struct edma_param{
+	uint32_t		opt;		/* Option */
+	uint32_t		src;		/* Ch source */
+	uint16_t		acnt;		/* 1st dim count */
+	uint16_t		bcnt;		/* 2nd dim count */
+	uint32_t		dst;		/* Chan dst addr */
+	int16_t			srcbidx;	/* Src b index */
+	int16_t			dstbidx;	/* Dst b index */
+	uint16_t		link;		/* Link addr */
+	uint16_t		bcntrld;	/* BCNT reload */
+	int16_t			srccidx;	/* Source C index */
+	int16_t			dstcidx;	/* Dest C index */
+	uint16_t		ccnt;		/* 3rd dim count */
+	uint16_t		res;		/* Reserved */
+} __attribute__((__packed__));
+
+int	edma_intr_dma_en(uint32_t, edma_intr_cb_t, void *); /* en it for chan */
+int	edma_intr_dma_dis(uint32_t);		    /* disable intr for chan */
+int	edma_trig_xfer_man(uint32_t);		    /* trig a dma xfer */
+int	edma_trig_xfer_by_dev(uint32_t);	    /* dma xfer trig by dev */
+void	edma_param_write(uint32_t, struct edma_param *);
+void	edma_param_read(uint32_t, struct edma_param *);
+
+#endif /* __EDMAVAR_H__ */
diff --git a/sys/arch/armv7/omap/files.omap b/sys/arch/armv7/omap/files.omap
index 24348cd2a21..b0f198c2b59 100644
--- a/sys/arch/armv7/omap/files.omap
+++ b/sys/arch/armv7/omap/files.omap
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.omap,v 1.1 2013/09/05 11:48:43 patrick Exp $
+#	$OpenBSD: files.omap,v 1.2 2013/10/10 19:40:02 syl Exp $
 
 define omap {}
 device omap: omap
@@ -28,7 +28,11 @@ file	arch/armv7/omap/sitara_cm.c		sitaracm
 
 device omgpio
 attach omgpio at omap
-file   arch/armv7/omap/omgpio.c			omgpio
+file	arch/armv7/omap/omgpio.c		omgpio
+
+device edma
+attach edma at omap
+file	arch/armv7/omap/edma.c			edma
 
 device intc
 attach intc at omap
diff --git a/sys/arch/armv7/omap/omap.c b/sys/arch/armv7/omap/omap.c
index 5781386b8ad..d92b0ada21d 100644
--- a/sys/arch/armv7/omap/omap.c
+++ b/sys/arch/armv7/omap/omap.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: omap.c,v 1.2 2013/09/12 12:03:15 rapha Exp $ */
+/* $OpenBSD: omap.c,v 1.3 2013/10/10 19:40:02 syl Exp $ */
 /*
  * Copyright (c) 2005,2008 Dale Rahn <drahn@openbsd.com>
  *
@@ -70,6 +70,7 @@ struct board_dev beaglebone_devs[] = {
 	{ "prcm",	0 },
 	{ "sitaracm",	0 },
 	{ "intc",	0 },
+	{ "edma",	0 },
 	{ "dmtimer",	0 },
 	{ "dmtimer",	1 },
 	{ "omdog",	0 },
diff --git a/sys/arch/armv7/omap/omapvar.h b/sys/arch/armv7/omap/omapvar.h
index b2a2e565f5e..5c891ac23a7 100644
--- a/sys/arch/armv7/omap/omapvar.h
+++ b/sys/arch/armv7/omap/omapvar.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: omapvar.h,v 1.1 2013/09/04 14:38:31 patrick Exp $ */
+/* $OpenBSD: omapvar.h,v 1.2 2013/10/10 19:40:02 syl Exp $ */
 /*
  * Copyright (c) 2005,2008 Dale Rahn <drahn@drahn.com>
  *
@@ -23,6 +23,7 @@ struct omap_mem {
 
 #define OMAP_DEV_NMEM 4		       /* number of memory ranges */
 #define OMAP_DEV_NIRQ 4		       /* number of IRQs per device */
+#define OMAP_DEV_NDMA 4		       /* number of DMA channels per device */
 
 /* Descriptor for all on-chip devices. */
 struct omap_dev {
@@ -30,6 +31,7 @@ struct omap_dev {
 	int unit;			/* driver instance number or -1 */
 	struct omap_mem mem[OMAP_DEV_NMEM]; /* memory ranges */
 	int irq[OMAP_DEV_NIRQ];		    /* IRQ number(s) */
+	int dma[OMAP_DEV_NDMA];		/* DMA chan number(s) */
 };
 
 /* Passed as third arg to attach functions. */
diff --git a/sys/arch/armv7/omap/prcm.c b/sys/arch/armv7/omap/prcm.c
index 9aa8abcafbd..05adeb69f39 100644
--- a/sys/arch/armv7/omap/prcm.c
+++ b/sys/arch/armv7/omap/prcm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: prcm.c,v 1.2 2013/09/11 23:08:29 dlg Exp $ */
+/* $OpenBSD: prcm.c,v 1.3 2013/10/10 19:40:02 syl Exp $ */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  *
@@ -273,6 +273,14 @@ prcm_am335x_clkctrl(int mod)
 		return PRCM_AM335X_MMC0_CLKCTRL;
 	case PRCM_USB:
 		return PRCM_AM335X_USB0_CLKCTRL;
+	case PRCM_TPCC:
+		return PRCM_AM335X_TPCC_CLKCTRL;
+	case PRCM_TPTC0:
+		return PRCM_AM335X_TPTC0_CLKCTRL;
+	case PRCM_TPTC1:
+		return PRCM_AM335X_TPTC1_CLKCTRL;
+	case PRCM_TPTC2:
+		return PRCM_AM335X_TPTC2_CLKCTRL;
 	default:
 		panic("%s: module not found\n", __func__);
 	}
diff --git a/sys/arch/armv7/omap/prcmvar.h b/sys/arch/armv7/omap/prcmvar.h
index c3070b4ac8e..50f4e995301 100644
--- a/sys/arch/armv7/omap/prcmvar.h
+++ b/sys/arch/armv7/omap/prcmvar.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: prcmvar.h,v 1.1 2013/09/04 14:38:32 patrick Exp $ */
+/* $OpenBSD: prcmvar.h,v 1.2 2013/10/10 19:40:03 syl Exp $ */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  *
@@ -27,6 +27,10 @@ enum PRCM_MODULES {
 	PRCM_TIMER1,
 	PRCM_TIMER2,
 	PRCM_TIMER3,
+	PRCM_TPCC,
+	PRCM_TPTC0,
+	PRCM_TPTC1,
+	PRCM_TPTC2,
 	PRCM_MMC,
 	PRCM_USB,
 	PRCM_USBTLL,