Fix IO clock speed and system reset on Octeon III.

3 files changed, 30 insertions, 6 deletions

diff --git a/sys/arch/octeon/include/octeon_model.h b/sys/arch/octeon/include/octeon_model.h
index f7a8e16860c..1ba3c76a602 100644
--- a/sys/arch/octeon/include/octeon_model.h
+++ b/sys/arch/octeon/include/octeon_model.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octeon_model.h,v 1.4 2016/07/16 10:41:53 visa Exp $	*/
+/*	$OpenBSD: octeon_model.h,v 1.5 2016/12/17 14:14:09 visa Exp $	*/
 
 /*
  * Copyright (c) 2007
@@ -53,6 +53,7 @@
 #define OCTEON_MODEL_FAMILY_CN30XX	0x000d0200
 #define OCTEON_MODEL_FAMILY_CN50XX	0x000d0600
 #define OCTEON_MODEL_FAMILY_CN61XX	0x000d9300
+#define OCTEON_MODEL_FAMILY_CN71XX	0x000d9600
 
 /*
  *  get chip id
diff --git a/sys/arch/octeon/include/octeonreg.h b/sys/arch/octeon/include/octeonreg.h
index 743b176a15c..a36ad4fb86c 100644
--- a/sys/arch/octeon/include/octeonreg.h
+++ b/sys/arch/octeon/include/octeonreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octeonreg.h,v 1.5 2015/07/20 19:44:32 pirofti Exp $	*/
+/*	$OpenBSD: octeonreg.h,v 1.6 2016/12/17 14:14:09 visa Exp $	*/
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com).
@@ -165,9 +165,17 @@
 #define CIU_INT0_EN4_1          0x00000C88
 #define CIU_INT1_EN4_1          0x00000C98
 
+/* OCTEON II */
 #define MIO_RST_BOOT		0x1180000001600ULL
 #define MIO_RST_BOOT_PNR_MUL_SHIFT	24
 #define MIO_RST_BOOT_PNR_MUL_MASK	0x3f
+
+/* OCTEON III */
+#define RST_BOOT		0x1180006001600ULL
+#define RST_BOOT_PNR_MUL_SHIFT		24
+#define RST_BOOT_PNR_MUL_MASK		0x3f
+#define RST_SOFT_RST		0x1180006001680ULL
+
 #define OCTEON_IO_REF_CLOCK	50000000	/* 50MHz */
 
 #endif /* !_MACHINE_OCTEONREG_H_ */
diff --git a/sys/arch/octeon/octeon/machdep.c b/sys/arch/octeon/octeon/machdep.c
index 0ecde24d617..530b53ce092 100644
--- a/sys/arch/octeon/octeon/machdep.c
+++ b/sys/arch/octeon/octeon/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.80 2016/12/17 11:17:56 visa Exp $ */
+/*	$OpenBSD: machdep.c,v 1.81 2016/12/17 14:14:09 visa Exp $ */
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -583,8 +583,8 @@ int
 octeon_ioclock_speed(void)
 {
 	extern struct boot_info *octeon_boot_info;
+	u_int64_t mio_rst_boot, rst_boot;
 	int chipid;
-	u_int64_t mio_rst_boot;
 
 	chipid = octeon_get_chipid();
 	switch (octeon_model_family(chipid)) {
@@ -592,7 +592,10 @@ octeon_ioclock_speed(void)
 		mio_rst_boot = octeon_xkphys_read_8(MIO_RST_BOOT);
 		return OCTEON_IO_REF_CLOCK * ((mio_rst_boot >>
 		    MIO_RST_BOOT_PNR_MUL_SHIFT) & MIO_RST_BOOT_PNR_MUL_MASK);
-		break;
+	case OCTEON_MODEL_FAMILY_CN71XX:
+		rst_boot = octeon_xkphys_read_8(RST_BOOT);
+		return OCTEON_IO_REF_CLOCK * ((rst_boot >>
+		    RST_BOOT_PNR_MUL_SHIFT) & RST_BOOT_PNR_MUL_MASK);
 	default:
 		return octeon_boot_info->eclock;
 	}
@@ -690,6 +693,8 @@ int	waittime = -1;
 __dead void
 boot(int howto)
 {
+	int chipid;
+
 	if (curproc)
 		savectx(curproc->p_addr, 0);
 
@@ -733,7 +738,17 @@ haltsys:
 		(void)disableintr();
 		tlb_set_wired(0);
 		tlb_flush(bootcpu_hwinfo.tlbsize);
-		octeon_xkphys_write_8(OCTEON_CIU_BASE + CIU_SOFT_RST, 1);
+
+		chipid = octeon_get_chipid();
+		switch (octeon_model_family(chipid)) {
+		case OCTEON_MODEL_FAMILY_CN71XX:
+			octeon_xkphys_write_8(RST_SOFT_RST, 1);
+			break;
+		default:
+			octeon_xkphys_write_8(OCTEON_CIU_BASE +
+			    CIU_SOFT_RST, 1);
+			break;
+		}
 	}
 
 	for (;;)