Add the missing ECX cpu flags from CPUID at 0x80000001.

This is all documented at:

http://support.amd.com/us/Embedded_TechDocs/25481.pdf (page 20)
http://www.intel.com/assets/pdf/appnote/241618.pdf (page 41)

ok jsg@

4 files changed, 57 insertions, 5 deletions

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index ad7bc7e5dad..c7b4d7c4562 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: identcpu.c,v 1.32 2011/05/29 14:50:25 deraadt Exp $	*/
+/*	$OpenBSD: identcpu.c,v 1.33 2011/12/26 23:07:04 haesbaert Exp $	*/
 /*	$NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $	*/
 
 /*
@@ -119,6 +119,25 @@ const struct {
 	{ CPUIDECX_XSAVE,	"XSAVE" },
 	{ CPUIDECX_OSXSAVE,	"OSXSAVE" },
 	{ CPUIDECX_AVX,		"AVX" }
+}, cpu_ecpuid_ecxfeatures[] = {
+	{ CPUIDECX_LAHF,	"LAHF" },
+	{ CPUIDECX_CMPLEG,	"CMPLEG" },
+	{ CPUIDECX_SVM,		"SVM" },
+	{ CPUIDECX_EAPICSP,	"EAPICSP"},
+	{ CPUIDECX_AMCR8,	"AMCR8"},
+	{ CPUIDECX_ABM,		"ABM" },
+	{ CPUIDECX_SSE4A,	"SSE4A" },
+	{ CPUIDECX_MASSE,	"MASSE" },
+	{ CPUIDECX_3DNOWP,	"3DNOWP" },
+	{ CPUIDECX_OSVW,	"OSVW" },
+	{ CPUIDECX_IBS,		"IBS" },
+	{ CPUIDECX_XOP,		"XOP" },
+	{ CPUIDECX_SKINIT,	"SKINIT" },
+	{ CPUIDECX_LWP,		"WDT" },
+	{ CPUIDECX_FMA4,	"FMA4" },
+	{ CPUIDECX_NODEID,	"NODEID" },
+	{ CPUIDECX_TBM,		"TBM" },
+	{ CPUIDECX_TOPEXT,	"TOPEXT" },
 };
 
 int
@@ -291,6 +310,8 @@ identifycpu(struct cpu_info *ci)
 	CPUID(1, ci->ci_signature, val, dummy, ci->ci_feature_flags);
 	CPUID(0x80000000, pnfeatset, dummy, dummy, dummy);
 	CPUID(0x80000001, dummy, dummy, dummy, ci->ci_feature_eflags);
+	if (pnfeatset >= 0x80000001)
+		CPUID(0x80000001, dummy, dummy, ecpu_ecxfeature, dummy);
 
 	vendor[3] = 0;
 	CPUID(0, dummy, vendor[0], vendor[2], vendor[1]);	/* yup, 0 2 1 */
@@ -352,6 +373,11 @@ identifycpu(struct cpu_info *ci)
 	for (i = 0; i < max; i++)
 		if (ci->ci_feature_eflags & cpu_ecpuid_features[i].bit)
 			printf(",%s", cpu_ecpuid_features[i].str);
+	max = sizeof(cpu_ecpuid_ecxfeatures) / sizeof(cpu_ecpuid_ecxfeatures[0]);
+	for (i = 0; i < max; i++)
+		if (ecpu_ecxfeature & cpu_ecpuid_ecxfeatures[i].bit)
+			printf(",%s", cpu_ecpuid_ecxfeatures[i].str);
+
 	printf("\n");
 
 	x86_print_cacheinfo(ci);
diff --git a/sys/arch/amd64/amd64/locore.S b/sys/arch/amd64/amd64/locore.S
index 5af0882f203..19e14d734ee 100644
--- a/sys/arch/amd64/amd64/locore.S
+++ b/sys/arch/amd64/amd64/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.50 2011/10/12 18:30:07 miod Exp $	*/
+/*	$OpenBSD: locore.S,v 1.51 2011/12/26 23:07:04 haesbaert Exp $	*/
 /*	$NetBSD: locore.S,v 1.13 2004/03/25 18:33:17 drochner Exp $	*/
 
 /*
@@ -169,7 +169,7 @@ _C_LABEL(lapic_isr):
 
 	.globl	_C_LABEL(cpu_id),_C_LABEL(cpu_vendor), _C_LABEL(cpu_brand_id)
 	.globl	_C_LABEL(cpuid_level),_C_LABEL(cpu_feature)
-	.globl	_C_LABEL(cpu_ecxfeature)
+	.globl	_C_LABEL(cpu_ecxfeature),_C_LABEL(ecpu_ecxfeature)
 	.globl	_C_LABEL(esym),_C_LABEL(boothowto),_C_LABEL(bootdev)
 	.globl	_C_LABEL(bootinfo), _C_LABEL(bootinfo_size), _C_LABEL(atdevbase)
 	.globl	_C_LABEL(proc0paddr),_C_LABEL(PTDpaddr)
@@ -181,6 +181,7 @@ _C_LABEL(cpu_id):	.long	0	# saved from `cpuid' instruction
 _C_LABEL(cpu_feature):	.long	0	# feature flags from 'cpuid'
 					#   instruction
 _C_LABEL(cpu_ecxfeature):.long	0	# extended feature flags from 'cpuid'
+_C_LABEL(ecpu_ecxfeature):.long	0	# extended ecx feature flags
 _C_LABEL(cpuid_level):	.long	-1	# max. level accepted by 'cpuid'
 					#   instruction
 _C_LABEL(cpu_vendor):	.space	16	# vendor string returned by `cpuid'
diff --git a/sys/arch/amd64/include/cpu.h b/sys/arch/amd64/include/cpu.h
index 5e839b6a39f..d9c0f1a0190 100644
--- a/sys/arch/amd64/include/cpu.h
+++ b/sys/arch/amd64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.69 2011/09/20 14:32:50 pirofti Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.70 2011/12/26 23:07:04 haesbaert Exp $	*/
 /*	$NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $	*/
 
 /*-
@@ -255,6 +255,7 @@ extern int biosextmem;
 extern int cpu;
 extern int cpu_feature;
 extern int cpu_ecxfeature;
+extern int ecpu_ecxfeature;
 extern int cpu_id;
 extern char cpu_vendor[];
 extern int cpuid_level;
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index 72c2db4e37e..3b5839fae74 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.19 2010/04/29 17:00:48 oga Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.20 2011/12/26 23:07:04 haesbaert Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -147,6 +147,30 @@
 #define CPUIDECX_OSXSAVE	0x08000000	/* OSXSAVE */
 #define CPUIDECX_AVX	0x10000000	/* Advanced Vector Extensions */
 
+#define CPUIDECX_LAHF		0x00000001 /* LAHF and SAHF instructions */
+#define CPUIDECX_CMPLEG		0x00000002 /* Core MP legacy mode */
+#define CPUIDECX_SVM		0x00000004 /* Secure Virtual Machine */
+#define CPUIDECX_EAPICSP	0x00000008 /* Extended APIC space */
+#define CPUIDECX_AMCR8		0x00000010 /* LOCK MOV CR0 means MOV CR8 */
+#define CPUIDECX_ABM		0x00000020 /* LZCNT instruction */
+#define CPUIDECX_SSE4A		0x00000040 /* SSE4-A instruction set */
+#define CPUIDECX_MASSE		0x00000080 /* Misaligned SSE mode */
+#define CPUIDECX_3DNOWP		0x00000100 /* 3DNowPrefetch */
+#define CPUIDECX_OSVW		0x00000200 /* OS visible workaround */
+#define CPUIDECX_IBS		0x00000400 /* Instruction based sampling */
+#define CPUIDECX_XOP		0x00000800 /* Extended operating support */
+#define CPUIDECX_SKINIT		0x00001000 /* SKINIT and STGI are supported */
+#define CPUIDECX_WDT		0x00002000 /* Watchdog timer */
+/* Reserved			0x00004000 */
+#define CPUIDECX_LWP		0x00008000 /* Lightweight profiling support */
+#define CPUIDECX_FMA4		0x00010000 /* 4-operand FMA instructions */
+/* Reserved			0x00020000 */
+/* Reserved			0x00040000 */
+#define CPUIDECX_NODEID		0x00080000 /* Support for MSRC001C */
+/* Reserved			0x00100000 */
+#define CPUIDECX_TBM		0x00200000 /* Trailing bit manipulation instruction */
+#define CPUIDECX_TOPEXT		0x00400000 /* Topology extensions support */
+
 /*
  * AMD/VIA processor specific flags.
  */