diff options
| author | Jasper Lievisse Adriaanse <jasper@cvs.openbsd.org> | 2013-10-27 12:58:54 +0000 |
|---|---|---|
| committer | Jasper Lievisse Adriaanse <jasper@cvs.openbsd.org> | 2013-10-27 12:58:54 +0000 |
| commit | e8227a9080380ea759f6cd0c08263e560feaa0e2 (patch) | |
| tree | eaa15fd54131c2e4d137b0008c87a12fa74d1775 /sys | |
| parent | 8ca395d4713666bd6faa4b4c546ef78d5c348fc5 (diff) | |
Fix timer on for A20 as the address and offsets for the A20 counter were off.
from Markus Hennecke, ok aalm@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/armv7/sunxi/sunxireg.h | 4 | ||||
| -rw-r--r-- | sys/arch/armv7/sunxi/sxitimer.c | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/sys/arch/armv7/sunxi/sunxireg.h b/sys/arch/armv7/sunxi/sunxireg.h index 24df6753f06..68a63bb275e 100644 --- a/sys/arch/armv7/sunxi/sunxireg.h +++ b/sys/arch/armv7/sunxi/sunxireg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: sunxireg.h,v 1.4 2013/10/24 11:09:02 jasper Exp $ */ +/* $OpenBSD: sunxireg.h,v 1.5 2013/10/27 12:58:53 jasper Exp $ */ /* * Copyright (c) 2013 Artturi Alm * @@ -114,5 +114,5 @@ #define GIC_SIZE 0x8000 #define CPUCONFG_ADDR 0x01c25c00 /* not in use */ #define CPUCONFG_SIZE 0x200 -#define CPUCNTRS_ADDR 0x01c25200 /* used by sxitimer */ +#define CPUCNTRS_ADDR 0x01c25e00 /* used by sxitimer */ #define CPUCNTRS_SIZE 0x200 diff --git a/sys/arch/armv7/sunxi/sxitimer.c b/sys/arch/armv7/sunxi/sxitimer.c index 8a9736472b8..bc744199a56 100644 --- a/sys/arch/armv7/sunxi/sxitimer.c +++ b/sys/arch/armv7/sunxi/sxitimer.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sxitimer.c,v 1.1 2013/10/23 17:08:48 jasper Exp $ */ +/* $OpenBSD: sxitimer.c,v 1.2 2013/10/27 12:58:53 jasper Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * Copyright (c) 2013 Raphael Graf <r@undefined.ch> @@ -44,10 +44,10 @@ #define TIMER_INTV(x) (0x14 + (0x10 * (x))) #define TIMER_CURR(x) (0x18 + (0x10 * (x))) -/* A20 counter */ -#define OSC24M_CNT64_CTRL 0x280 -#define OSC24M_CNT64_LOW 0x284 -#define OSC24M_CNT64_HIGH 0x288 +/* A20 counter, relative to CPUCNTRS_ADDR */ +#define OSC24M_CNT64_CTRL 0x80 +#define OSC24M_CNT64_LOW 0x84 +#define OSC24M_CNT64_HIGH 0x88 /* A1X counter */ #define CNT64_CTRL 0xa0 |