Remove MD intagp(4) code that is unused now that inteldrm(4) manages the GTT

all by itself.

4 files changed, 4 insertions, 263 deletions

diff --git a/sys/arch/amd64/pci/agp_machdep.c b/sys/arch/amd64/pci/agp_machdep.c
index 93dbaece57e..6d3abfa49e6 100644
--- a/sys/arch/amd64/pci/agp_machdep.c
+++ b/sys/arch/amd64/pci/agp_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: agp_machdep.c,v 1.8 2013/12/07 10:57:06 kettenis Exp $	*/
+/*	$OpenBSD: agp_machdep.c,v 1.9 2013/12/09 19:52:11 kettenis Exp $	*/
 
 /*
  * Copyright (c) 2008 - 2009 Owain G. Ainsworth <oga@openbsd.org>
@@ -56,15 +56,6 @@
 
 #include <uvm/uvm.h>
 
-#include "intagp.h"
-
-/* bus_dma functions */
-
-#if NINTAGP > 0
-void	intagp_dma_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
-	    bus_size_t, int);
-#endif
-
 void
 agp_flush_cache(void)
 {
@@ -129,122 +120,3 @@ agp_unmap_subregion(struct agp_map *map, bus_space_handle_t bsh,
 {
 	/* subregion doesn't need unmapping, do nothing */
 }
-
-/*
- * ick ick ick. However, the rest of this driver is supposedly MI (though
- * they only exist on x86), so this can't be in dev/pci.
- */
-
-#if NINTAGP > 0
-
-/*
- * bus_dmamap_sync routine for intagp.
- *
- * This is tailored to the usage that drm with the GEM memory manager
- * will be using, since intagp is for intel IGD, and thus shouldn't be
- * used for anything other than gpu-based work. Essentially for the intel GEM
- * driver we use bus_dma as an abstraction to convert our memory into a gtt
- * address and deal with any cache incoherencies that we create.
- *
- * We use the cflush instruction to deal with clearing the caches, since our
- * cache is physically indexed, we can even map then clear the page and it'll
- * work. on i386 we need to check for the presence of cflush() in cpuid,
- * however, all cpus that have a new enough intel GMCH should be suitable.
- */
-void	
-intagp_dma_sync(bus_dma_tag_t tag, bus_dmamap_t dmam,
-    bus_addr_t offset, bus_size_t size, int ops)
-{
-	bus_dma_segment_t	*segp;
-	struct sg_page_map	*spm;
-	void			*addr;
-	paddr_t	 		 pa;
-	bus_addr_t		 poff, endoff, soff;
-
-#ifdef DIAGNOSTIC
-	if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0 &&
-	    (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) != 0)
-		panic("agp_dmamap_sync: mix PRE and POST");
-	if (offset >= dmam->dm_mapsize)
-		panic("_intagp_dma_sync: bad offset %lu (size = %lu)",
-		    offset, dmam->dm_mapsize);
-	if (size == 0 || (offset + size) > dmam->dm_mapsize)
-		panic("intagp_dma_sync: bad length");
-#endif /* DIAGNOSTIC */
-	
-	/* Coherent mappings need no sync. */
-	if (dmam->_dm_flags & BUS_DMA_COHERENT)
-		return;
-
-	/*
-	 * We need to clflush the object cache in all cases but postwrite.
-	 *
-	 * - Due to gpu incoherency, postread we need to flush speculative
-	 * reads (which are not written back on intel cpus).
-	 *
-	 * - preread we need to flush data which will very soon be stale from
-	 * the caches
-	 *
-	 * - prewrite we need to make sure our data hits the memory before the 
-	 * gpu hoovers it up.
-	 *
-	 * The chipset also may need flushing, but that fits badly into
-	 * bus_dma and it done in the driver.
-	 */
-	soff = trunc_page(offset);
-	endoff = round_page(offset + size);
-	if (ops & BUS_DMASYNC_POSTREAD || ops & BUS_DMASYNC_PREREAD ||
-	    ops & BUS_DMASYNC_PREWRITE) {
-		if (curcpu()->ci_cflushsz == 0) {
-			/* save some wbinvd()s. we're MD anyway so it's ok */
-			wbinvd();
-			return;
-		}
-
-		mfence();
-		spm = dmam->_dm_cookie;
-		switch (spm->spm_buftype) {
-		case BUS_BUFTYPE_LINEAR:
-			addr = spm->spm_origbuf + soff;
-			while (soff < endoff) {
-				pmap_flush_cache((vaddr_t)addr, PAGE_SIZE);
-				soff += PAGE_SIZE;
-				addr += PAGE_SIZE;
-			} break;
-		case BUS_BUFTYPE_RAW:
-			segp = (bus_dma_segment_t *)spm->spm_origbuf;
-			poff = 0;
-
-			while (poff < soff) {
-				if (poff + segp->ds_len > soff)
-					break;
-				poff += segp->ds_len;
-				segp++;
-			}
-			/* first time round may not start at seg beginning */
-			pa = segp->ds_addr + (soff - poff);
-			while (poff < endoff) {
-				for (; pa < segp->ds_addr + segp->ds_len &&
-				    poff < endoff; pa += PAGE_SIZE) {
-					pmap_flush_page(pa);
-					poff += PAGE_SIZE;
-				}
-				segp++;
-				if (poff < endoff)
-					pa = segp->ds_addr;
-			}
-			break;
-		/* You do not want to load mbufs or uios onto a graphics card */
-		case BUS_BUFTYPE_MBUF:
-			/* FALLTHROUGH */
-		case BUS_BUFTYPE_UIO:
-			/* FALLTHROUGH */
-		default:
-			panic("intagp_dmamap_sync: bad buftype %d",
-			    spm->spm_buftype);
-			
-		}
-		mfence();
-	}
-}
-#endif /* NINTAGP > 0 */
diff --git a/sys/arch/i386/pci/agp_machdep.c b/sys/arch/i386/pci/agp_machdep.c
index ff33f36ea88..259d652627c 100644
--- a/sys/arch/i386/pci/agp_machdep.c
+++ b/sys/arch/i386/pci/agp_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: agp_machdep.c,v 1.14 2013/12/07 10:57:06 kettenis Exp $	*/
+/*	$OpenBSD: agp_machdep.c,v 1.15 2013/12/09 19:52:11 kettenis Exp $	*/
 
 /*
  * Copyright (c) 2008 - 2009 Owain G. Ainsworth <oga@openbsd.org>
@@ -56,15 +56,6 @@
 
 #include <uvm/uvm.h>
 
-#include "intagp.h"
-
-/* bus_dma functions */
-
-#if NINTAGP > 0
-void	intagp_dma_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
-	    bus_size_t, int);
-#endif
-
 void
 agp_flush_cache(void)
 {
@@ -170,122 +161,3 @@ agp_unmap_subregion(struct agp_map *map, bus_space_handle_t bsh,
 {
 	return (_bus_space_unmap(map->bst, bsh, size, NULL));
 }
-
-/*
- * ick ick ick. However, the rest of this driver is supposedly MI (though
- * they only exist on x86), so this can't be in dev/pci.
- */
-
-#if NINTAGP > 0
-
-/*
- * bus_dmamap_sync routine for intagp.
- *
- * This is tailored to the usage that drm with the GEM memory manager
- * will be using, since intagp is for intel IGD, and thus shouldn't be
- * used for anything other than gpu-based work. Essentially for the intel GEM
- * driver we use bus_dma as an abstraction to convert our memory into a gtt
- * address and deal with any cache incoherencies that we create.
- *
- * We use the cflush instruction to deal with clearing the caches, since our
- * cache is physically indexed, we can even map then clear the page and it'll
- * work. on i386 we need to check for the presence of cflush() in cpuid,
- * however, all cpus that have a new enough intel GMCH should be suitable.
- */
-void	
-intagp_dma_sync(bus_dma_tag_t tag, bus_dmamap_t dmam,
-    bus_addr_t offset, bus_size_t size, int ops)
-{
-	bus_dma_segment_t	*segp;
-	struct sg_page_map	*spm;
-	void			*addr;
-	paddr_t	 		 pa;
-	bus_addr_t		 poff, endoff, soff;
-
-#ifdef DIAGNOSTIC
-	if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0 &&
-	    (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) != 0)
-		panic("agp_dmamap_sync: mix PRE and POST");
-	if (offset >= dmam->dm_mapsize)
-		panic("_intagp_dma_sync: bad offset %lu (size = %lu)",
-		    offset, dmam->dm_mapsize);
-	if (size == 0 || (offset + size) > dmam->dm_mapsize)
-		panic("intagp_dma_sync: bad length");
-#endif /* DIAGNOSTIC */
-	
-	/* Coherent mappings need no sync. */
-	if (dmam->_dm_flags & BUS_DMA_COHERENT)
-		return;
-
-	/*
-	 * We need to clflush the object cache in all cases but postwrite.
-	 *
-	 * - Due to gpu incoherency, postread we need to flush speculative
-	 * reads (which are not written back on intel cpus).
-	 *
-	 * - preread we need to flush data which will very soon be stale from
-	 * the caches
-	 *
-	 * - prewrite we need to make sure our data hits the memory before the 
-	 * gpu hoovers it up.
-	 *
-	 * The chipset also may need flushing, but that fits badly into
-	 * bus_dma and it done in the driver.
-	 */
-	soff = trunc_page(offset);
-	endoff = round_page(offset + size);
-	if (ops & BUS_DMASYNC_POSTREAD || ops & BUS_DMASYNC_PREREAD ||
-	    ops & BUS_DMASYNC_PREWRITE) {
-		if (curcpu()->ci_cflushsz == 0) {
-			/* save some wbinvd()s. we're MD anyway so it's ok */
-			wbinvd();
-			return;
-		}
-
-		mfence();
-		spm = dmam->_dm_cookie;
-		switch (spm->spm_buftype) {
-		case BUS_BUFTYPE_LINEAR:
-			addr = spm->spm_origbuf + soff;
-			while (soff < endoff) {
-				pmap_flush_cache((vaddr_t)addr, PAGE_SIZE);
-				soff += PAGE_SIZE;
-				addr += PAGE_SIZE;
-			} break;
-		case BUS_BUFTYPE_RAW:
-			segp = (bus_dma_segment_t *)spm->spm_origbuf;
-			poff = 0;
-
-			while (poff < soff) {
-				if (poff + segp->ds_len > soff)
-					break;
-				poff += segp->ds_len;
-				segp++;
-			}
-			/* first time round may not start at seg beginning */
-			pa = segp->ds_addr + (soff - poff);
-			while (poff < endoff) {
-				for (; pa < segp->ds_addr + segp->ds_len &&
-				    poff < endoff; pa += PAGE_SIZE) {
-					pmap_flush_page(pa);
-					poff += PAGE_SIZE;
-				}
-				segp++;
-				if (poff < endoff)
-					pa = segp->ds_addr;
-			}
-			break;
-		/* You do not want to load mbufs or uios onto a graphics card */
-		case BUS_BUFTYPE_MBUF:
-			/* FALLTHROUGH */
-		case BUS_BUFTYPE_UIO:
-			/* FALLTHROUGH */
-		default:
-			panic("intagp_dmamap_sync: bad buftype %d",
-			    spm->spm_buftype);
-			
-		}
-		mfence();
-	}
-}
-#endif /* NINTAGP > 0 */
diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c
index f055a357ab6..abcdb2f3e17 100644
--- a/sys/dev/pci/agp_i810.c
+++ b/sys/dev/pci/agp_i810.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: agp_i810.c,v 1.79 2013/11/19 19:14:09 kettenis Exp $	*/
+/*	$OpenBSD: agp_i810.c,v 1.80 2013/12/09 19:52:11 kettenis Exp $	*/
 
 /*-
  * Copyright (c) 2000 Doug Rabson
@@ -129,7 +129,6 @@ struct agp_methods agp_i810_methods = {
 	agp_i810_bind_page,
 	agp_i810_unbind_page,
 	agp_i810_flush_tlb,
-	intagp_dma_sync,
 	agp_i810_enable,
 	agp_i810_alloc_memory,
 	agp_i810_free_memory,
diff --git a/sys/dev/pci/agpvar.h b/sys/dev/pci/agpvar.h
index 36f9d2de7ee..3646d0e9120 100644
--- a/sys/dev/pci/agpvar.h
+++ b/sys/dev/pci/agpvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: agpvar.h,v 1.28 2013/12/07 10:57:06 kettenis Exp $	*/
+/*	$OpenBSD: agpvar.h,v 1.29 2013/12/09 19:52:11 kettenis Exp $	*/
 /*	$NetBSD: agpvar.h,v 1.4 2001/10/01 21:54:48 fvdl Exp $	*/
 
 /*-
@@ -110,8 +110,6 @@ struct agp_methods {
 	void	(*bind_page)(void *, bus_addr_t, paddr_t, int);
 	void	(*unbind_page)(void *, bus_addr_t);
 	void	(*flush_tlb)(void *);
-	void	(*dma_sync)(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
-		    bus_size_t, int);
 	int	(*enable)(void *, u_int32_t mode);
 	struct agp_memory *
 		(*alloc_memory)(void *, int, vsize_t);