do a better job of setting up the PBM. Doesn't fix the PIO faults we're

seeing, I"m not convinced they're fixable any more.

2 files changed, 32 insertions, 5 deletions

diff --git a/sys/arch/sparc64/dev/schizo.c b/sys/arch/sparc64/dev/schizo.c
index d88a7f17409..3a6a867d58c 100644
--- a/sys/arch/sparc64/dev/schizo.c
+++ b/sys/arch/sparc64/dev/schizo.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: schizo.c,v 1.23 2006/06/01 19:12:45 jason Exp $	*/
+/*	$OpenBSD: schizo.c,v 1.24 2006/06/01 20:58:19 jason Exp $	*/
 
 /*
  * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
@@ -153,7 +153,7 @@ schizo_init(struct schizo_softc *sc, int busa)
 	struct schizo_pbm *pbm;
 	struct pcibus_attach_args pba;
 	int *busranges = NULL, nranges;
-	u_int64_t match;
+	u_int64_t match, reg;
 
 	pbm = (struct schizo_pbm *)malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT);
 	if (pbm == NULL)
@@ -216,6 +216,11 @@ schizo_init(struct schizo_softc *sc, int busa)
 
 	free(busranges, M_DEVBUF);
 
+	schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5);
+
+	/* clear out the bus errors */
+	schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL));
+
 	if (busa)
 		schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
 		   pbm, SCZ_PCIERR_A_INO, "pci_a");
@@ -223,8 +228,18 @@ schizo_init(struct schizo_softc *sc, int busa)
 		schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
 		   pbm, SCZ_PCIERR_B_INO, "pci_b");
 
-	schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL) |
-	    SCZ_PCICTRL_EEN | SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_DTO_INT);
+	reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL);
+	/* enable/disable error interrupts */
+	reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_SBH_INT;
+	reg &= ~SCZ_PCICTRL_DTO_INT;
+	/* enable bus arbiter for all pci slots */
+	reg |= SCZ_PCICTRL_ARB;
+	schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg);
+
+	reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG);
+	reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY |
+	    SCZ_PCIDIAG_D_INTSYNC);
+	schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);
 
 	/* double mapped */
 	schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, "ue");
diff --git a/sys/arch/sparc64/dev/schizoreg.h b/sys/arch/sparc64/dev/schizoreg.h
index 294d04ba0ea..5ee1c1d37e1 100644
--- a/sys/arch/sparc64/dev/schizoreg.h
+++ b/sys/arch/sparc64/dev/schizoreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: schizoreg.h,v 1.12 2006/06/01 19:12:45 jason Exp $	*/
+/*	$OpenBSD: schizoreg.h,v 1.13 2006/06/01 20:58:19 jason Exp $	*/
 
 /*
  * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
@@ -102,6 +102,8 @@ struct schizo_regs {
 #define	SCZ_PCI_IOMMU_CTXFLUSH		0x00218
 #define	SCZ_PCI_IMAP_BASE		0x01000
 #define	SCZ_PCI_ICLR_BASE		0x01400
+#define	SCZ_PCI_INTR_RETRY		0x01a00	/* interrupt retry */
+#define	SCZ_PCI_DMA_FLUSH		0x01a08	/* pci consistent dma flush */
 #define	SCZ_PCI_CTRL			0x02000
 #define	SCZ_PCI_AFSR			0x02010
 #define	SCZ_PCI_AFAR			0x02018
@@ -217,6 +219,16 @@ struct schizo_regs {
 
 #define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS"
 
+#define	SCZ_PCIDIAG_D_BADECC		(1UL << 10UL)	/* disable bad ecc */
+#define	SCZ_PCIDIAG_D_BYPASS		(1UL <<  9UL)	/* disable mmu bypass */
+#define	SCZ_PCIDIAG_D_TTO		(1UL <<  8UL)	/* disable trdy# timeout */
+#define	SCZ_PCIDIAG_D_RTRYARB		(1UL <<  7UL)	/* disable retry arb */
+#define	SCZ_PCIDIAG_D_RETRY		(1UL <<  6UL)	/* disable retry lim */
+#define	SCZ_PCIDIAG_D_INTSYNC		(1UL <<  5UL)	/* disable write sync */
+#define	SCZ_PCIDIAG_I_DMADPAR		(1UL <<  3UL)	/* invert dma parity */
+#define	SCZ_PCIDIAG_I_PIODPAR		(1UL <<  2UL)	/* invert pio data parity */
+#define	SCZ_PCIDIAG_I_PIOAPAR		(1UL <<  1UL)	/* invert pio addr parity */
+
 #define	SCZ_PBM_A_REGS			(0x600000UL - 0x400000UL)
 #define	SCZ_PBM_B_REGS			(0x700000UL - 0x400000UL)