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authorBrandon Creighton <bjc@cvs.openbsd.org>2001-03-01 07:37:18 +0000
committerBrandon Creighton <bjc@cvs.openbsd.org>2001-03-01 07:37:18 +0000
commit047e1e0c38ef8a21ec6e346db695fadcaebd2560 (patch)
tree8b9109a5df746589f0be9cfaab88cb9ce48e05ef /sys
parent38b04d62924eb4ea0b5f768f62e7cfb0282a13b9 (diff)
(all changes made behind #ifdef __vax__)
For the vax, write CSR0 in two steps instead of one. Why? DEC says so. This eliminates most (or all) of the le* timeout errors under heavy cpu/net usage. Fix from netbsd.
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/ic/am7990.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/sys/dev/ic/am7990.c b/sys/dev/ic/am7990.c
index 2ad72b6d600..b5c24362d31 100644
--- a/sys/dev/ic/am7990.c
+++ b/sys/dev/ic/am7990.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: am7990.c,v 1.20 2001/02/20 19:39:36 mickey Exp $ */
+/* $OpenBSD: am7990.c,v 1.21 2001/03/01 07:37:17 bjc Exp $ */
/* $NetBSD: am7990.c,v 1.22 1996/10/13 01:37:19 christos Exp $ */
/*-
@@ -674,9 +674,19 @@ am7990_intr(arg)
if ((isr & LE_C0_INTR) == 0)
return (0);
+#ifdef __vax__
+ /*
+ * DEC needs this write order to the registers, don't know
+ * the results on other arch's. Ragge 991029
+ */
+ isr &= ~LE_C0_INEA;
+ (*sc->sc_wrcsr)(sc, LE_CSR0, isr);
+ (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA);
+#else
(*sc->sc_wrcsr)(sc, LE_CSR0,
isr & (LE_C0_INEA | LE_C0_BABL | LE_C0_CERR | LE_C0_MISS | LE_C0_MERR |
LE_C0_RINT | LE_C0_TINT | LE_C0_IDON));
+#endif
if (isr & LE_C0_ERR) {
if (isr & LE_C0_BABL) {
#ifdef LEDEBUG