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author	Owain Ainsworth <oga@cvs.openbsd.org>	2009-03-05 22:51:33 +0000
committer	Owain Ainsworth <oga@cvs.openbsd.org>	2009-03-05 22:51:33 +0000
commit	14610802c50667e08386cd998c794795cc94418a (patch)
tree	576c17c2f5da765cb00e411bf56f3cad5bed572c /sys
parent	5899f1c3618e6db2f37f47ef99fa640ebdda5506 (diff)

Remove the stats_boxes counters and associated code from radeondrm.

They're really not all that useful.

Diffstat (limited to 'sys')

-rw-r--r--

sys/dev/pci/drm/radeon_cp.c

-rw-r--r--

sys/dev/pci/drm/radeon_drv.h

-rw-r--r--

sys/dev/pci/drm/radeon_irq.c

-rw-r--r--

sys/dev/pci/drm/radeon_state.c

143

4 files changed, 2 insertions, 193 deletions

diff --git a/sys/dev/pci/drm/radeon_cp.c b/sys/dev/pci/drm/radeon_cp.c
index 8c2dd6e6cc7..5add18e3047 100644
--- a/sys/dev/pci/drm/radeon_cp.c
+++ b/sys/dev/pci/drm/radeon_cp.c

@@ -226,8 +226,6 @@ radeon_do_pixcache_flush(drm_radeon_private_t *dev_priv)

u32 tmp;

int i;

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {

tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);

tmp |= RADEON_RB3D_DC_FLUSH_ALL;

@@ -257,8 +255,6 @@ radeon_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)

{

int i;

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

for (i = 0; i < dev_priv->usec_timeout; i++) {

int slots = (RADEON_READ(RADEON_RBBM_STATUS)

& RADEON_RBBM_FIFOCNT_MASK);

@@ -282,8 +278,6 @@ radeon_do_wait_for_idle(drm_radeon_private_t *dev_priv)

{

int i, ret;

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

ret = radeon_do_wait_for_fifo(dev_priv, 64);

if (ret)

return ret;

@@ -959,7 +953,6 @@ radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init)

dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;

- dev_priv->do_boxes = 0;

dev_priv->cp_mode = init->cp_mode;

/* We don't support anything other than bus-mastering ring mode,

@@ -1550,9 +1543,7 @@ radeon_freelist_get(struct drm_device *dev)

buf = dma->buflist[i];

buf_priv = buf->dev_private;

if (buf->file_priv == NULL || (buf->pending &&

- buf_priv->age <=

- done_age)) {

- dev_priv->stats.requested_bufs++;

+ buf_priv->age <= done_age)) {

buf->pending = 0;

return buf;

}

@@ -1561,7 +1552,6 @@ radeon_freelist_get(struct drm_device *dev)

if (t) {

DRM_UDELAY(1);

- dev_priv->stats.freelist_loops++;

}

@@ -1584,16 +1574,13 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)

dev_priv->last_buf = 0;

start = dev_priv->last_buf;

- dev_priv->stats.freelist_loops++;

for (t = 0; t < 2; t++) {

for (i = start; i < dma->buf_count; i++) {

buf = dma->buflist[i];

buf_priv = buf->dev_private;

if (buf->file_priv == 0 || (buf->pending &&

- buf_priv->age <=

- done_age)) {

- dev_priv->stats.requested_bufs++;

+ buf_priv->age <= done_age)) {

buf->pending = 0;

return buf;

}

@@ -1640,8 +1627,6 @@ radeon_wait_ring(drm_radeon_private_t *dev_priv, int n)

if (ring->space > n)

return 0;

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

if (head != last_head)

i = 0;

last_head = head;

diff --git a/sys/dev/pci/drm/radeon_drv.h b/sys/dev/pci/drm/radeon_drv.h
index 26cfb5d83a5..707f6e96bae 100644
--- a/sys/dev/pci/drm/radeon_drv.h
+++ b/sys/dev/pci/drm/radeon_drv.h

@@ -242,18 +242,6 @@ typedef struct drm_radeon_private {

int usec_timeout;

- struct {

- u32 boxes;

- int freelist_timeouts;

- int freelist_loops;

- int requested_bufs;

- int last_frame_reads;

- int last_clear_reads;

- int clears;

- int texture_uploads;

- } stats;

- int do_boxes;

int page_flipping;

u32 color_fmt;

@@ -411,14 +399,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,

struct drm_file *file_priv,

drm_radeon_kcmd_buffer_t *cmdbuf);

-/* Flags for stats.boxes

- */

-#define RADEON_BOX_DMA_IDLE 0x1

-#define RADEON_BOX_RING_FULL 0x2

-#define RADEON_BOX_FLIP 0x4

-#define RADEON_BOX_WAIT_IDLE 0x8

-#define RADEON_BOX_TEXTURE_LOAD 0x10

/* Register definitions, register access macros and drmAddMap constants

* for Radeon kernel driver.

@@ -1350,17 +1330,6 @@ do { \

* Misc helper macros

-/* Perfbox functionality only.

- */

-#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \

-do { \

- if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \

- u32 head = GET_RING_HEAD( dev_priv ); \

- if (head == dev_priv->ring.tail) \

- dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \

- } \

-} while (0)

#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \

do { \

drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \

diff --git a/sys/dev/pci/drm/radeon_irq.c b/sys/dev/pci/drm/radeon_irq.c
index d2effe4e4f8..2005ba9cadc 100644
--- a/sys/dev/pci/drm/radeon_irq.c
+++ b/sys/dev/pci/drm/radeon_irq.c

@@ -253,8 +253,6 @@ radeon_wait_irq(struct drm_device * dev, int swi_nr)

if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)

return 0;

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

DRM_WAIT_ON(ret, dev_priv, 3 * DRM_HZ,

RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);

diff --git a/sys/dev/pci/drm/radeon_state.c b/sys/dev/pci/drm/radeon_state.c
index 52eed840dc9..398870a39d0 100644
--- a/sys/dev/pci/drm/radeon_state.c
+++ b/sys/dev/pci/drm/radeon_state.c

@@ -54,9 +54,6 @@ int radeon_emit_state(drm_radeon_private_t *, struct drm_file *,

unsigned int);

int radeon_emit_state2(drm_radeon_private_t *, struct drm_file *,

drm_radeon_state_t *);

-void radeon_clear_box(drm_radeon_private_t *, int, int, int, int,

- int, int, int);

-void radeon_cp_performance_boxes(drm_radeon_private_t *);

void radeon_cp_dispatch_clear(struct drm_device *, drm_radeon_clear_t *,

drm_radeon_clear_rect_t *);

void radeon_cp_dispatch_swap(struct drm_device *);

@@ -796,114 +793,6 @@ static struct {

};

/* ================================================================

- * Performance monitoring functions

- */

-void

-radeon_clear_box(drm_radeon_private_t * dev_priv, int x, int y, int w,

- int h, int r, int g, int b)

- u32 color;

- RING_LOCALS;

- x += dev_priv->sarea_priv->boxes[0].x1;

- y += dev_priv->sarea_priv->boxes[0].y1;

- switch (dev_priv->color_fmt) {

- case RADEON_COLOR_FORMAT_RGB565:

- color = (((r & 0xf8) << 8) |

- ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));

- break;

- case RADEON_COLOR_FORMAT_ARGB8888:

- default:

- color = (((0xff) << 24) | (r << 16) | (g << 8) | b);

- break;

- }

- BEGIN_RING(4);

- RADEON_WAIT_UNTIL_3D_IDLE();

- OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));

- OUT_RING(0xffffffff);

- ADVANCE_RING();

- BEGIN_RING(6);

- OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));

- OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |

- RADEON_GMC_BRUSH_SOLID_COLOR |

- (dev_priv->color_fmt << 8) |

- RADEON_GMC_SRC_DATATYPE_COLOR |

- RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);

- if (dev_priv->sarea_priv->pfCurrentPage == 1) {

- OUT_RING(dev_priv->front_pitch_offset);

- } else {

- OUT_RING(dev_priv->back_pitch_offset);

- }

- OUT_RING(color);

- OUT_RING((x << 16) | y);

- OUT_RING((w << 16) | h);

- ADVANCE_RING();

-void

-radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv)

- /* Collapse various things into a wait flag -- trying to

- * guess if userspase slept -- better just to have them tell us.

- */

- if (dev_priv->stats.last_frame_reads > 1 ||

- dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

- }

- if (dev_priv->stats.freelist_loops) {

- dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

- }

- /* Purple box for page flipping

- */

- if (dev_priv->stats.boxes & RADEON_BOX_FLIP)

- radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);

- /* Red box if we have to wait for idle at any point

- */

- if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)

- radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);

- /* Blue box: lost context?

- */

- /* Yellow box for texture swaps

- */

- if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)

- radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);

- /* Green box if hardware never idles (as far as we can tell)

- */

- if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))

- radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);

- /* Draw bars indicating number of buffers allocated

- * (not a great measure, easily confused)

- */

- if (dev_priv->stats.requested_bufs) {

- if (dev_priv->stats.requested_bufs > 100)

- dev_priv->stats.requested_bufs = 100;

- radeon_clear_box(dev_priv, 4, 16,

- dev_priv->stats.requested_bufs, 4,

- 196, 128, 128);

- }

- memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));

-/* ================================================================

* CP command dispatch functions

@@ -922,8 +811,6 @@ radeon_cp_dispatch_clear(struct drm_device * dev, drm_radeon_clear_t * clear,

RING_LOCALS;

DRM_DEBUG("flags = 0x%x\n", flags);

- dev_priv->stats.clears++;

if (dev_priv->sarea_priv->pfCurrentPage == 1) {

unsigned int tmp = flags;

@@ -1412,11 +1299,6 @@ radeon_cp_dispatch_swap(struct drm_device *dev)

RING_LOCALS;

DRM_DEBUG("\n");

- /* Do some trivial performance monitoring...

- */

- if (dev_priv->do_boxes)

- radeon_cp_performance_boxes(dev_priv);

/* Wait for the 3D stream to idle before dispatching the bitblt.

* This will prevent data corruption between the two streams.

@@ -1490,13 +1372,6 @@ radeon_cp_dispatch_flip(struct drm_device *dev)

DRM_DEBUG("pfCurrentPage=%d\n",

dev_priv->sarea_priv->pfCurrentPage);

- /* Do some trivial performance monitoring...

- */

- if (dev_priv->do_boxes) {

- dev_priv->stats.boxes |= RADEON_BOX_FLIP;

- radeon_cp_performance_boxes(dev_priv);

- }

/* Update the frame offsets for both CRTCs

BEGIN_RING(6);

@@ -1728,8 +1603,6 @@ radeon_cp_dispatch_texture(struct drm_device *dev, struct drm_file *file_priv,

return EINVAL;

}

- dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;

/* Flush the pixel cache. This ensures no pixel data gets mixed

* up with the texture data from the host data blit, otherwise

* part of the texture image may be corrupted.

@@ -2189,8 +2062,6 @@ radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)

LOCK_TEST_WITH_RETURN(dev, file_priv);