Increase timeout on the processor bus when running without snooping enabled.

This lets 40MHz MVME197LE boards run with instruction cache enabled, and also
fixes random instruction faults occuring on the early 50MHz models.

2 files changed, 24 insertions, 29 deletions

diff --git a/sys/arch/mvme88k/dev/busswreg.h b/sys/arch/mvme88k/dev/busswreg.h
index a2c21c450d7..817383b11c4 100644
--- a/sys/arch/mvme88k/dev/busswreg.h
+++ b/sys/arch/mvme88k/dev/busswreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: busswreg.h,v 1.10 2007/12/13 18:50:10 miod Exp $ */
+/*	$OpenBSD: busswreg.h,v 1.11 2007/12/25 20:23:02 miod Exp $ */
 
 /*
  * Memory map for BusSwitch chip found in mvme197 boards.
@@ -113,16 +113,12 @@
 #define BS_BTIMER_PBT64		0x01	/* Processor Bus Timout, 64 usec */
 #define BS_BTIMER_PBT256	0x02	/* Processor Bus Timout, 256 usec */
 #define BS_BTIMER_PBTD		0x03	/* Processor Bus Timout, disable */
-#define BS_BTIMER_SBT8		(0x00 << 2)	/* System Bus Timout, 8 usec */
-#define BS_BTIMER_SBT64		(0x01 << 2)	/* System Bus Timout, 64 usec */
-#define BS_BTIMER_SBT256	(0x02 << 2)	/* System Bus Timout, 256 usec */
-#define BS_BTIMER_SBTD		(0x03 << 2)	/* System Bus Timout, disable */
-
-/* Prescaler Adjust values */
-#define BS_PADJUST_50	0xce	/* 50 MHz clock */
-#define BS_PADJUST_40	0xd8	/* 40 MHz clock */
-#define BS_PADJUST_33	0xdf	/* 33 MHz clock */
-#define BS_PADJUST_25	0xe7	/* 25 MHz clock */
+#define	BS_BTIMER_PBT_MASK	0x03
+#define BS_BTIMER_SBT8		0x00	/* System Bus Timout, 8 usec */
+#define BS_BTIMER_SBT64		0x04	/* System Bus Timout, 64 usec */
+#define BS_BTIMER_SBT256	0x08	/* System Bus Timout, 256 usec */
+#define BS_BTIMER_SBTD		0x0c	/* System Bus Timout, disable */
+#define	BS_BTIMER_SBT_MASK	0x0c
 
 /* ROM Control Register bit definitions */
 #define BS_ROMCR_WEN0	0x0100
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
index 7d706dab07e..714a0706ca2 100644
--- a/sys/arch/mvme88k/mvme88k/m88110.c
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.c,v 1.53 2007/12/22 17:13:53 miod Exp $	*/
+/*	$OpenBSD: m88110.c,v 1.54 2007/12/25 20:23:04 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * All rights reserved.
@@ -249,8 +249,10 @@ m88110_cpu_number(void)
 void
 m88110_initialize_cpu(cpuid_t cpu)
 {
-	extern int cpuspeed;
 	u_int ictl, dctl;
+#ifndef MULTIPROCESSOR
+	u_int8_t btimer;
+#endif
 	int i;
 	int procvers = (get_cpu_pid() & PID_VN) >> VN_SHIFT;
 
@@ -265,24 +267,21 @@ m88110_initialize_cpu(cpuid_t cpu)
 	/* clear PATCs */
 	patc_clear();
 
-	ictl = BATC_512K | CMMU_ICTL_DID | CMMU_ICTL_CEN | CMMU_ICTL_BEN;
-
+#ifndef MULTIPROCESSOR
 	/*
-	 * 40MHz MVME197LE boards need to run with their instruction cache
-	 * disabled, otherwise they get random bus errors and the kernel
-	 * eventually freezes. Unfortunately this makes them perform at
-	 * about the speed of a fictitious 25MHz board with I$ enabled.
-	 *
-	 * This happens with version 4 and version 5 processors (reporting
-	 * themselves as version 0xb and 0xf in dmesg) and BusSwitch
-	 * revision 1. However, 50MHz boards with the same BusSwitch
-	 * revision work nicely.
-	 *
-	 * (There is probably a better way to work around this problem,
-	 *  but I am not aware of it -- miod)
+	 * Kernels running without snooping enabled (i.e. without
+	 * CACHE_GLOBAL set in the apr in pmap.c) need increased processor
+	 * bus timeout limits, or the instruction cache might not be able
+	 * to fill or answer fast enough.  This is especially critical on
+	 * 40MHz boards, while some 50MHz boards can run without this
+	 * timeout change... but better be safe than sorry.
 	 */
-	if (cpuspeed == 40)
-		ictl &= ~CMMU_ICTL_CEN;
+	btimer = *(volatile u_int8_t *)(BS_BASE + BS_BTIMER);
+	btimer = (btimer & ~BS_BTIMER_PBT_MASK) | BS_BTIMER_PBT64;
+	*(volatile u_int8_t *)(BS_BASE + BS_BTIMER) = btimer;
+#endif
+
+	ictl = BATC_512K | CMMU_ICTL_DID | CMMU_ICTL_CEN | CMMU_ICTL_BEN;
 
 	/*
 	 * 88110 errata #10 (4.2) or #2 (5.1.1):